`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`SAMSUNG ELECTRONICS CO, LTD.,
`Petitioner,
`
`V.
`
`NETLIST, INC.,
`Patent Owner.
`
`IPR2022-00996
`Case No.
`Patent No. 11,016,918
`
`DECLARATION OF DR. WILLIAM HENRY MANGIONE-SMITH
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`I declare that all statements made here on my own knowledge are true and that all
`statements made contain information and belief are believed to be true, and further,
`that these statements were made with the knowledge that willful
`false statements
`and the like so made are punishable by fine or imprisonment, or both, under
`Section 1001 or Title 18 of the United States Code.
`
`Date:
`
`Dr. William Henry Mangione-Smith
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`DECLARATION OF DR. WILLIAM HENRY MANGIONE-SMITH, PH.D
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`I, William Henry Mangione-Smith, do hereby declare as follows:
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`INTRODUCTION
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`I have been retained on behalf of Netlist, Inc. (“Patent Owner”) as an
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`expert to evaluate certain technical aspects of U.S. Patent No. 11,016,918 (“the ’918
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`patent”), and to provide certain related opinions. I am personally knowledgeable
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`about the matters stated herein and am competent to make this declaration.
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`I understand
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`that Patent Owner will submit
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`this declaration
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`(“Declaration”) in connection with IPR2022-00996 (“Proceeding”), which I have
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`been informed is an inter partes review (IPR) proceeding before the Patent Trial and
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`Appeal Board challenging the patentability of claims 1-30 of the ’918 patent.
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`I receive compensation at my normal consulting rate for my time
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`working on this matter, plus expenses. I have no financial interest in Patent Owner
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`or in the patents involved in this litigation, and my compensation is not dependent
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`on the outcome of this litigation. The opinions I present are due to my own judgment.
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`All “EX10XX” cites herein are to exhibits I understand were submitted
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`by Petitioner and all “EX20XX” cites herein are to exhibits I understand have or will
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`be submitted by the Patent Owner in this Proceeding. All “Appendix _” cites
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`followed by a letter are to appendices to this Declaration. All citations to “Section
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`XX” are internal citations to the sections of this Declaration. All citations to
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`“Paragraph XX” are internal citations to the paragraphs of this Declaration.
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` BACKGROUND AND QUALIFICATIONS
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`I received my Bachelor of Science in Engineering in 1987 and my
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`Master of Science in Engineering in 1992, both from the University of Michigan. I
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`also received my Doctorate in Engineering from the University of Michigan.
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`I am a Member of the Association for Computing Machinery (ACM)
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`and the Institute of Electrical and Electronics Engineers (IEEE). I've served as the
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`Program Chair and the General Chair for the 26th and 36th International
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`Symposiums on Microarchitecture, respectively. I have served as the Associate
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`Editor of IEEE Transactions on Computers, the Associate Editor of ACM
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`Transactions on Embedded Computing Systems, and the Associate Editor of IEEE
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`Computer. I have served on various Program Committees, including ISCA, Network
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`Processors Workshop, Complexity-Effective Design, and Workshop on
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`Mediaprocessors and DSP. I have published numerous journal articles on
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`computing, given 49 conference presentations, and authored several book chapters
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`and magazine articles on such issues. I am listed as an inventor on 121 patents nearly
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`all of which are related to microprocessor and memory technology, and am listed on
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`more than 200 pending patent applications.
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`I have an extensive background working with electronics and computer
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`patents. I currently work as a consultant on intellectual property matters, including
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`reviewing and valuing patents and patent portfolios for Phase Two LLC, and I have
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`held this position since 2009. Prior to that, from 2005-2008, I was employed at
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`Intellectual Ventures, working on patent valuation, with a focus on computer patents,
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`and outbound licensing in consumer electronics, among other focuses. During my
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`time at Intellectual Ventures the company developed intellectual property that
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`resulted in several successful startups. I was not involved in any of the litigation
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`while I was at Intellectual Ventures, focusing instead on developing new ideas. From
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`1995-2005, I worked as an Assistant and an Associate Professor in electrical
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`engineering at the University of California, Los Angeles. From 1993-1995, I worked
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`as a Systems Architect for the Motorola Wireless Data Group, where I worked on
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`designing and developing the microprocessor for an early smartphone. From 1991-
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`1992, I worked with Motorola Corporate research, focusing on parallel computer
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`performance monitoring and low-power processor architecture. Finally, from 1986-
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`1987, I worked as a Software Architect at Chrysler Corporation, where I operated
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`supercomputers related to designing, testing, and simulating car designs. I have been
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`accepted by various courts as an expert in the fields of computer engineering,
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`including computer architecture and microarchitecture.
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`A current curriculum vitae is attached as Appendix A and includes the
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`above listed credentials, additional background and information, and my experience
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`as an expert witness from the previous four years.
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` MATERIALS CONSIDERED
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`I have considered information from various sources in forming my
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`opinions. Besides drawing from my decades of experience in the computer industry,
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`I have reviewed the Petition and supporting declaration from Dr. Wolfe, the ’918
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`patent and its file history, the prior art discussed below, Dr. Wolfe’s deposition
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`transcript, along with the other documents and references cited here.
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`I have also reviewed the declaration submitted by Dr. Khatri in support
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`of the preliminary patent owner response submitted in this Proceeding. Because of
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`significant overlaps with points that I make throughout my report, in some instances
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`I have adopt his positions as my own.
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` LEGAL STANDARDS
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`I have relied on instructions from counsel as to the applicable legal
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`standards to use in arriving at my opinions in this Declaration. I am relying only on
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`instructions from Netlist’s attorneys for these legal standards.
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`I understand that a patent claim is unpatentable and invalid if the subject
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`matter of the claim as a whole would have been obvious to a person of ordinary skill
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`in the art of the claimed subject matter, as of the time of the invention at issue.
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`I have been informed and understand that a patent claim can be
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`considered to have been obvious to a person of ordinary skill in the art at the time of
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`the alleged invention. This means that, even if all the requirements of a claim are not
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`found in a single prior art reference, the claim is not patentable if the differences
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`between the subject matter in the prior art and the subject matter in the claim, would
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`have been obvious to a person of ordinary skill in the art at the time of the alleged
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`invention.
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`I understand that the following factors must be evaluated to determine
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`whether the claimed subject matter is obvious: (1) the scope and content of the prior
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`art; (2) the difference or differences, if any, between each claim of the patent and the
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`prior art; and (3) the level of ordinary skill in the art at the time the patent was filed.
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`I have been informed and understand that the teachings of two or more
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`references may be combined if such a combination would have been obvious to one
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`having ordinary skill in the art. In determining whether a combination based on
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`multiple references would have been obvious, it is appropriate to consider, among
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`other factors: (1) whether the teachings of the prior art references disclose known
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`concepts combined in familiar ways, and when combined, would yield predictable
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`results; (2) whether a person of ordinary skill in the art could implement such a
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`combination, and would see the benefit of doing so; (3) whether the claimed
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`elements represent one of a limited number of known design choices, and would
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`have a reasonable expectation of success by those skilled in the art; (4) whether a
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`person of ordinary skill would have recognized a reason to combine known elements
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`in the manner described in the claim; (5) whether there is some teaching or
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`suggestion in the prior art to make the modification or combination of elements
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`claimed in the patent; and (6) whether the claimed invention applies a known
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`technique that had been used to improve a similar device or method in a similar way.
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`I have been informed and understand that one of ordinary skill in the
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`art has ordinary creativity, and is not an automaton.
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` I have been informed and understand that in considering obviousness,
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`it is important not to determine obviousness using the benefit of hindsight derived
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`from the patent being considered.
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` THE ’918 PATENT
` The ’918 patent generally relates to memory modules. In one preferred
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`embodiment, the memory system 1010 comprises a PCB 1020 having DRAM
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`(volatile) memory subsystem 1030 and NAND (nonvolatile) memory subsystem
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`1040, both of which may be operatively coupled to a controller unit 1062. See, e.g.,
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`EX1001, Fig. 12 (reproduced below); see also id., 21:14-23.
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` As shown in the embodiment of FIG. 12, the controller 1062 includes
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`a microcontroller unit (MCU) 1060 and a logic element (comprising a field-
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`programmable gate array (FPGA)) 1070. See id., 23:1-22, 24:35-37. However, in
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`other embodiments the FPGA 1070 may be integrated with the microcontroller 1060.
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`See id., 23:19-22, Fig. 14. The ’918 patent explains that the microcontroller 1060
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`provides memory management and controls data transfer between the non-volatile
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`memory 1040 and volatile memory 1030. See id., 24:38-41. The FPGA logic
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`element 1070 provides signal level translation and address translation between the
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`volatile memory and non-volatile memory. “The logic element 1070 can provide
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`signal level translation between the volatile memory elements 1032 (e.g., 1.8V
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`SSTL-2 for DDR2 SDRAM elements) and the non-volatile memory elements 1042
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`(e.g., 3V TTL for NAND flash memory elements),” and “address/address translation
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`between the volatile memory subsystem 1030 and the non-volatile memory
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`subsystem 1040.” Id., 24:48-56.
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` The ’918 patent further discloses that the PCB includes a DIMM
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`interface 1022, which comprises edge connections via which it provides “power
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`voltage as well as data, address and control signals between the memory system 1010
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`and [a] host system.” Id., 22:1-6.
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` The ’918 patent also discloses a voltage monitor circuit 1050 on the
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`PCB that “monitors the voltage supplied by the host system via the [DIMM]
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`interface 1022.” Id., 25:8-10, Fig. 12. Upon detecting an abnormal condition, “the
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`voltage monitor circuit 1050 may transmit a signal to the controller 1062 indicative
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`of the detected condition.” Id., 25:11-14. The controller 1062 may in turn transmit
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`a signal to switch 1052 for it to operatively couple the volatile memory and the non-
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`volatile memory, thereby effecting a transition from the first state to the second state.
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`See id., 25:15-20. In certain embodiments, the voltage monitor circuit 1050 may be
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`part of the controller 1062. See id., 25:27-31.
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` SKILL LEVEL OF A POSITA
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`I note that Dr. Wolfe contends that a person having ordinary skill in the
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`art (“POSITA”) in the field of the ’918 patent in 2008 would have been someone
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`with an advanced degree in electrical or computer engineering, or a related field, and
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`two years working or studying in the field of design or development of memory
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`systems, or a bachelor’s degree in such engineering disciplines and at least three
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`years of work experience in the field. See EX1003, ¶ 67.
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` For purposes of the opinions I set forth herein, and to simplify the
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`issues, I have adopted that understanding as to the level of skill in the relevant field
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`at the time of the invention, noting that none of the opinions I express herein would
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`change if a somewhat higher or somewhat lower level of skill were adopted.
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`However, I reserve the right to separately analyze the appropriate level of skill at the
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`time of the invention, and to propose a different ordinary level of skill in the art
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`based on that analysis.
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` THE PRIOR ART
` The Petition challenges the claims of the ’918 patent based primarily
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`on U.S. Patent Publication No. 2006/0174140 (“Harris”), certain JEDEC published
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`standards for Fully Buffered DIMM (FBDIMM) memory modules (EX1027 and
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`EX1028), U.S. Patent No. 7,724,604 (“Amidi”), U.S. Patent Publication No.
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`2006/0080515 (“Spiers”), and U.S. Patent No. 6,856,556 (“Hajeck”). Below I
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`provide a brief overview of those references.
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`A. Harris (EX1023)
` U.S. Patent Publication No. 2006/0174140 to Harris et al. (“Harris”),
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`titled “Voltage Distribution System and Method for a Memory Assembly,” discloses
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`a “memory assembly module including an on-board voltage regulator for converting
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`an externally supplied voltage into appropriate voltage levels for powering memory
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`devices of the memory assembly module.” EX1023, Title, Abstract, FIG. 1A.
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` As Harris explains, conventional memory modules, such as industry
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`standard Dual In-line Memory Modules (DIMM) “are provided with power supply
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`rails (on a relatively large number of pins) that are powered from system board or
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`main board voltage sources, and are specific to the memory technology.” Id., [0002].
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`Harris, on the other hand, aims to “provide[] a technology-independent voltage
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`distribution scheme for memory devices wherein system board power supply and
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`associated voltage plane(s) are eliminated.” Id., [0019]. Using a fully-buffered
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`DIMM as an example, Harris achieves its goal by “replacing the[] power supply
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`interface pins with … +12V pins (from an external power source), with local
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`conversion to VDD (to DRAM) and VCC (to buffer/logic) being added.” Id., [0012].
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`In other words, instead of obtaining power from the host via power
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`supply interface pins on the interface that fits into a corresponding memory slot in a
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`host system, Harris’ design derives its power from an external power source that is
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`subsequently converted to the appropriate voltage levels depending on the design.
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`See id., [0012]; [0016] (“voltage is supplied to a memory board assembly from an
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`external source, e.g., an unregulated source generating fairly high voltages
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`(illustratively, at +12V) with a wide tolerance. The voltage distribution method then
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`involves locally converting the supply voltage using an on-board VRM to generate
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`appropriate levels of voltage for powering on-board memory devices. … [T]he local
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`voltage levels preferably depend on the application….”).
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`In an alternative embodiment, more than one voltage source may be
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`provided “wherein each VRM is operable with an independent voltage supply path
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`for locally converting an external supply voltage into appropriate local voltage
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`levels.” Id., [0014]. The embodiment utilizes multiple VRMs “120-1 through 120-
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`K, [which] refer to K supply voltage paths which may be coupled to various voltage
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`sources provided within the electronic system (e.g., a computer system).” Id. This
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`embodiment contemplates one voltage regulator module per external voltage source
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`and does not contemplate multiple voltage regulator modules for a single voltage
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`source. In this embodiment, a “logic module 124 is provided for selecting among
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`the plurality of like voltage outputs from the VRMs 122-K in order to energize the
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`Vdd and Vcc paths 108, 106, respectively.” Id., [0015].
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` FBDIMM Standard (EX1027 & EX1028)“JESD82-20” (EX1027) is
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`the JEDEC specification for the Advanced Memory Buffer (AMB) of a fully-
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`buffered DIMM module (FBDIMM). JESD82-20 describes
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`the AMB as
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`“responsible for handling FBD channel and memory requests to and from the local
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`DIMM and for forwarding requests to other DIMMs on the FBD channel.” JESD82-
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`20 at 1. JESD82-20 describes the power supplies to the AMB.
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`(EX1027, p. 83)
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`“JESD205” (EX1028) is the JEDEC specification that “defines the
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`electrical and mechanical requirements for 240-pin, PC2-4200/PC2-5300/PC2-
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`6400, 72 bit-wide, Fully Buffered Double Data Rate Synchronous DRAM Dual In-
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`Line Memory Modules (DDR2 SDRAM FB-DIMMs).” EX1028, 9. JESD205 notes
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`the following supply voltages to the FBDIMM via the FBDIMM pins.
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`(EX1028, p.11)
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` FBDIMM uses packetized serial signaling to exchange data, address
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`and control information with the host. This contrasts with common DIMM formats
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`like RDIMMs, UDIMMs and SODIMMs. This is evident from the pinout of the
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`DIMM. As such, the AMB receives data, address, and control information, decodes
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`it and generates the data, address, and control signals needed by the DDR2
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`SDRAMs. This can be seen from the fact that in the pin description for AMB, there
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`are dedicated pins for data, address or control under the heading for “FB-DIMM
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`Channel Signals” (i.e., signals exchanged with between the AMB and the host).
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`Instead, the signals received from the host are denoted as PS[9:0] and its complement
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`PS[9:0]_bar; and the signals sent to the host are PN[13:0] and their complement
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`PN[13:0]_bar.
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`(EX1028, p. 29)
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` Signals such as DQ[63:0], A[15:0], BA[2:0], RAS, RAS bar, CAS,
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`CAS_bar, WE, WE_bar, CS, CS_bar are all under the heading “DDR2 Interface
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`Signals,” and are signals exchanged between the AMB and the DDR2 SDRAMs.
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` As Intel’s presentation indicates, these signals are generated within the
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`AMB after deserializing and decoding the serialized packets (PS[9:0]) from the host.
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`(Note, Intel was a key proponent of the FBDIMM technology).
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`(EX2101, p.5)
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` As such, the information the AMB receives is decoded and used to
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`generate the data, address and control signals to be sent on dedicated wires to
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`SDRAMs. This is further confirmed by datasheets for AMBs by component
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`suppliers such as IDT, which shows the differential signaling PS[9:0] and
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`PS[9:0]_bar pass through a series logic and control blocks to generate the data,
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`control and address signals for SDRAMs. See, e.g., EX2039, p.2.
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`B. Amidi (EX1024)
` U.S. 7,724,604 to Amidi et al. (“Amidi”) relates to “Clock and power
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`fault detection for memory modules.” EX1024, Title. Amidi provides a way of
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`“keeping data in volatile memory even when a surrounding system loses power” or
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`“suffers some form of error which causes a clock to malfunction.” Id. at 1:28-33. In
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`one embodiment, Amidi attempts to solve this problem by combining a “battery,
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`battery regulation circuitry, volatile memory, memory control state machine,
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`controller, clock detection circuit and voltage detection circuit.” Id., Abstract, 2:27-
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`39; see also FIG. 4.
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` Amidi’s disclosed structure includes a “[p]ower management block
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`500, include[ing] the actual power management module 510, an incoming system
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`supply 520, an incoming battery supply 530, and an outgoing memory power supply
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`540.” Id., 4:16-19; FIG 5. This power management block 500 is “used to attempt to
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`ensure a stable power supply even in the face of disruptions in system supply 520.”
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`Id., 4:19-22.
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` Power management block 600, depicted in FIG 6, provides an example
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`implementation of the internals of power management block 500. Id., 4:23-27. The
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`block 600 includes circuitry related to powering and managing battery 630,
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`including charging circuitry 620, discharging circuitry 635, gas gauge circuitry. Id.,
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`4:30-35. Battery 630’s output is provided to a boost converter 680, boost/buck
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`converter 690, and buck converter 640 when enabled by signal 670. Id., 4:35-39.
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`When enabled, buck converter 640 “produces battery power 650 as an input to power
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`switch multiplexer 655,” which “switch[es] between battery power 650 and system
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`supply 605 based on a signal 670.” Id., 4:39-43.
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`“Signal 670 is controlled by voltage supervisory block 665, which
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`receives system supply 605 and a reference voltage 675, and compares the two.”
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`Power switch multiplexer 655 chooses system supply 605 as a source for memory
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`supply 660 unless it falls below reference voltage 675. Id., 4:46-52.
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` Thus, at both a high-level and in its most specific embodiments, Amidi
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`tailored to the problem of keeping volatile memory powered when there is an
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`undervoltage condition. It achieves this by including a backup battery on the
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`memory module that is used only when the supply voltage falls below a particular
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`voltage level.
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`C.
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`Spiers (EX1025)
` U.S. 2006/0080515 to Spiers et al. (“Spiers”) relates to “Non-Volatile
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`Memory Backup for Network Storage System.” EX1025, p. 1 (title). Spiers aims
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`to reduce the amount of time it takes to report data that is written into a storage media
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`while minimizing the risk of data loss. See id., [0003].
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` To achieve its objective, Spiers provides a backup storage system to the
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`main storage device (such as a hard disk drive). See id., [0007]-[0008], Fig. 3. Spiers
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`describes its implementation with reference to network attached storage (NAS)
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`devices. See id., [0029], Fig. 1. The NAS device “receive[s] data from applications
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`104, and acknowledge back to the application 104 that the data is securely stored at
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`the NAS device 108, before the data is actually stored on storage media located
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`within the NAS 108.” Id., [0030]. This allegedly improves the NAS’s performance
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`as the NAS device can report that the data has been stored without waiting for the
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`data to be actually stored at the storage media. See id., [0030]-[0031], Figs. 2-3.
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`Spiers achieves this by sending a command to the backup device to store the data
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`and reports the data as having been stored if the backup device reports that that data
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`is store. See id., [0040], Fig. 6.
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`In addition to components that interface with the network, Spiers’ NAS
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`device includes a main storage device 140 with write-back cache and a backup
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`device 144, as shown in FIG. 3 above. See id., [0031]-[0032].
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` Spiers’ backup storage device 144 includes a volatile memory (such as
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`SDRAM), a non-volatile memory (such as a NAND flash), and a processor. See id.,
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`[0007], [0010], [0032], [0036], Fig. 4. The processor is “for causing a copy of data
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`provided to the [main] storage device to be provided to the [backup] storage device
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`volatile memory, and in the event of a power interruption, moving the data from the
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`[backup] data storage device volatile memory to the [backup] data storage device
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`non-volatile memory.” Id. In this manner, the data written to main storage’s write-
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`back cache would be retained even in the event of a power interruption, which in
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`turn reduces the risk of data loss. See id., [0007], [0034]. A high-level block diagram
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`for the backup device is shown in Figure 4.
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` Spiers explains that in the example backup device 144, there exists an
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`interface 152 “utilized to communicate with [a] storage controller 132” shown in
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`Figure 3. Id., [0036]. The interface 152 is connected to a processor 156 in the
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`backup device 144, and the processor “controls operations within the backup device
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`144.” Id. Connected to the processor 156 are volatile memory 160 (e.g., SDRAM)
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`and non-volatile memory 164 (e.g., flash). Id. The backup device 144 also includes
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`a power supply 168, which is used “upon detecting a power failure” to supply power
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`for moving data from the volatile memory 160 to the non-volatile memory 164. Id.
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`“After the data from the volatile memory 160 is stored in the non-volatile memory
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`164, the processor 156 shuts down the backup device 144.” Id.
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` One example of a backup power supply 168 is a capacitor array, which
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`is “charged when the backup device 144 is powered up.” Id. In the event of a power
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`interruption, “the backup device 144 receives power from the capacitors when
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`moving the data. After the data is securely stored in the non-volatile memory 164,
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`the power is switched off from the capacitor(s).” Id.
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` Spiers’ Figure 5 illustrates an example of such an implementation
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`which is reproduced below with the annotations included in the Petition. A red box
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`has been added around the components that correspond to the backup power supply
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`168 in Figure 4. See Petition at 83.
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` NAND Flash module 194, SDRAM module 190, processor 198 and 64-
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`bit PCI interface 172 correspond respectively to the non-volatile memory 164,
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`volatile memory 160, processor 156 and interface 152 of Figure 4. See EX1025,
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`[0037].
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` Spiers references only two voltage regulators: (1) the 5V-to-3.3V
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`regulator 184, and (2) regulator 206 that outputs 1.8V “required for the [processor]
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`core.” Id., [0037], Fig. 5.
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`In Figure 5, the power supply includes two 50F super capacitors
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`connected in a parallel. See id., [0037]. “The capacitors 176 are connected to a
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`diode 180[,] a voltage regulator 184, and a charger 186.” Id. The charger 186 draws
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`power from the PCI interface and “charge[s] the capacitors.” Id. “[I]n the event of
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`a power failure[,] the capacitors are used as the power source to power the backup
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`device 144 when moving data from the volatile memory to the non-volatile
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`memory.” Id.; see also Fig. 5 (showing “+5V_PCI Detector” block).
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`D. Hajeck (EX1038)
` U.S. 6,856,556 to Hajeck (“Hajeck”) uses a charge pump in a storage
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`subsystem (such as a flash memory card) as a backup power supply when power
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`signals from an associated host system is interrupted. EX1038, Abstract. In
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`response to detecting such an interruption, a busy signal is asserted to block the host
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`system from performing write operations to the storage subsystem. Id. In turn, the
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`backup, regulated power provided by the charge pump provides sufficient power for
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`the controller to complete all outstanding operations. Id. Such a setup reduces the
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`incidences of “data loss, data corruption, and circuitry damage caused by
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`interruptions and other irregularities in the power signal supplied by the host
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`system.” EX1038, 1:15-18, 1:34-36, 1:49-61 (“In addition to providing backup
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`power, the charge pump circuit protects the controller from potential damage caused
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`by power surges and spikes”), 1:62-2:7 (with the disclosed charge pump based
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`design, “[t]he likelihood that data will be lost as the result of the power signal
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`anomaly is …. significantly reduced”).
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` CLAIM CONSTRUCTION
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`I note that the term “memory module” appears in the preamble of each
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`of the independent claims of the ’918 patent, and that this term provides an
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`antecedent basis for the same term in the body of the text. See EX1001, Claims 1,
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`16, 23.
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`I understand that the District Court found that the preamble was limiting
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`because “a skilled artisan would understand a ‘memory module’ is distinct from, and
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`has essential structural requirements not necessarily found in, other modular
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`computer accessories. That includes the structure necessary to connect to a memory
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`controller.” EX2032, 28. I understand that the district court made this ruling after
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`reviewing the entire specification and based its ruling on the specification’s
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`disclosures. For instance, the specification states in the Overview section that the
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`memory module is particularly “couplable to a memory controller of a host
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`system.” EX1001, 3:66–67 (emphasis added); see also id., 1:66–67 (“[t]he present
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`disclosure relates generally to computer memory devices”).
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`I also note that Dr. Wolfe testified that the term “memory modules”
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`typically refers to “main memory modules,” which “are designed to connect to the
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`primary memory controller for the purpose of the holding general purpose code
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`and data in a computer system.” EX2030, 123:14-25. I agree, and in my experience,
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`at the time of the invention and in the context of the ‘918 patent, the term “memory
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`module” would be understood by a POSITA to refer to a module that is to be inserted
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`into a dedicated memory slots and that includes structures necessary to connect to a
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`memory controller for use as memory. See ‘918, 3:66-67; see also below.
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`EX2034 (Memory Systems), at 319.
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` ANALYSIS OF GROUNDS 1-3
`A. Harris Does Not Disclose a Memory Module Having a PCB
`Interface that Receives Voltage/Power from a Host System
` Harris describes an on-board voltage regulator module “for converting
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`an externally supplied voltage level available on external source path 104 into
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`appropriate local voltage levels ….” EX1023, [0010] (emphasis added). This
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`external voltage source is shown in FIG. 1A, reproduced below.
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`I note that Samsung cites to Figure 1A, [0010], [0012] and [0019] to
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`support its assertion that power is exchanged via the PCB interface between the
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`memory module and the host. But those citations clearly and consistently disclose
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`that Harris derives its power from an “external voltage source.” See Harris, Fig. 1A,
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`[0010], [0012], [0019].
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` For instance, Harris describes an on-board voltage regulator module
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`“for converting an externally supplied voltage level available on external source path
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`104 into appropriate local voltage levels.” Id., [0010]; see also id., [0016] (“voltage
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`is supplied to a memory board assembly from an external source, e.g., an unregulated
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`source generating fairly high voltages (illustratively, at +12V) with a wide
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`tolerance”). An external power source is one provided outside the system board.
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`It also notes that “a standard FBD module requires 28 VDD pins … and
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`8 VCC pins”1 but suggests “replacing the[] power supply interface pins with as few
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`as six +12V pins (from an external power source).” Id., [0012]. Notably, Harris does
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`not describe the 12V pins as “interface pins.”
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` Paragraph 19 of Harris, likewise, describes how Harris’s method
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`“eliminated” “system board power supply and associated voltage plane(s).”
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`Id.,[0019];see also id. (“Cost savings may include, for example, elimination of
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`1 The reference to “28 VDD pins” is either a typo or the JEDEC specification adopted
`fewer VDD pins.
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`system-board specific power supply or regulator output”), (“reduction in the pin
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`count on DIMM connector to system