United States Patent (19)
`Lau et al.
`
`IIIHIIII IIII
`USOO5592173A
`11
`Patent Number:
`5,592,173
`45) Date of Patent:
`Jan. 7, 1997
`
`54). GPS RECEIVER HAVING A LOW POWER
`STANDBY MODE
`
`(75) Inventors: Chung Y. Lau, Sunnyvale; Dominic G.
`Farmer, Milpitas; Kreg A. Martin;
`Eric B. Rodal, both of Cupertino, all of
`Calif.
`
`P.
`-
`s
`73) Assignee: Trimble Navigation, Ltd, Sunnyvale,
`Calif.
`
`21 Appl. No.: 276,886
`(22 Filed:
`Jul. 18, 1994
`(51) Int. Cl. ................................ G01S 5/02; G06F 1700;
`H04B 1/16
`52 U.S. C. .......................... 342/357; 364/707; 455/343;
`455/231
`58 Field of Search ............................. 342/357; 455/343,
`455/230, 231; 364/707
`
`56)
`
`References Cited
`U.S. PATENT DOCUMENTS
`4,449,248 5/1984 Leslie et al. ............................ 455/343
`5,101,510 3/1992 Duckeck ................................. 45.5/186
`5,128,938 7/1992 Borras ..................................... 455/343
`
`5,291,542 3/1994 Kivari et al. .............................. 379,158
`5,418,537 5/1995 Bird .................
`... 342/357
`5,448,773 9/1995 McBurney et al. ..................... 455,343
`Primary Examiner-Gregory C. Issing
`Attorney, Agent, or Firm-David R. Gildea
`57)
`ABSTRACT
`
`A GPS receiver having a normal mode to receive GPS
`satellite signals and to provide location information, and a
`low power standby mode. A microprocessor system in the
`GPS receiver causes the GPS receiver to alternate between
`the normal mode and the low power standby mode in order
`to reduce the average power consumption in the GPS
`receiver. In the normal mode a GPS antenna receives GPS
`satellite signals, the GPS frequency downconverter converts
`the frequency of the GPS satellite signals to an intermediate
`frequency, a digital signal processing system processes the
`intermediate frequency to provide GPS satellite signal cor
`relation information. The microprocessor system processes
`the correlation information and provides location informa
`tion to a user. In the standby mode, the operating power is
`inhibited in the GPS antenna and the GPS frequency down
`converter, the system clock is inhibited in the digital pro
`cessing system, and the microprocessor clock is inhibited in
`the microprocessor system.
`
`31 Claims, 4 Drawing Sheets
`
`30
`
`REFERENCE
`FREQUENCY
`OSCLAOR
`
`p
`
`P2
`
`CLOCK SIGNAL
`
`P
`
`12
`
`V P1
`
`50
`GPS FREQUENCY
`DOWNCONVERTER
`
`DSP SYSTEM
`
`MICROPROCESSOR BUS 41
`
`NTERRUPT BUS
`
`39
`
`P3
`
`OUTPU
`DEVICE
`P5
`
`6
`
`18
`
`INPUT
`4 DEVICE
`P4
`
`20
`
`DR
`DEVICE
`
`70
`P
`
`40
`MICROPROCESSOR
`SYSTEM
`
`F
`
`SO
`
`POWER
`CONTROLER
`
`4.
`POWER
`SUPPLY
`
`
`
`STANDEY
`PMODE
`SELECTION
`EANS
`
`44
`MCROPROCESSOR
`SYSTEM
`
`P1 P2 P3 P4 P5
`
`P
`
`P
`
`N
`O
`
`Petitioner Uber Ex-1031, 0001
`
`

`

`U.S. Patent
`
`Jan. 7, 1997
`
`Sheet 1 of 4
`
`5,592,173
`
`dHOSSEKOO8d080|W
`
`WEIS?S
`
`MEMOd
`
`Kidd[\S
`
`
`
`?jETTO HIN00
`
`MEMOd
`
`09
`
`0#01
`
`a | sw H-a
`
`gd
`
`fyd
`
`1, SmB HOSS3008d080|N-- No.
`
`WB1SÅS dS0
`
`assae}}]}}: AN00NM00
`
`d 9 |BONBAH-JE?!
`
`Z |
`
`
`
`
`
`
`
`
`
`
`
`Petitioner Uber Ex-1031, 0002
`
`

`

`U.S. Patent
`
`–199—1#
`ZdZd
`
`Jan. 7, 1997
`
`Sheet 2 of 4
`
`5,592,173
`
`XOOTO
`
`Sd50
`
`WNNHINW
`
`TVNOIS
`
`Petitioner Uber Ex-1031, 0003
`
`

`

`U.S. Patent
`
`Jan. 7, 1997
`
`Sheet 3 of 4
`
`5,592,173
`
`YOLVTIYNOO
`
`43009
`
`06
`
`sng
`
`—_—
`YOSSIOONAONINao)yoOTS
`
`YOSSIOONdOYNIIN—agge
`
`
`sna
`
`yaluva
`
`YOLYTANYOO
`
`98
`
`ly|
`
`
`YOSSIOONdONDIN399yQ07949079
`
`
`sna“TWNOISTWNOIS
`
`YOSSIOONdONOIN
`
`Sng
`
`
`
`STINNVHDdSG840|
`
`YOSSIOONdONDIN
`
`snd
`
`¢‘Old7
`
`3093085
`
`v8
`
`TINNVHO
`
`49019
`
`YaLSI9O34
`
`
`
`40018WALSAS
`
`WI0T
`
`YaLSIOSY
`
`UTIdAVS
`
`GNOO3STWNOIS
`
`AlSdd
`
`9019
`
`TWNOIS
`
`Petitioner Uber Ex-1031, 0004
`
`Petitioner Uber Ex-1031, 0004
`
`
`
`
`
`
`
`
`
`
`
`

`

`U.S. Patent
`
`Jan. 7, 1997
`
`Sheet 4 of 4
`
`5,592,173
`
`SELECT
`STANDBY MODE
`TME DURATION
`
`STORE WARIABLES
`FOR REACQUESTION
`
`SET RTC
`TIME DURATION
`
`INHIBIT POWER
`
`NHIBIT SYSTEM CLOCK
`
`INHIBIT
`MICROPROCESSOR
`CLOCK BY
`EXECUTENG SLEEP
`INSTRUCTION
`
`STANDBY MODE
`
`
`
`PROCESSOR
`WAKEUP
`
`PASS POWER
`ENABLE SYSTEM CLOCK
`ENABLE MICROPROCESSOR
`COCK
`
`
`
`
`
`
`
`INPUT DEVICE
`
`DEAD RECKONING
`DEVICE
`
`NORMAL MODE
`
`FIG. 4
`
`RETRIEVE WARIABLES
`FOR REACOUISION
`
`ACQUIRE GPS
`SATELITE SIGNALS
`
`COMPUTE LOCATION
`
`
`
`
`
`150
`
`152
`
`154
`
`
`
`
`
`
`
`Petitioner Uber Ex-1031, 0005
`
`

`

`1.
`GPS RECEIVER HAVING ALOW POWER
`STANDBY MODE
`
`5,592,173
`
`2
`Some users extend use time in a GPS receiver by manu
`ally cycling power. A limitation of manually cycling power
`is that users often forget to cycle power off and do not realize
`their error until the batteries are depleted. GPS receivers are
`also used or being considered for use by the United States
`Forest Service to track elk, by marine biologists to track
`elephant seals (when the seals are on the water surface or on
`land), and by the FBI to track crime suspects and parolees.
`A second limitation in these applications is that no user is
`present to manually cycle power.
`A handheld GPS receiver available with a model name
`Pronav 100 uses six disposable alkaline batteries or a
`rechargeable battery pack. It also allows the use of an
`external power source to provide continuous navigation
`microprocessor updates. The Pronav 100 has a "Battery
`Saver Mode' operable on six alkaline batteries for fourteen
`hours with a "QuickFix Mode' which automatically com
`pletes four location fixes per hour. Under most dynamic
`circumstances, use of QuickFix to obtain four position fixes
`per hour is not satisfactory. The usefulness of the Pronav 100
`is limited because the length of battery life is likely to be
`greatly shortened when the limited operations allowable
`under the "Battery Saver Mode' or "QuickFix Mode are not
`sufficient to satisfy the position accuracy requirements.
`Another handheld GPS receiver, the Magellan NAV 1000,
`is powered by six AA alkaline batteries. For the purpose of
`reducing power consumption and extending the life of the
`batteries, a "PowerSaveR' mode is provided under which
`the receiver can be manually turned on to compute a location
`fix. After the location fix is stored as the last fix, the receiver
`turns itself off. The receiver can also operate continuously
`and automatically revert to PowerSaveR mode when a
`"battery low” condition is detected. The NAV 1000 also
`allows the units to operate on an external power source. The
`user's manual includes the instruction not to collect almanac
`information in handheld operation using the battery because
`of the concern for battery life. The NAV 1000 is probably
`less useful due to this limitation. The Trimble Ensign GPS
`receiver uses automatic on/off power cycling to the RF
`circuits to provide a mode where location fixes are available
`at less frequent intervals with less power consumption.
`However, the maximum off time is less than five seconds
`which severely limits the power savings.
`Typical GPS receivers include the GPS antenna, a GPS
`engine, one or more user input devices, one or more user
`output devices, a user microprocessor system to operate the
`input devices and the output devices, and a power supply.
`Some existing low power GPS receivers use a Liquid
`Crystal Display (LCD) for the user output device, and
`electro-mechanical or touchscreen key switches. Electro
`mechanical key switches, where pressing a key completes an
`electrical connection, are often preferred for low power
`applications because no power is used except when a key is
`pressed. An LCD consumes little power in a display but
`consumes substantial power in a backlight if a backlight is
`used. Low power GPS receivers having backlit displays
`generally have a capability to turn off the backlight. The
`GPS engine includes a GPS frequency downconverter, a
`Digital Signal Processing (DSP) system having one or more
`DSP channels, a GPS microprocessor system, and a refer
`ence frequency oscillator. Some handheld GPS receivers
`combine the user microprocessor system and the GPS
`microprocessor system.
`GPS receivers include custom digital and analog circuitry.
`Most digital circuitry in existing GPS receivers use agen
`eration of components intended to be powered at 5 volts.
`New generations of GPS engines use components intended
`
`FIELD OF THE INVENTION
`This invention generally relates to Global Positioning
`System receivers and more specifically relates to techniques
`to reduce power consumption in a Global Positioning Sys
`tem receiver.
`
`10
`
`BACKGROUND OF THE INVENTION
`Global Positioning System is a navigation and position
`service offering worldwide, 24 hour coverage. The Global
`Positioning System (GPS) includes GPS satellites to broad
`cast GPS satellite signals, control stations to monitor and
`control the satellites, and a GPS receiver. The GPS receiver
`demodulates the GPS satellite signals, calculates a pseudo
`range for each GPS satellite that it receives, and computes
`a location and a time of observation. A GPS antenna that is
`apart of the GPS receiver must have a line of sight to a GPS
`satellite to receive a GPS signal from that satellite.
`GPS satellites broadcast two types of location informa
`tion, P code and C/A code. P-code is intended for use by the
`United States military and by agencies specifically autho
`rized by the United States military. P-code is encrypted by
`a Y-code to prevent its unauthorized use. C/A is available to
`everyone without charge. The C/A code is carried on an L1
`carrier at approximately 1.575 GHz. Each GPS satellite
`modulates C/A code information with a PRN sequence that
`is unique to the individual GPS satellite. The GPS receiver
`receives a GPS signal that is a superposition of the GPS
`satellite signals from all the GPS satellites having a line of
`sight. The unique PRN sequence enables the GPS receiver to
`differentiate the GPS signal from each GPS satellite. The
`GPS receiver computes a pseudorange for each GPS satellite
`by comparing the time of arrival of the PRN sequence
`against an internal time standard. The carrier frequency for
`each GPS satellite signal will vary according to Doppler
`shift from motion of the GPS satellite and GPS receiver. A
`description of GPS C/A code is set forth in GPS Interface
`Control Document ICD-GPS-200, published by Rockwell
`International Division, Revision A, 26 Sep. 1984, which is
`incorporated by reference herein.
`Commercial GPS receivers are now used for many appli
`cations involving timing, navigation, tracking, Surveying,
`and geographical information systems. Some of these appli
`cations require that the GPS receiver be carried by an
`individual user. Typically, where the GPS receiver is carded
`by an individual user, the user will not have operating access
`to the power grid or other external power source. Existing
`GPS receivers intended for handheld or carried applications
`use batteries for a power source. A limitation of existing
`GPS receivers intended for carried applications is that the
`power consumption requires frequent changing or charging
`of batteries, or large and heavy batteries. Power consump
`tion in existing handheld GPS receivers such as those
`available from Trimble, Garmin, Sony, Motorola, Panasonic,
`Rockwell, and Magellan is typically one to two watts. These
`GPS receivers operate for two to six hours using three to six
`AA size Alkaline or Nickel Cadmium batteries as recom
`mended by the manufacturers. Existing survey GPS receiv
`ers intended to be luggable, such as a Trimble 4000SST,
`operate for 4 to 8 hours using a battery weighing a few
`pounds.
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`Petitioner Uber Ex-1031, 0006
`
`

`

`3
`to be powered at 3.3 volts. The use of 3.3 volt designs in
`place of 5 volt designs is expected to reduce the power
`consumption in the digital circuitry in the GPS receivers by
`a factor of approximately 2. A second method being used in
`new generations of GPS receivers to reduce power is higher
`levels of integration. In general, less power is consumed in
`a single chip than in two or more chips accomplishing the
`same function because parasitic capacitances, which require
`power to charge and discharge, are lower within an inte
`grated circuit than on a printed circuitboard or other external
`wiring system connecting the chips. Existing low power
`GPS engines use Complementary Metal Oxide Silicon
`(CMOS) for digital circuitry because CMOS allows high
`circuit density and consumes less average power than other
`digital circuit technologies such as Transistor Transistor
`Logic (TTL), Emitter Coupled Logic (ECL), or N type
`Metal Oxide Silicon (NMOS). A CMOS circuit consumes
`power primarily when changing digital states and consumes
`very little power when the circuit is quiescent. Most digital
`systems are synchronous where changes in digital states are
`driven by a clock. Where no clock is present in a synchro
`nous system, the CMOS circuit is quiescent.
`Gallium Arsenide (GaAs) and Silicon technologies are
`used for analog RF circuitry in existing GPS antennas and
`GPS engines. In either GaAs or Silicon, higher levels of
`integration reduces power consumption because parasitic
`capacitances, which require power to charge and discharge,
`are lower within an integrated circuit than on a printed
`circuit board or other external wiring system. New GPS
`receivers are using new RF is designs and fabrication
`processes to achieve higher levels of integration to reduce
`power consumption.
`Static microprocessors such as the Motorola 68300 series
`exist that have a low power quiescent mode when not
`clocked. The microprocessor is placed in the low power
`quiescent or standby mode in response to executing a
`'sleep' instruction in software. At least two types of pro
`cessor sleep instructions are provided to inhibit the clocking
`of the microprocessor-a "stop' instruction for temporarily
`disabling a microprocessor clock source and a "wait'
`instruction for inhibiting a microprocessor clock signal from
`being passed. The clock signal is made available again by
`the receipt of a wakeup interrupt signal. Although static
`microprocessors have been around for a few years, and have
`been s used in a Trimble "Gamma' GPS receiver, no GPS
`receiver is known to use the sleep instruction in order to
`reduce power for a standby mode.
`Many U.S. patents disclose power saving methods for
`signal receivers such as pagers and general communication
`radios. Basically, a receiver is maintained in a standby state
`with low power consumption. Either a hardware or a soft
`ware system is provided to monitor incoming signals. The
`receiving system is activated when an incoming signal
`intended for the receiver is detected. The power is automati
`cally turned off after reception of the signals is complete. In
`some systems, one receiver remains on to reawaken a second
`receiver. Although the general concept of power saving is
`widely known, the known methods are not of practical use
`to a GPS receiver. Unlike the signals received by pagers and
`communication radios, the GPS satellite signals are intended
`to be received and used on a continuous basis. Even when
`not processing GPS satellite signals, GPS receivers are kept
`busy maintaining tables of visibility, almanacs, ephemeris,
`and signal strengths for GPS satellites and implementing
`navigation algorithms. GPS receivers, unlike pagers and
`communication radios, typically require twenty seconds to
`three minutes to re-acquire the GPS signal after power is
`
`4
`turned on. Unlike pagers and communication radios, where
`the receiver initiates a request for a response from a user
`when a signal is received, a GPS user initiates a request for
`a response from the GPS receiver when the user needs
`location. Therefore, the methods of maintaining a standby
`state and passively waiting for the arrival of a signal to save
`battery power, as disclosed in the U.S. patents for general
`signal receiving systems, are not useful for reducing power
`consumption in a GPS receiver.
`Some GPS receivers also include dead reckoning devices
`to enable the GPS receiver to continue to compute and to
`display new locations when lines of sight to GPS satellite
`signals are blocked. Existing GPS receivers do not make use
`of dead reckoning devices to conserve power or to reawaken
`the GPS receiver after a standby time.
`The combination of all existing or known techniques for
`reducing power consumption in GPS receivers is expected to
`reduce power by a factor of approximately 3 or 4 to
`approximately 250 to 750 milliwatts resulting in an increase
`in battery life to approximately 6 to 24 hours. While users of
`handheld GPS receivers will appreciate this increase in
`battery life, a GPS receiver is needed for carried applications
`that will operate with still lower power for still longer
`periods of time without recharging or replacing batteries,
`while providing location fixes at frequent intervals.
`
`SUMMARY OF THE INVENTION
`In a first object, the invention is a GPS receiver having
`two modes, a normal mode where GPS satellite signals are
`acquired and tracked and location is computed, and a
`standby mode where GPS satellite signals are not acquired,
`tracked, or displayed but where power consumption is
`reduced by an order of magnitude or more. The GPS receiver
`includes the following elements: a GPS antenna to receive
`GPS satellite signals; a GPS frequency downconverter to
`convert the GPS satellite signals to an intermediate fre
`quency; a Digital Signal Processing (DSP) system to process
`the intermediate frequency and provide correlation informa
`tion; one or more user input devices to receive user inputs;
`a microprocessor system to receive and to process the
`correlation information, to process the user inputs, to
`receive, process, and issue digital signals to control the
`elements of the GPS receiver, and to provide location
`information to one or more user output devices; a system
`clock source to provide clock signals to the GPS frequency
`downconverter and the DSP system; and a power supply to
`supply power to the elements of the GPS receiver. The
`system clock source is optionally a reference frequency
`oscillator included in the GPS receiver or is an external
`source. The GPS receiver optionally includes dead reckon
`ing devices to provide direction information or change of
`location information.
`In a second object, the GPS receiver includes a power
`controller to control the passing of power from the power
`supply to a recipient device including at least one of the GPS
`antenna, the GPS frequency downconverter, one or more
`user input devices, and one or more user output devices. The
`power controller under the control of the microprocessor
`system passes power to the recipient device during the
`normal mode and inhibits power to the recipient device
`during the low power standby mode.
`In a third object, the DSP system includes at least one
`clock enable register, controlled by the microprocessor
`system, to enable and to inhibit clock signals within the DSP
`system for the normal mode and the standby mode, respec
`
`5,592,173
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`Petitioner Uber Ex-1031, 0007
`
`

`

`5,592,173
`
`10
`
`15
`
`20
`
`25
`
`5
`tively. The DSP system is designed with Complementary
`Metal On Silicon (CMOS) circuits having very low power
`consumption in a quiescent mode compared to power con
`sumption when driven by a clock signal to change between
`digital states.
`In a fourth object, the microprocessor system includes a
`static microprocessor having the capability of inhibiting a
`microprocessor clock signal by executing a sleep instruc
`tion. The microprocessor system is designed with Comple
`mentary Metal On Silicon (CMOS) circuits having very low
`power consumption in a quiescent mode compared to power
`consumption when driven by a clock signal to change
`between digital states. When the sleep instruction is
`executed, the microprocessor system enters low power
`standby mode.
`In a fifth object, a wakeup interrupt signal received by the
`microprocessor system causes the GPS receiver to exit
`standby mode and to enter normal mode. The wakeup
`interrupt signal is provided by a real time clock (RTC), by
`one or more input devices operated by a user, or by an
`optional dead reckoning device.
`In a sixth object, the GPS receiver alternates between the
`normal mode and the low power standby mode, the average
`power consumption over time being reduced to the time
`weighted average of the power consumption in normal mode
`and the power consumption in standby mode.
`In a seventh object, the GPS receiver includes a selection
`means to select a time duration for standby mode. The
`selection means selects a standby mode time duration based
`30
`upon an intended user application, variables that are mea
`sured by the GPS receiver during normal operation, and
`variables requested by the user through the user input
`devices. Time duration of the normal mode includes time
`required to re-acquire the GPS satellite signals, compute a
`new location, and for the microprocessor system to update
`status of the GPS satellite signals. During standby mode, a
`user may provide a wakeup interrupt to override the standby
`mode time duration and to cause the GPS receiver to enter
`the normal mode. The user may also terminate the normal
`mode to cause the GPS receiver to enter standby mode.
`These and other objects and advantages of the present
`invention will no doubt become obvious to those skilled in
`the an after having read the following detailed description of
`the preferred embodiment.
`
`6
`where GPS satellite signals are acquired and tracked and
`where location information is provided and a low power
`standby mode where little or no power is consumed. The
`GPS receiver 10 includes one or more input devices 16 to
`receive requests from a user, one or more output devices 18
`to display information to a user, and optionally one or more
`dead reckoning devices 20 to provide direction information
`or change of location information. The GPS antenna 12
`receives the GPS satellite signals and provides a GPS
`antenna signal having a frequency of approximately 1.575
`GHz and including PRN encoded C/A code modulation. A
`GPS frequency downconverter 50 receives and downcon
`verts the GPS antenna signal a GPS intermediate frequency
`(IF) signal suitable for digital processing. A Digital Signal
`Processing (DSP) system 80 receives the GPSIF signal from
`the GPS frequency downconverter 50 and provides digital
`signals representing correlation information to a micropro
`cessor system 40. A reference oscillator 30 provides a
`system clock signal 31 to the frequency downconverter 50
`and the DSP system 80. Optionally, the system clock is
`provided by an external source. The user input devices 18
`have associated labels to enable a user to know how to
`request an operation of the GPS receiver 10. In one embodi
`ment, the labels are hard or permanent. Alternatively, the
`labels are soft or changed by the user according to a menu
`of operations.
`The microprocessor system 40 includes a microprocessor
`capable of executing a pre-determined set of instructions a
`memory, pre-coded software instructions and data stored in
`the memory, an interrupt receiver, and associated hardware.
`The microprocessor system 40 operates in a conventional
`manner to receive digital signals including information, to
`process the information by executing the pre-coded software
`stored in the memory, and to issue digital signals to control
`the elements of the GPS receiver 10. A microprocessor clock
`source 44, under control of the microprocessor system 40,
`supplies a microprocessor clock signal to the microprocessor
`system 40. The microprocessor system 40 receives digital
`signals representing correlation information from the DSP
`system 80 and issues digital signals representing location,
`rate of change of location, direction, and/or time to the
`output devices 16. A microprocessor bus 41 carries digital
`signals between the microprocessor system 40 and the
`elements of the GPS receiver 10. An interrupt bus 39 carries
`digital signals representing interrupt semaphores from the
`elements of the GPS receiver 10 to the microprocessor
`system 40. The microprocessor is a Motorola CPU32 having
`in its instruction set a "sleep' instruction that inhibits the
`microprocessor clock signal by temporarily disabling the
`clock source or by inhibiting the clock signal. The micro
`processor system 40 retains the capability of receiving and
`processing an interrupt signal when a sleep instruction has
`been executed even though the microprocessor system is not
`being driven by a clock signal. In normal mode, circuits in
`the microprocessor system 40 are driven by the micropro
`cessor clock signal to change digital states. When a sleep
`instruction is executed, the circuits in the microprocessor
`system 40 are quiescent. The microprocessor system 40 uses
`Complementary Metal Oxide Silicon (CMOS) circuits that
`consume substantially less power when quiescent than when
`driven by a clock signal to change digital states. The
`microprocessor system 40 enters low power standby mode
`when it executes a sleep instruction and enters normal mode
`when a wakeup interrupt signal is received.
`A selection means 42, controlled by the microprocessor
`system 40, uses information based on the intended user
`application of the GPS receiver 10, variables measured by
`
`35
`
`40
`
`45
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`FIG. 1 is a block diagram illustrating an embodiment of
`a GPS receiver according to the invention.
`FIG. 2 is a block diagram illustrating an embodiment of
`a GPS frequency downconvertersection of the GPS receiver
`according to the invention.
`FIG. 3 is a block diagram illustrating an embodiment of
`a GPS Digital Signal Processing (DSP) system of the GPS
`receiver according to the invention.
`FIG. 4 is a flow chart illustrating an embodiment of a
`procedure to enter and to exit low power standby mode.
`
`DETAILED DESCRIPTION OF THE
`INVENTION
`FIG. 1 illustrates a block diagram of an embodiment of a
`GPS receiver 10 to receive GPS satellite signals from one or
`more GPS satellites having a line of sight to a GPS antenna
`12 and to determine a location of the GPS antenna 12 and a
`time of observation. The GPS receiver 10 has a normal mode
`
`50
`
`55
`
`60
`
`65
`
`Petitioner Uber Ex-1031, 0008
`
`

`

`7
`the GPS receiver 10, and variables received from the user
`input devices to calculate a time duration for a standby
`mode. The selection means 42 includes and executes pre
`coded software instructions stored in the memory in the
`microprocessor system 40. The standby mode time duration
`is converted to an RTC count number and passed to a real
`time clock (RTC) 70 before a low power standby mode is
`initiated. The RTC 70, including a RTC clock source, counts
`cycles generated by the RTC clock source and then issues a
`wakeup interrupt signal to initiate normal mode when the
`cycle count equals the RTC count number provided by the
`microprocessor system 40.
`A power supply 14 supplies operating power to the
`reference frequency oscillator 30, the microprocessor sys
`tem 40, the selection means 42, the microprocessor clock 44,
`the RTC 70, and a power controller 60. The power controller
`60 is controlled by the microprocessor system 40 to pass or
`to inhibit power to at least one of the following: the GPS
`antenna 12 at P1, the GPS frequency downconverter 50 at
`P2, the one or more output devices 16 at P3, the one or more
`input devices 18 at P5, and the one or more optional dead
`reckoning devices 20 at P4. At least one input device 18,
`such as a key switch, continues to receive power so that a
`user can terminate low power standby mode on request by
`pressing at least one key. In an alternative embodiment, an
`optional dead reckoning device 20 continues to receive
`power to generate an interrupt signal to terminate low power
`standby mode. In normal mode, the power controller 60
`passes power to the above elements of the GPS receiver 10.
`In low power standby mode the power controller 60 inhibits
`power by providing output voltages approximately equal to
`Zero volts or ground voltage, by providing an open circuit so
`that current cannot pass, or by a combination of ground
`voltages and open circuits.
`FIG. 2 illustrates a block diagram of the GPS frequency
`downconverter 50. The GPS frequency downconverter 50
`has a normal mode where the GPS frequency downconverter
`50 provides a GPS IF signal to the DSP system 80 and a low
`power standby mode where the GPS frequency downcon
`verter 50 does not provide the GPS IF signal and where little
`or no power is consumed. The GPS frequency downcon
`verter 50 uses radio frequency (RF) analog integrated circuit
`design techniques and fabrication processes using primarily
`Silicon NPN transistors with 12 GHz F. In alternative
`embodiments, the GPS frequency downconverter 50 may
`use Gallium Arsenide (GaAs) Field Effect Transistor (FET)
`active devices, or uses a combination of Silicon and GaAs
`transistors.
`In the normal mode a preamplifier 52 receives the GPS
`antenna signal at a frequency of approximately 1.575 GHz
`50
`and issues an amplified signal to an RF to IF channel 54. In
`an alternative embodiment, a preamplifier in the GPS
`antenna 12 eliminates the requirement for the preamplifier
`52. Typically, a preamplifier in the GPS antenna 12 and/or
`the preamplifier 52 is required in order to provide good
`signal to noise ratios for the GPS IF signal. A local oscillator
`system 58 receives the system clock signal at one frequency
`from the reference frequency oscillator 30 or external clock
`source and provides one or more local oscillator signals at
`one or more other frequencies to the RF to IF channel 54.
`The RF to IF channel 54 uses the local oscillator signals to
`downconvert the frequency of the amplified GPS antenna
`signal to the GPS IF signal and passes the IF signal to an
`optional first sampler 56. The first sampler 56 synchronizes
`the GPS IF signal to the clock signal, quantizes the ampli
`tude of the GPS IF signal, and issues a digital GPS IF signal
`to the DSP system 80. The power controller 60 shown in
`
`65
`
`35
`
`40
`
`45
`
`55
`
`60
`
`5,592,173
`
`10
`
`15
`
`20
`
`25
`
`30
`
`8
`FIG. 1 enables power for normal mode and inhibits power
`for low power standby mode to the preamplifier 52, the RF
`to IF channel 54, the local oscillator system 58, and the first
`sampler 56.
`FIG. 3 illustrates a block diagram of the Digital Signal
`Processing (DSP) system 80. The DSP system 80 has a
`normal mode where the GPS IF signal is acquired and
`tracked and a low power standby mode where the GPS IF
`signal is not acquired or tracked and where little or no power
`is consumed. The embodiment, the DSP system 80 uses
`digital integrated circuit design techniques and fabrication
`processes using Complementary Metal Oxide Silicon
`(CMOS) active devices having low quiescent power con
`sumption when not driven by clock signals. A second
`sampler 92 synchronizes the GPS IF signal to the system
`clock signal and quantizes the amplitude of the GPS IF
`signal to provide a digital GPS IF signal to one or more DSP
`channels 90. In a preferred embodiment, the DSP system 80
`includes eight (8) identical DSP channels 90 shown in FIG.
`3 as 1 of 8 DSP channels 90.
`The second sampler 92 may be included in each of the
`DSP channels 90, however since the input and the output of
`the second sampler 92 is common for all the DSP channels,
`a cost savings is achieved by using a single second sampler
`92. The microprocessor system 40 assigns each DSP channel
`90 to process the GPS satellite signals, as represented by the
`GPS IF signal, from one or more individual GPS satellites.
`The DSP channel 90 is assigned only one GPS satellite
`signal in parallel operation and is assigned more than one
`GPS satellite signal in serial operation. In serial operation
`the DSP channel 90 time sequences through the assigned
`GPS satellite signals. The DSP channel 90 includes at least
`one carrier correlator 86 and at least one code correlator 88
`to receive the GPS IF signal, to receive the system clock
`signal and to correlate the carrier and code, respectively, in
`the GPS satellite signal as assigned by the microprocessor
`system 40. In a preferred embodiment, each DSP channel 90
`includes four correlators, where each of the correlators is
`configurable by the microprocessor system 40 as a carrier
`correlator 86 or as a code correlator 86.
`The carrier correlator 86 correlates the carrier of the GPS
`satellite signal to a carrier Numerically Controlled Oscillator
`(NCO) included i