Jonathan Dodge, P.E.
`Senior Applications Engineer
`
`IGBT Tutorial
`
`Advanced Power Technology
`405 S.W. Columbia Street
`Bend, OR 97702
`
`Application Note
`APT0201 Rev. B
`July 1, 2002
`
`John Hess
`Vice President, Marketing
`
`3. What is the current that will flow through the
`device? The first two numbers in the part number
`give a rough indication of the usable current. For
`hard switching applications, the usable frequency
`versus current graph is helpful in determining
`whether a device will
`fit
`the application.
`Differences between datasheet test conditions and
`the application should be taken into account, and
`an example of how to do this will be given later.
`For soft switching applications, the IC2 rating could
`be used as a starting point.
`4. What is the desired switching speed? If the
`answer is “the higher, the better”, then a PT device
`is the best choice. Again, the usable frequency
`versus current graph can help answer this question
`for hard switching applications.
`5. Is short circuit withstand capability required? For
`applications such as motor drives, the answer is
`yes, and the switching frequency also tends to be
`relatively low. An NPT device would be required.
`Switch mode power supplies often don’t require
`short circuit capability.
`
`IGBT Overview
`
`Gate
`
`N-channel
`MOSFET
`structure
`
`Emitter
`
`n+
`Body region
`
`Drift region
`
`p n
`
`-
`
`n+
`
`n+
`Buffer layer (PT IGBT)
`p+ Substrate (injecting layer)
`
`Collector
`
`Figure 1 N-Channel IGBT Cross Section
`
`1
`
`Introduction
`With the combination of an easily driven MOS gate
`and low conduction loss, IGBTs quickly displaced
`power bipolar transistors as the device of choice for
`high current and high voltage applications. The
`balance
`in
`tradeoffs between
`switching
`speed,
`conduction loss, and ruggedness is now being ever
`finely tuned so that IGBTs are encroaching upon the
`high frequency, high efficiency domain of power
`MOSFETs. In fact, the industry trend is for IGBTs to
`replace power MOSFETs except in very low current
`applications. To help understand the tradeoffs and to
`help circuit designers with IGBT device selection and
`application, this application note provides a relatively
`painless overview of
`IGBT
`technology and a
`walkthrough of Advanced Power Technology IGBT
`datasheet information.
`
`How to Select an IGBT
`This section is intentionally placed before the technical
`discourse. Answers to the following set of burning
`questions will help determine which
`IGBT
`is
`appropriate
`for a particular application.
` The
`differences between Non Punch-Through (NPT) and
`Punch-Through (PT) devices as well as terms and
`graphs will be explained later.
`
`1. What is the operating voltage? The highest
`voltage the IGBT has to block should be no more
`than 80% of the VCES rating.
`2. Is it hard or soft switched? A PT device is better
`suited for soft switching due to reduced tail
`current, however a NPT device will also work.
`
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`

`An N-channel IGBT is basically an N-channel power
`MOSFET constructed on a p-type substrate, as
`illustrated by the generic IGBT cross section in Figure
`1. (PT IGBTs have an additional n+ layer as well as
`will be explained.) Consequently, operation of an
`IGBT is very similar to a power MOSFET. A positive
`voltage applied from the emitter to gate terminals
`causes electrons to be drawn toward the gate terminal
`in the body region. If the gate-emitter voltage is at or
`above what is called the threshold voltage, enough
`electrons are drawn toward the gate to form a
`conductive channel across the body region, allowing
`current to flow from the collector to the emitter. (To
`be precise, it allows electrons to flow from the emitter
`to the collector.) This flow of electrons draws positive
`ions, or holes, from the p-type substrate into the drift
`region toward the emitter. This leads to a couple of
`simplified equivalent circuits for an IGBT as shown in
`Figure 2.
`
`
`Collector
`
`Collector
`
`Gate
`
`Gate
`
`Emitter
`
`Emitter
`
`
`
`Figure 2 IGBT Simplified Equivalent Circuits
`
`The first circuit shows an N-channel power MOSFET
`driving a wide base PNP bipolar transistor in a
`Darlington configuration. The second circuit simply
`shows a diode in series with the drain of an N-channel
`power MOSFET. At first glance, it would seem that
`the on state voltage across the IGBT would be one
`diode drop higher than for the N-channel power
`MOSFET by itself. It is true in fact that the on state
`voltage across an IGBT is always at least one diode
`drop. However, compared to a power MOSFET of the
`same die size and operating at the same temperature
`and current, an IGBT can have significantly lower on
`state voltage. The reason for this is that a MOSFET is
`a majority carrier device only. In other words, in an N-
`channel MOSFET only electrons flow. As mentioned
`before, the p-type substrate in an N-channel IGBT
`injects holes into the drift region. Therefore, current
`flow in an IGBT is composed of both electrons and
`holes. This injection of holes (minority carriers)
`significantly reduces the effective resistance to current
`flow in the drift region. Stated otherwise, hole
`injection significantly increases the conductivity, or the
`conductivity is modulated. The resulting reduction in
`
`on state voltage is the main advantage of IGBTs over
`power MOSFETs.
`
`Nothing comes for free of course, and the price for
`lower on state voltage is slower switching speed,
`especially at turn-off. The reason for this is that during
`turn-off the electron flow can be stopped rather
`abruptly, just as in a power MOSFET, by reducing the
`gate-emitter voltage below
`the
`threshold voltage.
`However, holes are left in the drift region, and there is
`no way to remove them except by voltage gradient and
`recombination. The IGBT exhibits a tail current during
`turn-off until all the holes are swept out or recombined.
`The rate of recombination can be controlled, which is
`the purpose of the n+ buffer layer shown in Figure 1.
`This buffer layer quickly absorbs trapped holes during
`turn-off. Not all IGBTs incorporate an n+ buffer layer;
`those that do are called punch-through (PT), those that
`do not are called non punch-through (NPT). PT IGBTs
`are sometimes referred to as asymmetrical, and NPT as
`symmetrical.
`
`The other price for lower on state voltage is the
`possibility of latchup if the IGBT is operated well
`outside the datasheet ratings. Latchup is a failure mode
`where the IGBT can no longer be turned off by the
`gate. Latchup can be induced in any IGBT through
`misuse. Thus the latchup failure mechanism in IGBTs
`warrants some explanation.
`
`The basic structure of an IGBT resembles a thyristor,
`namely a series of PNPN junctions. This can be
`explained by analyzing a more detailed equivalent
`circuit model for an IGBT shown in Figure 3.
`
`
`Collector
`
`Drift region
`resistance
`
`Gate
`
`Parasitic
`NPN
`
`Parasitic
`thyristor
`
`Body region
`spreading
`resistance
`
`Emitter
`
`
`
`Figure 3 IGBT Model Showing Parasitic Thyristor
`
`A parasitic NPN bipolar transistor exists within all N-
`channel power MOSFETS and consequently all N-
`
`2
`
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`

`channel IGBTs. The base of this transistor is the body
`region, which is shorted to the emitter to prevent it
`from turning on. Note however that the body region
`has some resistance, called body region spreading
`resistance, as shown in Figure 3. The P-type substrate
`and drift and body regions form the PNP portion of the
`IGBT. The PNPN structure forms a parasitic thyristor.
`If the parasitic NPN transistor ever turns on and the
`sum of the gains of the NPN and PNP transistors are
`greater than one, latchup occurs. Latchup is avoided
`through design of the IGBT by optimizing the doping
`levels and geometries of the various regions shown in
`Figure 1.
`
`The gains of the PNP and NPN transistors are set so
`that their sum is less than one. As temperature
`increases, the PNP and NPN gains increase, as well as
`the body region spreading resistance. Very high
`collector current can cause sufficient voltage drop
`across the body region to turn on the parasitic NPN
`transistor, and excessive localized heating of the die
`increases the parasitic transistor gains so their sum
`exceeds one. If this happens, the parasitic thyristor
`latches on, and the IGBT cannot be turned off by the
`gate and may be destroyed due to over-current heating.
`This is static latchup. High dv/dt during turn-off
`combined with excessive collector current can also
`effectively increase gains and turn on the parasitic
`NPN transistor. This is dynamic latchup, which is
`actually what limits the safe operating area since it can
`happen at a much lower collector current than static
`latchup, and it depends on the turn-off dv/dt. By
`staying within the maximum current and safe operating
`area ratings, static and dynamic latchup are avoided
`regardless of turn-off dv/dt. Note that turn-on and
`turn-off dv/dt, overshoot, and ringing can be set by an
`external gate resistor (as well as by stray inductance in
`the circuit layout).
`
`PT versus NPT Technology
`Conduction Loss
`For a given switching speed, NPT technology generally
` This
`has a higher VCE(on) than PT technology.
`difference is magnified further by fact that VCE(on)
`increases with
`temperature
`for NPT
`(positive
`temperature coefficient), whereas VCE(on) decreases
`with
`temperature
`for PT
`(negative
`temperature
`coefficient). However, for any IGBT, whether PT or
`NPT, switching loss is traded off against VCE(on).
`Higher speed IGBTs have a higher VCE(on); lower speed
`IGBTs have a lower VCE(on). In fact, it is possible that a
`very fast PT device can have a higher VCE(on) than a
`NPT device of slower switching speed.
`
`
`Switching Loss
`For a given VCE(on), PT IGBTs have a higher speed
`switching capability with lower total switching energy.
`This is due to higher gain and minority carrier lifetime
`reduction, which quenches the tail current.
`
`Ruggedness
`NPT IGBTs are typically short circuit rated while PT
`devices often are not, and NPT IGBTs can absorb more
`avalanche energy than PT IGBTs. NPT technology is
`more rugged due to the wider base and lower gain of
`the PNP bipolar transistor. This is the main advantage
`gained by trading off switching speed with NPT
`technology. It is difficult to make a PT IGBT with
`greater than 600 Volt VCES whereas it is easily done
`with NPT technology. Advanced Power Technology
`does offer a series of very fast 1200 Volt PT IGBTs,
`the Power MOS 7 IGBT series.
`
`Temperature Effects
`For both PT and NPT IGBTs, turn-on switching speed
`and loss are practically unaffected by temperature.
`Reverse recovery current in a diode however increases
`with temperature, so temperature effects of an external
`diode in the power circuit affect IGBT turn-on loss.
`
`For NPT IGBTs, turn-off speed and switching loss
`remain
`relatively
`constant over
`the operating
`temperature range. For PT IGBTs, turn-off speed
`degrades and switching loss consequently increases
`with temperature. However, switching loss is low to
`begin with due to tail current quenching.
`
`As mentioned previously, NPT IGBTs typically have a
`positive temperature coefficient, which makes them
`well suited for paralleling. A positive temperature
`coefficient is desirable for paralleling devices because
`a hot device will conduct less current than a cooler
`device, so all the parallel devices tend to naturally
`share current. It is a misconception however that PT
`IGBTs cannot be paralleled because of their negative
`temperature coefficient. PT IGBTs can be paralleled
`because of the following:
`• Their temperature coefficients tend to be almost
`zero and are sometimes positive at higher current.
`• Heat sharing through the heat sink tends to force
`devices to share current because a hot device will
`heat its neighbors, thus lowering their on voltage.
`• Parameters that affect the temperature coefficient
`tend to be well matched between devices.
`
`
`IGBTs from Advanced Power Technology
`Advanced Power Technology offers three series of
`IGBTs to cover a broad range of applications:
`
`3
`
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`

`• Power MOS 7® Series – 600V and 1200V PT
`technology IGBTs designated by ‘GP’ in the part
`number, one of the fastest IGBTs on the market,
`designed for operation at high frequencies and/or
`for tail current sensitive applications such as soft
`switching.
`• Thunderbolt® Series – 600V only NPT technology
`IGBTs designated by ‘GT’ in the part number, fast
`IGBTs capable of 150kHz in hard switching
`applications, short circuit rated rugged devices
`suitable for switch-mode power supplies as well as
`motor drives.
`• Fast Series – 600V and 1200V NPT technology
`IGBTs designated by ‘GF’ in the part number,
`short circuit rated rugged devices with low on
`voltage suitable for hard switching operation
`below 100kHz such as in motor drives.
`
`
`Power MOS 7® IGBTs from APT are unique in that
`they are designed to switch extremely fast, and they
`incorporate a proprietary metal gate and open cell
`structure.
` The result
`is extremely
`low
`internal
`equivalent gate resistance (EGR), typically a fraction
`of an Ohm; one to two orders of magnitude lower than
`for poly-silicon gate devices. Low EGR enables faster
`switching and consequently lower switching loss. The
`
`Heading
`
`APT
`
`50
`
`GF
`
`60
`
`B2
`
`R
`
`D
`
`metal gate and open cell structure also result in
`extremely uniform and fast excitation of the gate,
`minimizing hot spots during switching transients and
`improving reliability. An open cell structure is also
`more
`tolerant of defects
`induced during
`the
`manufacturing process.
`
`Datasheet Walkthrough
`The intent of datasheets provided by APT is to include
`relevant information that is useful and convenient for
`the power circuit designer, both for selection of the
`appropriate device
`as well
`as predicting
`its
`performance in an application. Graphs are provided to
`enable the designer to extrapolate from one set of
`operating conditions to another. It should be noted
`though that test results are very strongly circuit
`dependent, especially on stray emitter inductance but
`also on stray collector inductance and gate drive circuit
`design and layout. Different test circuits yield different
`results.
`
`The following walkthrough provides definition of
`terms in APT datasheets as well as further details on
`IGBT characteristics.
`
`Combi
`D, D1, D2, D3, D4: anti-parallel FRED
`U2 FRED connected in "boost" configuration
`U3 FRED connected in "buck" configuration
`Not a Combi if blank (IGBT only).
`
`R Avalanche energy rated: EAS is specified for
`unclamped inductive switching (UIS).
`Not avalanche energy rated if blank.
`
`Package
`K TO-220
`B TO-247
`B2 T-MAXTM
`L
`TO-264
`J
`ISOTOP®
`
`VCES rating divided by 10
`
`IGBT Series
`GP Power MOS 7® IGBTs, PT technology
`GT Thunderbolt® IGBTs, NPT technology
`GF Fast IGBTs, NPT technology
`
`Device current indicator -- not necessarily tied to
`any datasheet parameter but gives a rough
`indication of usable current capability.
`
`Advanced Power Technology
`
`
`
`4
`
`ISOTOP® is a registered trademark of STMicroelectronics
`
`Figure 4 APT Part Numbering for IGBTs
`
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`

`Maximum Ratings
`VCES – Collector-Emitter Voltage
`This is a rating of the maximum voltage between the
`collector and emitter terminals with the gate shorted to
`the emitter. This is a maximum rating, and depending
`on temperature, the maximum permissible collector-
`emitter voltage could actually be less than the VCES
`rating. See the description of BVCES in Static Electrical
`Characteristics.
`
`VGE – Gate-Emitter Voltage
`VGE is a rating of the maximum continuous voltage
`between the gate and emitter terminals. The purposes
`of this rating are to prevent breakdown of the gate
`oxide and to limit short circuit current. The actual gate
`oxide breakdown voltage is significantly higher than
`this, but staying within this rating at all times ensures
`application reliability.
`
`VGEM – Gate Emitter Voltage Transient
`VGEM is the maximum pulsed voltage between the gate
`and emitter terminals. The purpose of this rating is to
`prevent breakdown of the gate oxide.
`
`Transients on the gate can be induced not only by the
`applied gate drive signal but often more significantly
`by stray inductance in the gate drive circuit as well as
`feedback through the gate-collector capacitance. If
`there is more ringing on the gate than VGEM, stray
`circuit inductances probably need to be reduced, and/or
`the gate resistance should be increased to slow down
`the switching speed. In addition to the power circuit
`layout, gate drive circuit
`layout
`is critical
`in
`minimizing the effective gate drive loop area and
`resulting stray inductances. See Figure 9.
`
`If a clamping zener is used, it is recommended to
`connect it between the gate driver and the gate resistor
`rather than directly to the gate terminal. Negative gate
`drive is not necessary but may be used to achieve the
`utmost
`in switching speed while avoiding dv/dt
`induced turn-on. See application note APT9302 for
`more information on gate drive design.
`
`IC1, IC2 – Continuous Collector Current
`IC1 and IC2 are ratings of the maximum continuous DC
`current with the die at its maximum rated junction
`temperature. They are based on the junction to case
`thermal resistance rating RθJC and the case temperature
`as follows:
`
`
`=
`
`P
`D
`
`−
`
`T
`C
`
`=
`
`V
`CE(on)
`
`⋅
`
`I
`
`C
`
` (1)
`
`can be dissipated,
`
`, equals the maximum
`
`T
`J(max)
`R θ
`JC
`This equation simply says that the maximum heat that
`−
`T
`T
`J(max)
`C
`R θ
`JC
`loss,
`conduction
`allowable heat generated by
`I⋅
`V
`. There are no switching losses involved in
`CE(on)
`C
`IC1 and IC2. Solving for IC:
`
`
`=
`
`I
`
`C
`
`−
`
`T
`C
`
`T
`J (max)
`⋅
`R
`Vθ
`JC
`CE(on)
`
` (2)
`
`
`Of course VCE(on) depends upon IC (as well as junction
`temperature). Except at relatively low current, the
`relationship between IC and VCE(on) is fairly linear, as
`shown in Figure 5. Thus a linear approximation can be
`used to relate IC to VCE(on).
`
`Ι
`
`C
`
`TJ = TJ(max)
`
`RCE(on) = ∆VCE ÷ ∆IC
`
`∆Ι
`
`C
`
`VCE(on,max)
`
`∆VCE
`
`VCE(zero)
`
`VCE
`
`
`Figure 5 Linear Approximation of IC versus VCE(on)
`The curve of VCE(on) is with the die at elevated
`temperature. (To calculate datasheet values, APT uses
`the maximum VCE(on), which is higher than the typical
`VCE(on) to account for normal variations between parts.)
`The equation relating VCE(on) to IC is:
`
`V
`CE(on)
`
`This equation is substituted into (2) for VCE(on) to solve
`for IC:
`
`
`=
`
`⋅
`I R
`C
`
`CE(on)
`
`+
`
`V
`CE(zero)
`
` (3)
`
`5
`
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`

`=
`
`I
`
`C
`
`−
`
`T
`C
`
`T
`J(max)
`R
`V
`CE(on)
`
`⋅
`
`θ
`JC
`
`=
`
`(
`
`R
`
`θ
`JC
`
`−
`
`T
`J(max)
`⋅
`I R
`C
`
`CE(on)
`
`T
`C
`+
`V
`CE(zero)
`
`)
`
`⇒
`
`⋅
`
`R
`
`2
`
`I
`
`C
`
`CE(on )
`
`+
`
`⋅
`I V
`C
`CE(zero)
`
`=
`
`T
`C
`
`−
`
`T
`J(max)
`Rθ
`JC
`
` (4)
`
`
`This is in the form of the familiar quadratic equation
`− ±
`− ⋅
`⋅
`2
`b
`b
`4 a c
`⋅
`2 a
`
`(
`
`T
`C
`
`−
`
`T
`J(max)
`R θ
`JC
`
`)
`
`. The
`
`=
`
`x
`
` with
`
`a = RCE(on), b = VCE(zero), and
`
`c
`
`−
`
`=
`
`solution is:
`
`
`−
`
`V
`CE(zero)
`
`+
`
`V
`CE(zero)
`
`2
`
`+ ⋅
`4 R
`
`CE(on )
`
`
`⋅
`
`
`⋅
`2 R
`
`CE(on )
`
`=
`
`I
`
`C
`
`−
`
`T
`C
`
`T
`J(max)
`R
`
`θ
`JC
`
`
`
`
`
` (5)
`
`
`IC in (5) represents the continuous DC current (with the
`device fully on) that causes the die to heat up to its
`maximum rated junction temperature. IC1 is the
`solution to (5) with TC equal to 25 ºC. IC2 is the
`solution to (5) with TC at an elevated temperature. This
`is a more useful rating than the traditional IC1 rating
`since operating at a case temperature of only 25 ºC is
`seldom feasible, however IC2 still does not take
`switching losses into account.
`
`Graph of IC versus TC
`To assist designers in the selection of devices for a
`particular application, APT provides a graph of
`maximum collector current versus case temperature.
`This graph is simply the solution to (5) over a range of
`case temperatures. Figure 6 shows an example. Note
`that in this case, the package leads limit the current to
`100 Amps at low temperature, not the die.
`
`
`
`Figure 6 Maximum Collector Current versus Case
`Temperature
`
`Using the IC1 and IC2 Ratings
`The IC1 and IC2 ratings and the graph of maximum
`collector current versus case
`temperature simply
`indicate the maximum theoretical continuous DC
`current that the device can carry, based on the
`maximum junction to case thermal resistance. Their
`purpose is mainly as figures of merit for comparing
`devices. For a soft switching application, IC2 is a good
`starting point for selecting a device. In a hard or soft
`switching application, the device might safely carry
`more or less current depending upon:
`• switching losses
`• duty cycle
`• switching frequency
`• switching speed
`• heat sinking capacity
`• thermal impedances and transients
`
`
`The point is that you cannot simply assume that the
`device can safely carry the same current in a switch-
`mode power converter as is indicated in the IC1 or IC2
`ratings or in the graph of maximum collector current
`versus case temperature. APT offers application
`support if you require assistance with selecting devices
`or modules that are appropriate for your application.
`
`ICM – Pulsed Collector Current
`This rating indicates how much pulsed current the
`device can handle, which is significantly higher than
`the rated continuous DC current. The purposes of the
`ICM rating are:
`• To keep the IGBT operating in the “linear” region
`of its transfer characteristic. See Figure 7. There
`is
`a maximum
`collector
`current
`for
`a
`corresponding gate-emitter voltage that an IGBT
`will conduct. If the operating point at a given
`gate-emitter voltage goes above the linear region
`“knee” in Figure 7, any further increase in
`collector current results in a significant rise in
`collector-emitter voltage and consequent rise in
`conduction loss and possible device destruction.
`The ICM rating is set below the “knee” for typical
`gate drive voltages.
`• To prevent burnout or latchup. Even if the pulse
`width is theoretically too short to overheat the die,
`significantly exceeding the ICM rating can cause
`enough localized die feature heating to result in a
`burnout site or latchup.
`• To prevent overheating the die. The footnote
`“Repetitive
`rating: Pulse width
`limited by
`maximum junction temperature” implies that ICM is
`based on a thermal limitation depending on pulse
`width. This is always true for two reasons: 1)
`there is some margin in the ICM rating before risk
`
`6
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`

`The circuit designer does not need to worry about
`snubbers, minimum gate resistance, or limits on dv/dt
`as long as these ratings are not exceeded.
`
`EAS – Single Pulse Avalanche Energy
`All devices that are avalanche energy rated have an EAS
`rating. Avalanche energy rated is synonymous with
`unclamped inductive switching (UIS) rated. EAS is
`both thermally limited and defect limited and indicates
`how much reverse avalanche energy the device can
`safely absorb with the case at 25 ºC and the die at or
`below the maximum rated junction temperature. The
`open cell structure used in Power MOS 7 mitigates
`the defect limitation on EAS. On the other hand, a
`defect in a closed cell structure can cause the cell to
`latchup under avalanche condition. Do not operate an
`IGBT intentionally in avalanche condition without
`thorough testing.
`
`Conditions for a test circuit are stated in a footnote, and
`L i
`
` where L is the value of
`
`2 C
`
`2⋅
`
`the EAS rating is equal to
`
`an inductor carrying a peak current iC, which is
`suddenly diverted into the collector of the device under
`test. It is the inductor’s voltage, which exceeds the
`breakdown voltage of the IGBT, that causes the
`avalanche condition. An avalanche condition allows
`the inductor current to flow through the IGBT, even
`though the IGBT is in the off state. Energy stored in
`the inductor is analogous to energy stored in leakage
`and/or stray inductances and is dissipated in the device
`under test. In an application, if ringing due to leakage
`and stray inductances does not exceed the breakdown
`voltage, then the device will not avalanche and hence
`does not need
`to dissipate avalanche energy.
`Avalanche energy rated devices offer a safety net
`depending on the margin between the voltage rating of
`the device and system voltages, including transients.
`
`PD – Total Power Dissipation
`This is a rating of the maximum power that the device
`can dissipate and is based on the maximum junction
`temperature and the thermal resistance RθJC at a case
`temperature of 25 ºC.
`
`
`−
`
`=
`
`P
`D
`
`T
`J(max)
`R θ
`JC
`At case temperatures above 25 ºC, the linear derating
`factor is simply the inverse of RθJC.
`
`
`T
`C
`
` (6)
`
`7
`
`of damage other than by the die exceeding its
`maximum junction temperature, and 2) no matter
`what the failure mechanism really is, overheating
`is almost always the observed end result anyway.
`• To avoid problems with excessive current through
`the bond wires, although there would probably
`first be problems related to excessive current
`through the die.
`
`
`
`iC
`
`Linear
`region
`
`BV CES
`
`0
`
`0
`
`Increasing VGE
`
`Active
`region
`
`VGE4
`
`VGE3
`
`VGE2
`
`V GE1
`
`BV CES
`
`v CE
`
`
`
`Figure 7 IGBT Transfer Characteristic
`
`Regarding the thermal limitation on ICM, temperature
`rise depends upon the pulse width, time between
`pulses, heat dissipation, and VCE(on) as well as the shape
`and magnitude of the current pulse. Simply staying
`within the ICM limit does not ensure that the maximum
`junction temperature will not be exceeded. See the
`discussion of
`the Maximum Effective Transient
`Thermal Impedance curve for a procedure to estimate
`junction temperature during a current pulse.
`
`ILM, RBSOA, and SSOA – Safe Operating
`Areas
`These ratings are all related. ILM is the amount of
`clamped inductive load current the device can safely
`switch in a snubberless hard switching application.
`Test circuit conditions are specified (case temperature,
`gate resistance, clamp voltage, etc.) The ILM rating is
`limited by the turn-off transient, where the gate was
`positive-biased and switches to zero or negative bias.
`Hence the ILM rating and the Reverse Bias Safe
`Operating Area (RBSOA) are similar. The ILM rating is
`a maximum current, RBSOA is a maximum current at
`a specified voltage.
`
`Switching safe operating area (SSOA) is simply
`RBSOA at the full VCES voltage rating. Forward bias
`safe operating area (FBSOA), which covers the turn-on
`transient, is typically much higher than the RBSOA
`and is therefore typically not listed in the datasheet.
`
`IPR2022-00716
`Apple EX1012 Page 7
`
`

`

`TJ,TSTG – Operating and Storage Junction
`Temperature Range
`This is the range of permissible storage and operating
`junction temperatures. The limits of this range are set
`to ensure a minimum acceptable device service life.
`Operating away from the limits of this range can
`significantly enhance the service life. It’s actually an
`exponential function relating device life to junction
`temperature, but as a “rule of thumb”, for thermally
`induced effects only, every 10 ºC reduction in junction
`temperature doubles the device life.
`
`Static Electrical Characteristics
`BVCES – Collector-Emitter Breakdown
`Voltage
`the actual collector-emitter breakdown
`Measuring
`voltage is practically impossible without destroying the
`device. Therefore, BVCES is the collector-emitter
`voltage at which no more than the specified collector
`current will flow at the specified temperature. This
`tracks the actual breakdown voltage.
`
`
`
`
`Figure 8 Normalized Breakdown Voltage vs.
`Junction Temperature
`
`in Figure 8, BVCES has a positive
`As shown
`temperature coefficient. At a fixed leakage current, an
`IGBT can block more voltage when hot than when
`cold. In fact, when cold, the BVCES specification is less
`than the VCES rating. For the example shown in Figure
`8, at -50 ºC, BVCES is about 93% of the nominal 25 ºC
`specification.
`
`
`RBVCES – Reverse Collector-Emitter
`Breakdown Voltage
`This is the reverse collector-emitter breakdown voltage
`specification, i.e., when the emitter voltage is positive
`with respect to the collector. As with BVCES, RBVCES
`is the emitter-collector voltage at which no more than
`the specified emitter current will flow at the specified
`temperature. A typical value is about 15 Volts,
`however RBVCES is often not specified since an IGBT
`is not designed for reverse voltage blocking. Even
`though in theory an NPT IGBT can block as much
`reverse voltage as forward voltage, in general it cannot
`due to the manufacturing process. A PT IGBT cannot
`block very much reverse voltage due to the n+ buffer
`layer.
`
`VGE(th) – Gate Threshold Voltage
`This is the gate-source voltage at which collector
`current begins to flow. Test conditions (collector
`current,
`collector-emitter
`voltage,
`junction
`temperature) are also specified. All MOS gated
`devices exhibit variation in VGE(th) between devices,
`which is normal. Therefore, a range of VGE(th) is
`specified, with
`the minimum
`and maximum
`representing the edges of the VGE(th) distribution.
`VGE(th) has a negative temperature coefficient, meaning
`that as the die heats up, the IGBT will turn on at a
`lower gate-emitter voltage.
` This
`temperature
`coefficient is typically about minus 12mV/ºC, the same
`as for a power MOSFET.
`
`VCE(on) – Collector-Emitter On Voltage
`This is the collector-emitter voltage across the IGBT at
`a specified collector current, gate-emitter voltage, and
`junction temperature. Since VCE(on) is temperature
`dependent, it is specified both at room temperature and
`hot.
`
`that show the relationships
`Graphs are provided
`between
`typical
`(not maximum) collector-emitter
`voltage and collector current, temperature, and gate-
`emitter voltage. From these graphs, a circuit designer
`can estimate conduction loss and the temperature
`coefficient of VCE(on). Conduction power loss is VCE(on)
`times collector current. The temperature coefficient is
`the slope of VCE(on) versus temperature. NPT IGBTs
`have a positive temperature coefficient, meaning that
`as the junction temperature increases, VCE(on) increases.
`PT IGBTs on the other hand tend to have a slightly
`negative temperature coefficient. For both types, the
`temperature coefficient
`tends
`to
`increase with
`increasing collector current. As current increases, the
`temperature coefficient of a PT IGBT can actually
`transition from negative to positive.
`
`8
`
`IPR2022-00716
`Apple EX1012 Page 8
`
`

`

`ICES – Collector Cutoff Current
`This is the leakage current that flows from collector to
`emitter when the device is off, at a specified collector-
`emitter and gate-emitter voltage. Since leakage current
`increases with temperature, ICES is specified both at
`room temperature and hot. Leakage power loss is ICES
`times collector-emitter voltage.
`
`IGES – Gate-Emitter Leakage Current
`This is the leakage current that flows through the gate
`terminal at a specified gate-emitter voltage.
`
`Dynamic Characteristics
`Figure 9 shows an equivalent IBGT model that
`includes the capacitances between the terminals. Input,
`output,
`and
`reverse
`transfer
`capacitances
`are
`combinations of these capacitances. See application
`note APT0103 for more details. Test conditions to
`measure capacitances are specified in the datasheet.
`
`
`C
`
`CGC
`
`RG
`
`G
`
`CCE
`
`Gate
`supply
`voltage
`
`Gate drive
`circuit
`
`Coes – Output Capacitance
`This is the output capacitance measured between the
`collector and emitter terminals with the gate shorted to
`the emitter for AC voltages. Coes is made up of the
`collector to emitter capacitance (CCE) in parallel with
`the gate to collector capacitance (CGC), or
`
`+
`=
`C
`C
`C
`
`
`oes
`CE
`GC
`For soft switching applications, Coes is important
`because it can affect the resonance of the circuit.
`
`Cres – Reverse Transfer Capacitance
`This is the reverse transfer capacitance measured
`between the collector and gate terminals with the
`emitter connected to ground. The reverse transfer
`capacitance
`is equal
`to
`the gate
`to collector
`capacitance.
`
`
`
`The reverse transfer capacitance, often referred to as
`the Miller capacitance, is one of the major parameters
`affecting voltage rise and fall times during switching.
`
`
`C=
`
`
`
`GC
`
`C
`
`res
`
`CGE
`
`E
`
`
`
`inimize this area
`
`+
`
`Optional
`negative gate
`supply voltage
`
`-M
`
`Figure 9 IGBT Capacitances
`Cies – Input Capacitance
`This is the input capacitance measured between the
`gate and emitter terminals with the collector s