UNITED STATES PATENT AND TRADEMARK OFFICE
`
`_________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`_________________
`
`APPLE INC.,
`Petitioner
`
`v.
`
`TELEFONAKTIEBOLAGET LM ERICSSON,
`Patent Owner
`
`_________________
`
`Inter Partes Review Case No. IPR2022-00716
`U.S. Patent No. 9,705,400
`
`DECLARATION OF DR. MARWAN HASSOUN, PH.D. IN SUPPORT OF
`PETITION FOR INTER PARTES REVIEW OF
`U.S. PATENT NO. 9,705,400
`
`IPR2022-00716
`Apple EX1006 Page 1
`
`
`
`_________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`_________________
`
`APPLE INC.,
`Petitioner
`
`v.
`
`TELEFONAKTIEBOLAGET LM ERICSSON,
`Patent Owner
`
`_________________
`
`Inter Partes Review Case No. IPR2022-00716
`U.S. Patent No. 9,705,400
`
`DECLARATION OF DR. MARWAN HASSOUN, PH.D. IN SUPPORT OF
`PETITION FOR INTER PARTES REVIEW OF
`U.S. PATENT NO. 9,705,400
`
`IPR2022-00716
`Apple EX1006 Page 1
`
`
`
`TABLE OF CONTENTS
`
`I. ASSIGNMENT ............................................................................................. 1
`
`II. BACKGROUND AND QUALIFICATIONS ............................................. 2
`
`III. MATERIALS AND OTHER INFORMATION CONSIDERED .............. 4
`
`IV. UNDERSTANDING OF PATENT LAW ................................................... 5
`
`V. OVERVIEW OF TECHNOLOGY AND OF THE ’400 PATENT ........... 8
`
`A. TECHNOLOGY BACKGROUND ....................................................................... 8
`
`1. H-Bridge Circuits ................................................................................... 8
`
`2. Class D Power Amplifiers ...................................................................... 9
`
`3. Bridge Rectifiers....................................................................................11
`
`B. OVERVIEW OF THE ’400 PATENT .................................................................11
`
`1. Claims ...................................................................................................12
`
`2. Summary of the Alleged Invention .........................................................12
`
`3. Summary of the Prosecution History .....................................................18
`
`VI. LEVEL OF ORDINARY SKILL IN THE ART .......................................20
`
`VII. DETAILED INVALIDITY ANALYSIS ....................................................21
`
`A. BACKGROUND ON PRIOR ART REFERENCES ................................................21
`
`1. Overview of Smith (Ex. 1004) ................................................................21
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`2. Overview of Stengel (Ex. 1005) .............................................................27
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`B. GROUND I: SMITH IN VIEW OF THE KNOWLEDGE OF A POSITA ....................33
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`1.
`
`Independent Claim 1 .............................................................................33
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`2. Claim 2 ..................................................................................................43
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`3. Claim 8 ..................................................................................................45
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`4. Claim 10 ................................................................................................46
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`C. GROUND II: SMITH IN VIEW OF STENGEL ......................................................48
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`1. Claim 14 ................................................................................................48
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`VIII. CONCLUSION........................................................................................53
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`LIST OF EXHIBITS FOR THE PETITION
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`Exhibit 1001 U.S. Patent No. 9,705,400
`Exhibit 1002 File History of U.S. Patent No. 9,705,400
`Exhibit 1003 File History of European Patent No. EP2811646
`Exhibit 1004
`International Publication WO 2010/111433 A2 (“Smith”)
`Exhibit 1005 United States Patent No. 5,506,493 (Stengel)
`Exhibit 1007 Curriculum Vitae of Dr. Marwan Hassoun, Ph.D.
`Exhibit 1008 Hart, Daniel W., “Power Electronics,” McGraw-Hill, 2011
`Exhibit 1009 Maxim Integrated, “Fundamentals of Class D Amplifiers,”
`Application Note 3977, Jan. 31, 2007.
`Exhibit 1010 Honda, Jun et al. “Class D Audio Amplifier Basics,” Application
`Note AN-1071, Internal Rectifier, Feb. 8, 2005
`Exhibit 1011 Sattar, Abdus, “Insulated Gate Bipolar Transistor (IGBT)
`Basics,” IXYS Corp., 2008
`Exhibit 1012 Dodge, Jonathan, “IGBT Tutorial,” Application Note APT0201
`Rev. B, Advanced Power Technology, July 1, 2002
`In the Matter of Certain Mobile Phones and Tablet Computers,
`All With Switchable Connectivity, ITC-337-TA-1300, Exhibit
`15A to Complaint, Complainant’s Proof of Infringement (ITC
`Jan. 18, 2022)
`In the Matter of Certain Mobile Phones and Tablet Computers,
`All with Switchable Connectivity, ITC-337-TA-1300, Proposed
`Scheduling Order (ITC Mar. 11, 2022)
`
`Exhibit 1013
`
`Exhibit 1014
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`
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`I, Dr. Marwan Hassoun, hereby declare as follows:
`
`I.
`
`ASSIGNMENT
`1.
`
`I have been retained as an expert witness on behalf of Apple Inc.
`
`(“Apple” or “Petitioner”) to offer technical opinions in connection with the above-
`
`captioned Petition for Inter Partes Review (“IPR”) of U.S. Patent No. 9,705,400
`
`(“the ’400 patent”) (Ex. 1001).
`
`2.
`
`I have been asked to provide my independent analysis of the ʼ400 Patent
`
`in light of the prior art patents and publications cited below.
`
`3.
`
`I have been asked to provide my opinions regarding whether certain
`
`limitations of claims 1, 2, 8, 10, and 14 (the “Challenged Claims”) of the ’400 patent
`
`were known in the art to a person having ordinary skill in the art (“POSITA”) at the
`
`time of the alleged invention and whether a POSITA would have been motivated to
`
`modify Smith’s disclosed circuit in view of Stengel.
`
`4.
`
`In preparing my Declaration, I reviewed the ’400 patent, the file history
`
`of the patent, prior art references, technical references, and the other publications set
`
`forth in the Exhibit List above from the time of the alleged invention, which are
`
`discussed herein.
`
`5.
`
`For the purposes of my Declaration, I have been asked to assume that
`
`the priority date of the alleged invention recited in the Ericsson ’400 patent is June
`
`3, 2013 (hereinafter the “Priority Date”).
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`6.
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`I am not currently, and never have been, an employee of Apple. I
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`received no compensation for this Declaration beyond my normal hourly
`
`compensation based on my time actually spent analyzing the ’400 Patent, the prior
`
`art patents and publications cited below, and issues related thereto, and I will not
`
`receive any added compensation based on the outcome of any IPR or other
`
`proceeding involving the ’400 patent.
`
`II. BACKGROUND AND QUALIFICATIONS
`7.
`I am over the age of 18 and am competent to write this Declaration. I
`
`have personal knowledge and expertise concerning the relevant technologies based
`
`upon my education, training, or experience. My relevant experience includes a deep
`
`understanding of electronic analog and digital integrated circuits and systems
`
`including circuit output stages and amplifiers.
`
`8.
`
`Below is a summary of my education and experience. My CV, filed in
`
`this proceeding as Exhibit 1007, records my education, experience, and publications
`
`in greater detail.
`
`9.
`
`I earned a Bachelor of Science degree in electrical engineering from
`
`South Dakota State University in 1983, a Master of Science degree in electrical
`
`engineering from Purdue University in 1984, and a Ph.D. in electrical engineering,
`
`also from Purdue University, in 1988.
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`10.
`
`I have over 30 years of experience in academia and industry in
`
`integrated circuits, including field programmable gate arrays (FPGAs) and systems-
`
`on-chip (SOC) designs, including memory innovation and design, as well as
`
`products integrating high-speed and high-complexity analog, digital, and mixed
`
`signal circuits including, for example, memories, analog-to-digital converters,
`
`digital-to-analog converters, and power management circuits. My teaching and
`
`product experience (design, management, and production) includes all aspects of
`
`integrated circuits covering the various packaging options including single chip,
`
`multiple chips on boards, and multi-chip modules (MCMs), and the various signal
`
`integrity requirements.
`
`11.
`
`I was a Professor of Electrical and Computer Engineering at Iowa State
`
`University from 1988–2000, teaching and performing research in very-large-scale
`
`integration (VLSI) integrated circuits and am currently a Professor-of-the-Practice
`
`in the Electrical and Computer Engineering department at Tufts University teaching
`
`integrated circuits design.
`
`12.
`
`In industry, I have held a variety of senior professional positions, at
`
`startups and leading chip companies including Hewlett-Packard, Texas Instruments,
`
`Xilinx, RocketChips and KeyEye Communications.
`
`13.
`
`I have been involved in building analog, digital, and mixed-signal
`
`integrated circuits products
`
`that
`
`involve communications, processor and
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`co-processors, analog-to-digital converters, digital-to-analog converters, and
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`serializers-deserializers (and their integration into large complex integrated SOCs),
`
`FPGAs, boards and multi-chip modules with multiple analog and digital
`
`subcomponents including power management on-chip circuitry.
`
`14.
`
`I am a named inventor on 56 issued patents and 3 pending patent
`
`applications related to highly integrated circuits with novel functionality in the areas
`
`of multi-gigabit serial transceivers, power conversion, memories, analog-to-digital
`
`converters (ADCs), digital-to-analog converters, RF devices, FPGAs, robotics, and
`
`digital signal processor filters. Additionally, I have over 70 publications that include
`
`papers on high-speed interleaved analog-to-digital converters and digital-to-analog
`
`converters.
`
`III. MATERIALS AND OTHER INFORMATION CONSIDERED
`15.
`In forming the opinions expressed in this Declaration, I relied upon my
`
`education and many years of experience in the relevant field of the art and have
`
`considered the viewpoint of a person having ordinary skill in the art (a POSITA) as
`
`of the Priority Date of the ʼ400 Patent.
`
`16.
`
`I have considered the materials referenced in this Declaration, including
`
`the ’400 Patent, its file history, and other documents listed in the Exhibit List to the
`
`ʼ400 Petition, reproduced above. In particular, I have considered the prior art
`
`references listed in the Table below.
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`Reference
`
`International Publication WO 2010/111433 A2 to
`Smith et al. (Ex. 1004)
` United States Patent No. 5,506,493 to Stengel (Ex.
`1005)
`
`Date of Public
`Availability
`September 30, 2010
`
`April 9, 1996
`
`17. The references listed in the Table above are prior art to the ’400 patent.
`
`18.
`
`Smith (Ex. 1004) was published on September 30, 2010, thus before
`
`
`
`June 3, 2013—the assumed Priority Date of the ’400 patent.
`
`19.
`
`Stengel (Ex. 1005) was published on April 9, 1996, thus before June 3,
`
`2013—the assumed Priority Date of the ’400 patent.
`
`IV. UNDERSTANDING OF PATENT LAW
`20.
`I understand that prior art to the ’400 patent includes patents and printed
`
`publications in the relevant art that predate the Priority Date of the ’400 patent.
`
`21.
`
`I understand that claims in an IPR are given their plain and ordinary
`
`meaning as understood by a person of ordinary skill in the art in view of the
`
`specification and prosecution history, unless those sources show an intent to depart
`
`from such meaning, such as where the inventor acts as their own lexicographer or
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`demonstrates an express intent to disclaim the scope of the claims, in which case the
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`claim will be given the meaning expressly advanced by the inventor or implicitly
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`advanced via the disclaimer.
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`22.
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`I understand that a patent claim is invalid if it is anticipated or obvious.
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`Anticipation of a claim requires that every element of a claim be disclosed expressly
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`or inherently in a single prior art reference, arranged in the prior art reference as
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`arranged in the claim. Obviousness of a claim requires that the claim be obvious
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`from the perspective of a POSITA at the time of the alleged invention. I understand
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`that a claim may be obvious in view of one reference or a combination of two or
`
`more prior art references.
`
`23.
`
`I understand that an obviousness analysis requires an understanding of
`
`the scope and content of the prior art, any differences between the alleged invention
`
`and the prior art, and the level of ordinary skill in evaluating the pertinent art.
`
`24.
`
`I understand
`
`that certain
`
`factors—often called “secondary
`
`considerations”—may support or rebut an assertion of obviousness of a claim. I
`
`understand that such secondary considerations include, among other things,
`
`commercial success of the alleged invention, skepticism of those having ordinary
`
`skill in the art at the time of the alleged invention, unexpected results of the alleged
`
`invention, any long-felt but unsolved need in the art that was satisfied by the alleged
`
`invention, the failure of others to make the alleged invention, praise of the alleged
`
`invention by those having ordinary skill in the art, and copying of the alleged
`
`invention by others in the field. I further understand that there must be a nexus—a
`
`connection—between any such secondary considerations and the alleged invention.
`
`I also understand that contemporaneous and independent invention by others is a
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`secondary consideration tending to show obviousness.
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`25.
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`I further understand that while it may be helpful to identify a reason for
`
`this combination, there is no rigid requirement for a teaching, suggestion, or
`
`motivation to combine. When a product is available, design incentives and other
`
`market forces can prompt variations of it, either in the same field or different one. If
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`a person having ordinary skill in the relevant art can implement a predictable
`
`variation, obviousness likely bars patentability. Similarly, if a technique has been
`
`used to improve one device, and a person having ordinary skill in the art would
`
`recognize that the technique would improve similar devices in the same way, use of
`
`the technique is obvious.
`
`26.
`
`I also understand that the following rationales may support a finding of
`
`obviousness:
`
`• Combining prior art elements according to known methods to yield
`predictable results;
`• Simple substitution of one known element for another to obtain predictable
`results;
`• Use of known technique to improve similar devices (methods, or products)
`in the same way;
`• Applying a known technique to a known device (method, or product) ready
`for improvement to yield predictable results;
`• “Obvious to try” – choosing from a finite number of identified, predictable
`solutions, with a reasonable expectation of success;
`• Known work in one field of endeavor may prompt variations of it for use
`in either the same field or a different one based on design incentives or
`other market forces if the variations are predictable to one of ordinary skill
`in the art;
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`• Some teaching, suggestion, or motivation in the prior art that would have
`led one of ordinary skill to modify the prior art reference or to combine
`prior art reference teachings to arrive at the claimed invention.
`V. OVERVIEW OF TECHNOLOGY AND OF THE ’400 PATENT
`A. Technology Background
`1. H-Bridge Circuits
`27. H-bridge circuits are common circuits to those skilled in the art.
`
`Generally, they consist of four switching elements that control the flow of current to
`
`a load and that are arranged in a H-like configuration—hence, H-bridge circuit. Hart
`
`(Ex. 1008), 331 (“the full bridge converter of Fig 8-1a is the basic circuit used to
`
`convert dc to ac”), 348 (identifying the circuit of Fig. 8-1 as an H-bridge circuit). In
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`this configuration, the four switches are in two sets of two, where each set is
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`connected through the load:
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`Id. at 332, Fig. 8-1a. “In this application, an ac output is synthesized from a dc input
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`by closing and opening the switches [S1 – S4] in an appropriate sequence. The output
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`voltage can be +Vdc, –Vdc, or zero, depending on which switches are closed.” Id. at
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`331. However, it should be noted “that S1 and S4 should not be closed at the same
`
`time, nor should S2 and S3. Otherwise, a short circuit exist across the dc source.” Id.
`
`at 332. Because switches do not turn on and off instantaneously, “switching
`
`transition times must be accommodated in the control the switches” to avoid overlap
`
`in the switches on times, which would “result in a short circuit, sometimes called a
`
`shoot-through fault, across the dc voltage source.” Id.
`
`28.
`
`It was well-known in the art that the H-bridge topology was a highly
`
`versatile switching output stage for a variety of modern applications. Perhaps the
`
`most well-known application is driving a motor. Because of the H-bridge
`
`configuration, the circuit can drive the motor either forwards or backwards by
`
`reversing the open and closed switches, thereby reversing the direction of the current
`
`and, by extension, the direction of the motor. Other well-understood applications of
`
`the H-bridge circuit are Class D power amplifiers and bridge rectifiers.
`
`2.
`Class D Power Amplifiers
`29. An amplifier is a circuit designed to increase the magnitude of its input
`
`signal. Amplifiers can broadly be classified by the particular input signals modified
`
`by the amplifier—voltage amplifiers, current amplifiers, and power amplifiers.
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`Voltage amplifiers, increase the amplitude of the output voltage of the input signal.
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`Current amplifiers increase the amplitude of the input current compared to the input
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`current signal. Finally, power amplifiers increase the power—the product of output
`
`voltage and current is greater than the product of input voltage and current.
`
`30. Power amplifiers can broadly be classified into two categories: (1)
`
`linear power amplifiers designed to generally amplify analog signals fall under, for
`
`example, Class A, B, AB, or C class power amplifiers; and (2) switching power
`
`amplifiers designed to generally amplify pulse width modulation (PWM) digital
`
`signals fall under, for example, Class D or E power amplifiers.
`
`31.
`
`It was well-known in the art that the main application for Class D
`
`amplifiers was as audio amplifiers, as Class D audio amplifiers provided power-
`
`efficiency advantages over linear audio-amplifier classes such as Class A, B, and
`
`AB in audio system design. See generally Maxim Integrated (Ex. 1009); AN-1071
`
`(Ex. 1010). Whereas significant amounts of power are lost in linear amplifiers due
`
`to biasing elements and the linear operation of output transistors, because the
`
`transistors of a Class D amplifier are just used as switches to steer current through a
`
`load, minimal power is lost due to the output stage. Maxim Integrated (Ex. 1009).
`
`32. As alluded to above, it was also understood in the art that many Class
`
`D amplifiers utilized a full H-bridge design. Maxim Integrated (Ex. 1009); AN-1071
`
`(Ex. 1010). As Smith notes, a Class D amplifier is just one type of DC-AC Inverter
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`using an H bridge AC output stage. Smith [0063]–[0064]. The full H-bridge design
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`operates by alternating the conducting path through the load, thereby allowing
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`bidirectional current to flow through the load without the need of a negative supply
`
`or a DC-blocking capacitor. This type of load connection is often referred to as a
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`bridge-tied load (“BTL”). Id.
`
`3.
`Bridge Rectifiers
`33. A bridge rectifier was well known in the art as a circuit used to
`
`transform AC to DC (i.e., an AC-DC Rectifier)—the reverse of a DC-AC Inverter
`
`described above. Conventionally, bridge rectifiers utilized four diodes arranged in
`
`series pairs. Hart (Ex. 1008), 111–12. However, it was well known in the art that the
`
`diodes could be replaced with some type of controlled solid-state components such
`
`as MOSFETs, IGBTs, or SCRs instead of the conventional diodes to create a
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`controlled bridge rectifier. Id. at 9 (contrasting transistors with diodes), 131
`
`(discussing replacing diodes in bridge rectifier with an SCR to create a controlled
`
`bridge rectifier), 94 (noting that an IGBT can replace a SCR). This allows the output
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`to be “controlled by adjusting the delay angle of each [controlled switch], resulting
`
`in an output voltage that is adjustable over a limited range.” Id. at 131.
`
`B. Overview of the ’400 Patent
`34.
`I understand that the ’400 Patent issued on July 11, 2017 from U.S.
`
`Application No. 14/889,892 (Ex. 1002) filed on November 9, 2015. For purposes of
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`this declaration, I have been asked to assume that the ʼ400 Patent is entitled to a June
`
`3, 2013 priority date, based on the European application EP13305740, to which the
`
`’400 patent claims priority.
`
`1.
`Claims
`35. The ’400 patent has 15 claims, 6 of which are independent: claims 1, 8,
`
`11, 13, 14, and 15. I understand that all of the claims relate to apparatuses or devices.
`
`For instance, claim 1 claims an “output stage adapted to operate in at least a first
`
`operating state and a second operating state,” claims 8 and 11 claim a “control
`
`apparatus,” claim 13 claims a “circuit,” claim 14 claims a “device,” and claim 15
`
`claims an “apparatus.”
`
`36. The ’400 patent has 9 dependent claims. Claims 2–7 depend from claim
`
`1; claims 9–10 depend from claim 8, and claim 12 depends from claim 11. The
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`Challenged Claims are claims 1, 2, 8, 10, and 14.
`
`2.
`Summary of the Alleged Invention
`37. The ’400 patent generally describes a circuit structure that includes an
`
`output stage that can be adapted to work with at least two subsystem circuit
`
`components, such as a Class-D amplifier and a DC-DC boost converter. ‘400 Patent
`
`(Ex. 1001), 1:44–56 (“Therefore, it is proposed an output stage suitable for use in a
`
`subsystem circuit which can be shared between at least two subsystem circuit
`
`components. . . Hence, with the above example of the audio subsystem and contrary
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`to the prior art, only one output stage is needed for both the Class-D amplifier and
`
`the DC-DC booster”). As described in the ‘400 Patent, these disclosed circuit
`
`configurations purport to solve the problem of wasted circuit die area. Id. at 5:61–
`
`6:8 (“As stated above, this [prior art] situation result in wastage of the circuit die
`
`area. In order to solve this problem, it is proposed an electronic circuit output stage
`
`adapted to operate in at least a first operating state and a second operating state”).
`
`Instead of a control stage and an output stage dedicated for use with either a Class-
`
`D amplifier or a DC-DC boost converter, the circuit described in the ‘400 patent can
`
`“operate in at least a first operating state and a second operating state, such that the
`
`output stage may be shared by at least two circuit components such as the Class-D
`
`amplifier and the DC-DC boost converter.” Id. Because the output stage may be
`
`shared by at least two circuit components, the proposed control stage would “always
`
`be in [sic] used in all associated audio configurations.” Id. at 6:1–8.
`
`38.
`
`In one embodiment described and illustrated in Figure 3, the ’400
`
`Patent describes using an H-bridge circuit structure to function as a Class-D
`
`amplifier used with an audio speaker:
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`Id. at Fig. 3 (color emphasis added). As illustrated and described, there are four
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`configurable input/output terminals labeled T1–T4. Id. at 6:66–7:24. There are also
`
`four switches S1–S4 controlled by the H-bridge control stage 10. Id. at 7:15–20
`
`(“[T]he structure of the output stage 200 . . . is an H-bridge circuit structure, thus the
`
`output stage 200 may be controlled by an H-bridge control stage 10. Namely, the
`
`switches S1, S2, S3, and S4 of the output stage 200 may be controlled by the H-
`
`bridge control stage 10.”) In this embodiment, “the first input/output terminal T1
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`and second input/output terminal T2 are configured to operate as input terminals
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`[shown in green in the annotated Fig. 3 above] and are also configured to be
`
`connected to a common node receiving a supply potential 201”. Id. at 6:66–7:2.
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`Similarly, “the third input/output terminal T3 and fourth input/output terminal T4
`
`[shown in red in the annotated Fig. 3 above] are configured to be connected to a load
`
`element,” which is illustrated here as an audio speaker 202. Id. at 7:8–10.
`
`39.
`
`In another embodiment, the ’400 patent describes modifying the circuit
`
`for use as a DC-DC boost converter configured to step up an input voltage. Id. at
`
`7:29–60. That embodiment is illustrated in Figure 4:
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`Id. at Fig. 4 (color emphasis added). In this embodiment, terminals T3 and T4 (now
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`colored in green) act as inputs, while terminals T1 and T2 (now colored in red) act as
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`outputs. Id. at 7:29–60. Terminals T3 and T4 are “short-circuited,” thus creating a
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`“short-circuit.” Id. The load element 30 is connected to terminals T1 and T2. Id.
`
`40.
`
`In another embodiment, the ‘400 patent describes modifying the circuit
`
`for use as a double DC-DC boost converter configured to step up an input voltage to
`
`two load elements. See id. at 8:30–67. That embodiment is illustrated in Figure 6:
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`
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`Id. at Fig. 6 (color emphasis added). As illustrated and described, there are two
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`separate load elements 30 and 40 in this embodiment that are each in series with a
`
`respective terminal T1 and T2 (colored in red above and acting as outputs) and in
`
`parallel to a respective capacitor 209 and 210. Id. at 8:30–67 (“[T]he first
`
`input/output terminal T1 and second input/output terminal T2 are configured to
`
`operate as output terminals. The first input/output terminal T1 is further configured
`
`to be connected, in series with a first load element 30 and in parallel with the first
`
`decoupling capacitor 209. The second input/output terminal T2 is further configured
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`to be connected, in series with a second load element 40 and in parallel with the
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`second decoupling capacitor 210”). In this embodiment, terminals T3 and T4 (colored
`
`in green above and acting as inputs) are each connected through an independent
`
`inductor to a common node receiving a supply potential 206. Id. at 8:41–50. In this
`
`configuration, as described in the ’400 patent, each branch of the structure leading
`
`to load elements 30 and 40 can be controlled independently by the control stage 20.
`
`Id. at 8:63–66 (“Also, due to the fact that each branch of the structure may be
`
`controlled independently by the control stage 20, using a DC-DC control stage
`
`enables to generate different voltage on each branch 4,5 of the output stage that may
`
`be used to supply in voltage the load elements 30,40”).
`
`3.
`
`Summary of the Prosecution History
`
`41.
`
`I have reviewed the prosecution history of the ’400 patent. The
`
`Application that issued in the ’400 patent was filed on November 9, 2015, as a
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`national phase in the United States claiming priority to International Application No.
`
`PCT/EP2014/061350 with an International Filing Date of June 2, 2014. See File
`
`History (Ex. 1002), 1. In the United States, the Application received a first action
`
`allowance, and there are no substantive rejections on the record here. See generally
`
`id. Apart from clerical changes to the claims in a Preliminary Amendment and
`
`additional changes to address minor formalities and claim dependency in an
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`Amendment After Allowance, no changes were made to the claims during
`
`prosecution in the national phase in the United States. See id. at 12–19, 215–236.
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`However, in the Notice of Allowance, the Examiner’s reason for allowance indicated
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`that the prior art of record (EP 1526643) failed to teach the claimed output stage as
`
`a whole and, more specifically, “fail[ed] to disclose wherein, when the first and
`
`second input/output terminals are configured to operate as input terminals, the third
`
`and fourth input/output terminals are configured to operate as output terminals; and,
`
`when the first and second input/output terminals are configured to operate as output
`
`terminals, the third and fourth input/output terminals are configured to operate as
`
`input terminals.” Id. at 199–200.
`
`42.
`
`In the counterpart application in the European Patent Office, the
`
`applicant submitted a claim set similar in scope to those issued in the ‘400 Patent.
`
`Compare, e.g., EPO File History (Ex. 1003), 240–41 (Claim 1) with ’400 Patent
`
`(Ex. 1001), Claim 1. The examiner there noted that “the present claims are too broad
`
`and too ambiguous to be allowable.” EPO File History (Ex. 1003), 231–32. In order
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`to position the EPO counterpart application for allowability, the applicant there was
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`prompted to limit the scope of the claims to an integrated circuit that switches
`
`between a Class-D amplifier and a DC-DC converter. Id. To that end, the applicant
`
`submitted a claim amendment adding the following limitations:
`
`wherein the integrated circuit further comprising a Class-D control
`stage and a DC-DC converter control stage wherein
`
`If Class-D control stage is connected to the output stage the DC-DC
`converter control stage is electrically disconnected from the output
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`stage, the output stage being configured to operate as a Class-D
`amplifier output stage, and,
`
`
`If the DC-DC converter control stage is connected to the output
`stage, the Class-D control stage is electronically disconnected from the
`output stage, the output stage being configured to operate as a DC-DC
`converter.
`
`
`Id. at 117. Notably, these limitations that were required for allowability in the EPO
`
`are absent from the Challenged Claims, and there are no similar limitations that limit
`
`the Challenged Claims to the subject matter found patentable there.
`
`VI. LEVEL OF ORDINARY SKILL IN THE ART
`43.
`I have been informed that a person of ordinary skill in the art is a
`
`hypothetical person who is presumed to have the skill and experience of an ordinary
`
`worker in the field at the time of the alleged invention.
`
`44.
`
`I understand that there are multiple factors relevant to determining the
`
`level of ordinary skill in the pertinent art, including the educational level of active
`
`workers in the field at the time of the alleged invention, the sophistication of the
`
`technology, the type of problems encountered in the art, and the prior art solutions
`
`to those problems.
`
`45.
`
`In determining the characteristics of a hypothetical person of ordinary
`
`skill in the art of the ’400 patent at the time of the claimed invention, I considered
`
`several things, including the type of problems encountered in this field, and the
`
`rapidity with which innovations were made. I also considered the sophistication of
`
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`the technology involved, and the educational background and experience of those
`
`actively working in the field, and the level of education that would be necessary to
`
`understand the ’400 patent.
`
`46. Finally, I placed myself back in the relevant period of time and
`
`considered the state of the art and the level of skill of the engineers working in this
`
`field at that time.
`
`47.
`
`It is my opinion that the art of the subject matter of the ’400 patent is
`
`broadly output stage circuitry. Based on the materials I have considered, and my
`
`own experience detailed above in Section II, as well as the knowledge required to
`
`understand the relevant subject matter, I came to the conclusion that the
`
`characteristics of a POSITA of the ’400 patent would be someone who had a
`
`bachelor’s degree in electrical engineering or an equivalent field with one year of
`
`experience in the field of electronic circuit design. Additional education or
`
`experience might substitute for the above requirements.
`
`48.
`
`I also note that my opinions provided in this Declaration would not
`
`change in view of minor modifications to this level of ordinary skill.
`
`VII. DETAILED INVALIDITY ANALYSIS
`A. Background on Prior Art References
`1.
`Overview of Smith (Ex. 1004)
`Smith is generally directed to a bidirectional converter that functions in
`
`49.
`
`some embodiments “as a DC to AC energy con
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