`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`——————————
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`Google LLC,
`Petitioner,
`v.
`Arigna Technology Limited,
`Patent Owner.
`_____________________________
`
`Case No. IPR2022-00685
`U.S. Patent No. 6,603,343
`_____________________________
`DECLARATION OF DAVID K. CHOI, PH.D.
`IN SUPPORT OF PETITION FOR INTER PARTES REVIEW OF
`U.S. PATENT NO. 6,603,343
`
`GOOGLE EXHIBIT 1003
`
`Page 1 of 81
`
`

`

`Declaration of Dr. David K. Choi
`U.S. Patent No. 6,603,343
`
`I.
`II.
`
`TABLE OF CONTENTS
`INTRODUCTION ................................................................................................. 1
`QUALIFICATIONS AND BACKGROUND ............................................................... 1
`A.
`Education ............................................................................................... 2
`B.
`Experience ............................................................................................. 2
`III. MATERIALS CONSIDERED ................................................................................. 6
`IV. LEGAL STANDARDS .......................................................................................... 7
`A.
`Claim Construction ............................................................................... 7
`B.
`Anticipation Under 35 U.S.C. § 102 ..................................................... 8
`C.
`Obviousness Under 35 U.S.C. § 103 ..................................................... 9
`D.
`Secondary Considerations of Non-Obviousness ................................. 11
`THE ’343 PATENT ........................................................................................... 13
`A. Overview of the ’343 Patent ................................................................ 13
`B.
`Summary of the Prosecution History of the ’343 Patent .................... 18
`C.
`Claim Construction of Terms in the ’343 Patent ................................ 21
`VI. PERSON OF ORDINARY SKILL IN THE ART ....................................................... 24
`VII. THE PRIOR ART .............................................................................................. 24
`A. Overview of Jeon ................................................................................ 24
`B.
`Overview of Yoshimasu ...................................................................... 27
`C.
`Overview of LaRosa ............................................................................ 29
`D. Overview of Garver ............................................................................ 30
`E.
`Overview of Oswald ............................................................................ 31
`F.
`Overview of Meyer .............................................................................. 33
`
`V.
`
`i
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`Page 2 of 81
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`

`

`b.
`
`c.
`
`d.
`
`Declaration of Dr. David K. Choi
`U.S. Patent No. 6,603,343
`VIII. OPINIONS ON UNPATENTABILITY .................................................................... 34
`A. Ground 1: Jeon Anticipates Claims 1, 2 ............................................. 35
`1.
`Claim 1 ...................................................................................... 35
`a.
`“A phase correction circuit for a transistor,
`comprising:” ................................................................... 35
`“a circuit element having an output terminal
`connected to a gate of a transistor to which a
`control signal line is connected, and an input
`terminal,” ........................................................................ 36
`“wherein the circuit element has a reactance that
`changes with potential difference between the
`input terminal and the output terminal; and” .................. 38
`“a voltage control circuit supplying a voltage to the
`input terminal of the circuit element so that the
`reactance of the circuit element decreases in
`response to an increase in potential of the gate,” ........... 40
`“wherein a sum of the reactance of the circuit
`element and a gate-source reactance of the
`transistor remains substantially constant.” ..................... 42
`Claim 2 ...................................................................................... 44
`a.
`“The phase correction circuit according to claim 1,
`wherein the circuit element is a diode having an
`anode as the input terminal and a cathode as the
`output terminal,” ............................................................. 44
`“the cathode of the diode is connected to the gate
`of the transistor, and” ...................................................... 44
`“the voltage control circuit supplies a reverse bias
`to the anode of the diode.” .............................................. 45
`Ground 2: Jeon and LaRosa (Ground 2A) or Jeon and Garver
`(Ground 2B) Render Obvious Claim 3. .............................................. 46
`
`B.
`
`2.
`
`e.
`
`b.
`
`c.
`
`ii
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`Page 3 of 81
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`

`

`1.
`
`b.
`
`c.
`
`Declaration of Dr. David K. Choi
`U.S. Patent No. 6,603,343
`Claim 3 ...................................................................................... 46
`a.
`“The phase correction circuit according to claim 1,
`wherein the circuit element includes a diode
`having an anode as the inputs terminal and a
`cathode as the output terminal,” ..................................... 46
`“the cathode being connected directly, or indirectly
`to the gate of the transistor, and including a
`transmission line serially connected to one of the
`anode and cathode of the diode,” ................................... 47
`“wherein the voltage control circuit supplies a
`reverse bias to the anode of the diode.” .......................... 52
`Jeon (Ground 3A) or Jeon and Oswald (Ground 3B) or Jeon
`and Meyer (Ground 3C) Render Obvious Claim 4 ............................. 53
`1.
`Claim 4 ...................................................................................... 53
`a.
`“The phase correction circuit according to claim 1,
`wherein the circuit element includes first and
`second diodes having respective anodes and
`cathodes, the cathodes are connected to each
`other,” ............................................................................. 53
`“the anode of the first diode is the output terminal
`connected to the gate of the transistor and,”................... 60
`“the voltage control circuit supplies a reverse bias
`to the anode of the second diode as the input
`terminal.” ........................................................................ 61
`Yoshimasu Anticipates Claims 1, 2, 3 (Ground 4) .............................. 62
`1.
`Claim 1 ...................................................................................... 62
`a.
`“A phase correction circuit for a transistor,
`comprising:” ................................................................... 62
`“a circuit element having an output terminal
`connected to a gate of a transistor to which a
`
`C.
`
`D.
`
`b.
`
`c.
`
`b.
`
`iii
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`Page 4 of 81
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`

`

`c.
`
`d.
`
`e.
`
`Declaration of Dr. David K. Choi
`U.S. Patent No. 6,603,343
`control signal line is connected, and an input
`terminal,” ........................................................................ 64
`“wherein the circuit element has a reactance that
`changes with potential difference between the
`input terminal and the output terminal; and” .................. 65
`“a voltage control circuit supplying a voltage to the
`input terminal of the circuit element so that the
`reactance of the circuit element decreases in
`response to an increase in potential of the gate,” ........... 67
`“wherein a sum of the reactance of the circuit
`element and a gate-source reactance of the
`transistor remains substantially constant.” ..................... 69
`Claim 2 ...................................................................................... 69
`a.
`“The phase correction circuit according to claim 1,
`wherein the circuit element is a diode having an
`anode as the input terminal and a cathode as the
`output terminal,” ............................................................. 69
`“the cathode of the diode is connected to the gate
`of the transistor, and” ...................................................... 70
`“the voltage control circuit supplies a reverse bias
`to the anode of the diode.” .............................................. 70
`Claim 3 ...................................................................................... 71
`a.
`“The phase correction circuit according to claim 1,
`wherein the circuit element includes a diode
`having an anode as the inputs terminal and a
`cathode as the output terminal,” ..................................... 71
`“the cathode being connected directly, or indirectly
`to the gate of the transistor, and including a
`transmission line serially connected to one of the
`anode and cathode of the diode,” ................................... 72
`“wherein the voltage control circuit supplies a
`reverse bias to the anode of the diode.” .......................... 72
`
`b.
`
`c.
`
`b.
`
`c.
`
`iv
`
`2.
`
`3.
`
`Page 5 of 81
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`

`

`E.
`
`Declaration of Dr. David K. Choi
`U.S. Patent No. 6,603,343
`Yoshimasu (Ground 5A) or Yoshimasu and Oswald (Ground
`5B) or Yoshimasu and Meyer (Ground 5C) Render Obvious
`Claim 4 ................................................................................................ 73
`IX. CONCLUSION ................................................................................................... 75
`
`
`
`
`
`
`v
`
`Page 6 of 81
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`

`

`I.
`
`Declaration of Dr. David K. Choi
`U.S. Patent No. 6,603,343
`
`INTRODUCTION
`1.
`I, Dr. David Choi, submit this declaration to state my opinions on the
`
`matters described below.
`
`2.
`
`I have been retained by Petitioner, Google LLC (“Petitioner” or
`
`“Google”), as an independent expert in this proceeding before the United States
`
`Patent and Trademark Office. Although I am being compensated at my usual and
`
`customary rate of $600.00 per hour, no part of my compensation depends on the
`
`outcome of this proceeding, and I have no other interest in this proceeding.
`
`3.
`
`I understand that this proceeding involves U.S. Patent No. 6,603,343
`
`(“the ’343 patent”), and I have been asked to provide my opinions as to the
`
`patentability of the claims of the ’343 patent.
`
`4.
`
`I have been asked to consider the validity of certain claims of the ’343
`
`patent based on certain prior art references. I have also been asked to consider the
`
`state of the art and prior art available as of December 18, 2001, which is the
`
`earliest claimed priority date on the face of the ’343 patent. Based on the
`
`combination of prior art references discussed in this declaration, it is my opinion
`
`that claims 1-4 of the ’343 patent are invalid for the reasons provided below.
`
`II. QUALIFICATIONS AND BACKGROUND
`5.
`I believe that I am well qualified to serve as a technical expert in this
`
`matter based upon my educational and work experience, which I summarize below.
`
`1
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`

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`Declaration of Dr. David K. Choi
`U.S. Patent No. 6,603,343
`I understand that my curriculum vitae, which includes a more detailed summary of
`
`my background, experience, patents, and publications, is being submitted as Ex-
`
`1004.
`
`A. Education
`6.
`I received my Ph.D. in Electrical and Computer Engineering from
`
`University of California, Santa Barbara in 2001. Previously, I obtained a Master of
`
`Science degree in Electrical and Computer Engineering from California State
`
`University, Fullerton in 1996, and a Bachelor of Science degree in physics from
`
`the University of California, Berkeley in 1993.
`
`B. Experience
`7.
`As of December 2001, I had approximately 7 years of professional
`
`and academic experience in research and product development in digital integrated
`
`circuit (IC) design, analog circuit design, RF/Microwave circuit design, wireless
`
`communications, and semiconductor manufacturing.
`
`8.
`
`From September 1993 to July 1994, I worked as a research assistant in
`
`the Department of Physics at the University of California, Irvine. In this role, I was
`
`responsible for analysis and design of a cryogenic camera system for mid-Infrared
`
`imaging of deep space phenomenon using (at the time) the largest available (1
`
`Megapixel, 1024x1024) Charge Coupled Device (CCD) and custom Fabry-Perot
`
`Interferometer.
`
`2
`
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`

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`Declaration of Dr. David K. Choi
`U.S. Patent No. 6,603,343
`From January 1995 to August 1996, I worked as a Digital Design
`
`9.
`
`Engineer at Western Digital Corporation in the ASIC design group (acquired by
`
`Adaptec Inc.). In this role, I used a number of industry standard VLSI design tools
`
`from Cadence, Synopsis, Meta, etc. to perform static critical delay analysis,
`
`characterize and generate libraries for custom digital logic cells, and to analyze and
`
`design clock trees and custom ASIC pad driver cells. I received an award for
`
`outstanding achievement for developing a “no re-spin” solution to correct a design
`
`error preventing a new ASIC from being powered on and was recognized for my
`
`analysis of circuit and system level meta-stable logic.
`
`10.
`
`I worked at the Nokia Research Center as a Senior Research Engineer
`
`from April 2001 to March 2006. In that role, I designed, built, and tested RF
`
`circuits (including RF power amplifiers, phase shifters, power combining
`
`networks, etc.), RF systems, and power management systems. My work included
`
`designing a novel LDMOS-based Chireix Outphasing (base station) transmitter for
`
`UMTS systems, development of an OFDM RF system simulator (with physical
`
`impairments and forward error correction (FEC)), development of baseband PAPR
`
`reduction techniques for OFDM radio systems, and development of a high power,
`
`high precision, 16-bit digitally-controlled switched-mode power supply.
`
`11. From July 2006 to February 2007, I worked as a group leader and
`
`staff engineer in the Infrastructure Products Group at RF Micro Devices. In that
`
`3
`
`Page 9 of 81
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`

`

`Declaration of Dr. David K. Choi
`U.S. Patent No. 6,603,343
`role, I worked on advanced product development, including development of a GaN
`
`HEMT dual carrier UMTS Doherty base station transmitter and a scalable GaN
`
`HEMT non-linear simulator model.
`
`12. From March 2007 to July 2008, I worked as a Section Manager of the
`
`Technology Strategy Team in Technology Intelligence & Collaboration at
`
`Samsung Electronics. In that role, I worked on technical feasibility and business
`
`opportunity analysis of nanotechnology, and market and technical analysis of
`
`biomedical electronics and THz imaging.
`
`13. From July 2008 to February 2011, I worked as a Technical Manager
`
`and Principal Engineer in the Advanced Development Group at Aethercomm, Inc.
`
`In that role, I worked on product development of pulsed/CW wideband, high
`
`power RF transmitters implemented in silicon LDMOS, GaAs FET and HBT, and
`
`GaN HEMT device technologies. I also worked on the design of other
`
`RF/microwave components such as power detectors, switches, filters, magnetics
`
`(including ferrites), phase shifters, frequency control, signal processing elements
`
`and rectangular waveguides, microwave cavities, as well as, DC power
`
`management systems, control logic, temperature compensation, fault protection,
`
`etc.
`
`14. From May 2011 to December 2012, I worked as a Senior R&D RF
`
`Hardware Engineer in R&D Hardware Engineering at LGS Bell Labs Innovations.
`
`4
`
`Page 10 of 81
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`

`

`Declaration of Dr. David K. Choi
`U.S. Patent No. 6,603,343
`In that role, I developed high power, highly-linear and efficient RF transmitter
`
`solutions for various wireless standards (including GSM/EDGE, CDMA,
`
`WCDMA, and LTE) using peak to average power reduction (PAPR) techniques,
`
`analog and digital (pre-distortion) linearization, and various high-Q (SAW, BAW,
`
`FBAR, ceramic, and cavity) filters.
`
`15. From August 2013 to March 2014, I worked as a Technical Director
`
`in the RF/microwave Power Amplifier Business Unit at Mercury Systems, Inc. In
`
`that role, I directed and led all aspects of Mercury Systems’ RF/microwave Power
`
`Amplifier Business Unit.
`
`16. Since February 2012, I have been the Principal and Owner of RF
`
`Design Concepts, Ltd. In this role, I provide consulting services, including product
`
`design and development related to RF/microwave circuits, power amplifiers, power
`
`management systems, and semiconductor fabrication, advanced IC packaging, as
`
`well as for nascent scientific research/technologies.
`
`17.
`
`In addition to my work experience in industry, I have also taught
`
`electrical engineering (microelectronics, e.g., semiconductor circuits, diodes,
`
`transistors, and transistor circuits, including transistor amplifiers) at the university
`
`level. From March 2013 to March 2014 and from August 2015 to August 2016, I
`
`was an Adjunct Professor in the Department of Electrical, Computer, and Energy
`
`Engineering at the University of Colorado, Boulder. Also, from August 2004 to
`
`5
`
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`

`Declaration of Dr. David K. Choi
`U.S. Patent No. 6,603,343
`August 2008, I was a Visiting Scholar in the Department of Electrical & Computer
`
`Engineering at the University of California, San Diego.
`
`18.
`
`I have published several technical papers in the field of electrical
`
`engineering and power amplifier design, including adaptive impedance matching.
`
`A list of these publications can be found in my curriculum vitae (Ex-1004).
`
`III. MATERIALS CONSIDERED
`In forming my opinions, I have reviewed the following documents:
`19.
`
`Ex-1006
`
`Ex-1009
`
`Ex-1010
`
`Description
`Exhibit
`Ex-1001 U.S. Patent No. 6,603,343 (“the ’343 patent”)
`Ex-1002 Prosecution History of the ’343 patent
`Ex-1005 U.S. Patent No. 6,222,412 to Jeon et al. (“Jeon”)
`Certified Translation of Japanese Patent Publication No. JPH
`0440702 to Yoshimasu et al. (“Yoshimasu”), Certificate of
`Translation of Yoshimasu, and Original Japanese Patent Publication
`No. JPH 0440702
`Ex-1007 U.S. Patent No. 3,422,378 to LaRosa (“LaRosa”)
`Ex-1008 U.S. Patent No. 3,479,615 to Garver (“Garver”)
`G. Oswald, “Application of Multiple Varactor Diodes to AM and
`FM Tuners”, 1968 IEEE International Solid-State Circuits
`Conference, Digest of Technical Papers (Feb. 1968) (“Oswald”)
`R.G. Meyer, M.L. Stephens, “Distortion in variable-capacitance
`diodes”, IEEE Journal of Solid-State Circuits, Vol. 10, Issue 1, pp.
`47-54 (Feb. 1975) (“Meyer”)
`Erickson, N. R., A Self–Biased Anti–Parallel Planar Varactor Diode.
`In Proc. Sixth Intl. Symp. Space Terahertz Tech. (Mar. 1995)
`(“Erickson”)
`Ex-1012 U.S. Patent No. 6,433,641 to Sakuno (“Sakuno”)
`Ex-1013 U.S. Patent No. 5,815,038 to Ogura (“Ogura”)
`
`Ex-1011
`
`6
`
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`

`Declaration of Dr. David K. Choi
`U.S. Patent No. 6,603,343
`Ex-1014 D. M. Pozar, Microwave Engineering, (2d ed. 1998) (“Pozar”)
`Complaint for Patent Infringement, Arigna Technology Ltd. v.
`Google LLC, No. 6:21-cv-1045 (W.D. Tex. Oct. 6, 2021), ECF No.
`1
`Ex-1018 Scheduling Order, Arigna Technology Ltd. v. Google LLC, No. 6:21-
`cv-1045 (W.D. Tex. Feb. 22, 2022), ECF No. 41
`
`Ex-1017
`
`IV. LEGAL STANDARDS
`20.
`In forming my opinions and considering the subject matter of the ’343
`
`patent and its claims in light of the prior art, I am relying on certain legal principles
`
`that counsel in this case explained to me. My understanding of these concepts is
`
`summarized below.
`
`21.
`
`I understand that the claims define the invention. I also understand
`
`that an unpatentability analysis is a two-step process. First, the claims of the patent
`
`are construed to determine their meaning and scope. Second, after the claims are
`
`construed, the content of the prior art is compared to the construed claims.
`
`22.
`
`I understand that a claimed invention is only patentable when it is
`
`new, useful, and non-obvious in light of the “prior art.” That is, the invention, as
`
`defined by the claims of the patent, must not be anticipated by or rendered obvious
`
`by the prior art.
`
`A. Claim Construction
`23.
`I understand that the United States Patent and Trademark Office
`
`interprets claim terms in an inter partes review proceeding under the same claim
`
`7
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`Declaration of Dr. David K. Choi
`U.S. Patent No. 6,603,343
`construction standard that is used in a United States federal court. I understand that
`
`under this standard, the meaning of claim terms is considered from the viewpoint
`
`of one of ordinary skill in the art at the time of the alleged invention.
`
`24.
`
`I have been informed that claim terms are generally given their
`
`ordinary and customary meaning as understood by one of ordinary skill in the art
`
`in light of the specification and the prosecution history pertaining to the patent. I
`
`understand, however, that claim terms are generally not limited by the
`
`embodiments described in the specification.
`
`25.
`
`I understand that in addition to the claims, specification, and
`
`prosecution history, other evidence may be considered to ascertain the meaning of
`
`claim terms, including textbooks, encyclopedias, articles, and dictionaries. I have
`
`been informed that this other evidence is often less significant and less reliable
`
`than the claims, specification, and prosecution history.
`
`B. Anticipation Under 35 U.S.C. § 102
`26.
`I understand that a patent claim is invalid as anticipated if a single
`
`piece of prior art teaches every element of the claims, viewed from the perspective
`
`of a person of ordinary skill in the art. I also understand that an anticipatory
`
`reference does not have to recite word for word what is in the anticipated claims.
`
`Anticipation can also occur when a claimed limitation is inherent in the relevant
`
`reference. I have been advised that if the prior art necessarily functions in
`
`8
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`Declaration of Dr. David K. Choi
`U.S. Patent No. 6,603,343
`accordance with, or includes, the claimed limitations, it can anticipate even though
`
`the limitation is not expressly disclosed.
`
`C. Obviousness Under 35 U.S.C. § 103
`27.
`I understand that a patent claim is invalid as obvious if the claimed
`
`invention would have been obvious to a person of ordinary skill in the art at the
`
`time the claimed invention was made. This means that even if all of the elements
`
`of the claim cannot be found in a single prior art reference that would anticipate the
`
`claim, a person of ordinary skill in the field who knew about all the prior art would
`
`have come up with the claimed invention. I understand that in an obviousness
`
`determination, the person of ordinary skill in the art is presumed to have
`
`knowledge of all material prior art. I understand that whether a claim is obvious is
`
`based upon the determination of several factual issues.
`
`28.
`
`In considering obviousness, I understand that one must determine the
`
`scope and content of the prior art. I understand that, in order to be considered as
`
`prior art to a patent being considered, a prior art reference must be reasonably
`
`related to the claimed invention of that patent. A reference is reasonably related if
`
`it is in the same field as the claimed invention or is from another field to which a
`
`person of ordinary skill in the art would look to solve a known problem.
`
`29.
`
`I understand that one must determine what differences, if any, existed
`
`between the claimed invention and the prior art.
`
`9
`
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`Declaration of Dr. David K. Choi
`U.S. Patent No. 6,603,343
`I understand that a patent claim composed of several elements is not
`
`30.
`
`proved obvious merely by demonstrating that each of its elements was
`
`independently known in the prior art. In evaluating whether such a claim would
`
`have been obvious, one may consider whether a reason has been identified that
`
`would have prompted a person of ordinary skill in the art to combine the elements
`
`or concepts from the prior art in the same way as in the claimed invention. There is
`
`no single way to define the line between true inventiveness on the one hand (which
`
`is patentable) and the application of common sense and ordinary skill to solve a
`
`problem on the other hand (which is not patentable). For example, market forces or
`
`other design incentives may be what produced a change, rather than true
`
`inventiveness.
`
`31.
`
`I understand that one may consider whether (1) the change was
`
`merely the predictable result of using prior art elements according to their known
`
`functions, or whether it was the result of true inventiveness; (2) there is some
`
`teaching or suggestion in the prior art to make the modification or combination of
`
`elements claimed in the patent; (3) the innovation applies a known technique that
`
`had been used to improve a similar device or method in a similar way; (4) the
`
`claimed invention would have been obvious to try, meaning that the claimed
`
`innovation was one of a relatively small number of possible approaches to the
`
`problem with a reasonable expectation of success by those skilled in the art; (5) the
`
`10
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`Declaration of Dr. David K. Choi
`U.S. Patent No. 6,603,343
`invention merely substituted one known element for another known element in
`
`order to obtain predictable results; (6) the invention merely applies a known
`
`technique to a known device, method, or product to yield predictable results, or (7)
`
`known work in the field may have prompted variations of use of the same
`
`inventions in the same or different fields due to market forces or design incentives
`
`that would have been predictable to a person of ordinary skill in the art.
`
`32.
`
`I understand that one must be careful not to determine obviousness
`
`using the benefit of hindsight; many true inventions might seem obvious after the
`
`fact. I understand that the determination should be based on the position of a
`
`person of ordinary skill in the field at the time the claimed invention was made and
`
`should not consider what is known today or what is learned from the teaching of
`
`the patent.
`
`D. Secondary Considerations of Non-Obviousness
`33.
`I understand that certain secondary considerations may be considered
`
`in evaluating obviousness in order to prevent hindsight bias. These secondary
`
`considerations include commercial success of products that practice the patent,
`
`long-felt need for the patented technology, failure by others to solve the problem
`
`addressed by the patent, initial skepticism by others in the industry, industry
`
`recognition and praise of the patented products, and efforts by others to copy the
`
`patented technology.
`
`11
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`Declaration of Dr. David K. Choi
`U.S. Patent No. 6,603,343
`I have been informed that these secondary considerations of non-
`
`34.
`
`obviousness must be balanced against the strength of the prima facie case of
`
`obviousness. Where the invention represents no more than the predictable use of
`
`prior art elements according to their established functions, secondary
`
`considerations are inadequate to establish non-obviousness.
`
`35.
`
`I have also been informed that the patentee must establish a nexus
`
`between any secondary consideration factors and the claimed invention. Where a
`
`secondary consideration factor results from something other than what is both
`
`claimed and novel in the patent, there is no nexus to the merits of the claimed
`
`invention.
`
`36.
`
`I have been informed that, for example, the nexus requirement as it
`
`applies to the evidence of commercial success requires that the patentee must show
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`that the sales of a product that allegedly practices the claimed invention must be a
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`direct result of the unique characteristics of the claimed invention, as opposed to
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`other economic and commercial factors that are unrelated to the patented
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`invention. I understand that this means if the commercial success is due to an
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`element that existed in the prior art or that is not claimed by the patent, then no
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`nexus exists.
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`37.
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`I have been further informed that, for example, the nexus requirement
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`as it applies to the long-felt need element must likewise be supported by evidence.
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`12
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`Declaration of Dr. David K. Choi
`U.S. Patent No. 6,603,343
`Where the differences between the prior art and the claimed invention are minimal,
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`it cannot be said that any long-felt need was met by the patented invention or that
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`the patent solved any technological problems that were unaddressed by others.
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`38.
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`I have been informed that evidence of industry praise must also show
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`a nexus with the claimed invention, and that self-serving statements by the patentee
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`regarding the merits of the claimed invention are generally not given weight.
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`V. THE ’343 PATENT
`A. Overview of the ’343 Patent
`39. The ’343 patent discloses a “phase correction circuit” for
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`“stabiliz[ing] a phase of an output signal of a transistor” that uses “a high-
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`frequency signal.” Ex-1001, Abstract, 1:7-9; see also id., Title. The patent explains
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`that its purpose is for this phase correction circuit to provide such stabilization,
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`even if the gate potential of the transistor “is increased by a temperature
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`compensation function, [a] temperature increase,” or “other reasons.” Id., 2:60-64.
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`40. Figure 1 of the ’343 patent shows an embodiment of the “phase
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`correction circuit 20 [that] has a diode 21 as a circuit element” and a “terminal 22,
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`functioning as a voltage control circuit.” Id., 4:54-67, FIG. 1.
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`Declaration of Dr. David K. Choi
`U.S. Patent No. 6,603,343
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`Phase correction circuit
`Voltage control circuit
`Circuit element
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`Transistor
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`Ex-1001, FIG. 1 (annotated).
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`
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`41. As shown in Figure 1 and explained in the patent, “[a] cathode of the
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`diode 21 is connected with the gate of the transistor 100,” and “[a]n anode of the
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`diode 21 is connected with the voltage-supplying terminal 22.” Id., 4:59-61.
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`Moreover, “[t]he voltage terminal 22 is supplied with Vg3=−3V. Therefore, a
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`potential of the gate is always higher than a potential of the terminal 22.” Id., 4:61-
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`63.
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`42. The patent explains that an increase in temperature causes an increase
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`in a depletion capacitance (CGS) of the transistor 100. Id., 4:39-46, FIG. 5. If the
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`transistor 100 is used in high-frequency applications, this increase in depletion
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`capacitance causes a phase shift in the output signal from the transistor 100, which
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`is undesirable and prevents the high frequency circuit 200 from working properly.
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`Id., 1:66-2:6.
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`Declaration of Dr. David K. Choi
`U.S. Patent No. 6,603,343
`43. The ’343 patent purports to solve this problem using the
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`aforementioned phase correction circuit, by compensating for the increasing
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`depletion capacitance of transistor 100 with an off-setting, decreasing depletion
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`capacitance of the diode 21. Specifically, the patent explains that the depletion
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`capacitance (Cd)1 of the diode 21 can be “decrease[d] inversely with the increase
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`in depletion capacitance CGS . . . .” This is accomplished by adjusting a potential
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`difference Vab2 between a terminal-a and a terminal-b of the diode 21, using the
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`voltage-supplying terminal 22. Id., 4:46-57, 5:17-22, FIG. 7. Because the depletion
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`capacitance (Cd) of the diode 21 changes inversely with the depletion capacitance
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`(CGS) of the transistor 100, the “total capacitance of Cd and CGS is maintained
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`constant irrelevant to the temperature.” Id., 5:30-32, FIG. 9.
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`44. This effect can best be shown by a combination of Figures 5, 7, and 9,
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`which show how the increasing capacitance CGS of the transistor 100 (Figure 5, left
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`below) and the inversely decreasing capacitance Cd of the diode 21 (Figure 7,
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`middle below) combine to create a total capacitance Cd + CGS that is constant
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`(Figure 9, right below):
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`
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`1 The patent refers to Cd as both a “depletion capacitance” and a “reactance
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`component.” E.g., Ex-1001, 4:46-47, 5:3, 5:17-18, 5:34-35.
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`2 The potential difference, Vab, is a reverse-bias voltage across diode 21.
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`Declaration of Dr. David K. Choi
`U.S. Patent No. 6,603,343
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`
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`Ex-1001, FIGs. 5, 7, 9 (annotated).
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`
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`45. But the ’343 patent’s phase correction circuit, including the precise
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`configuration of the diode and the voltage-supplying terminal, was well known in
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`the art, as evidenced by prior art references such as Jeon, Yoshimasu, discussed in
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`more detail below. As the ’343 patent concedes, its phase correction circuit
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`operates based on the “well-known character” that the depletion capacitance of a
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`reverse biased diode will decrease as the potential difference Vab of the diode
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`decreases.” Ex-1001, 5:20-22.
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`46. The ’343 patent