Iie Transactions
`
`ISSN: 0740-817X (Print) 1545-8830 (Online) Journal homepage: https://www.tandfonline.com/loi/uiie20
`
`A REVIEW OF PRODUCTION PLANNING AND
`SCHEDULING MODELS IN THE SEMICONDUCTOR
`INDUSTRY PART I: SYSTEM CHARACTERISTICS,
`PERFORMANCE EVALUATION AND PRODUCTION
`PLANNING
`
`REHA UZSOY , CHUNG-YEE LEE & LOUIS A. MARTIN-VEGA
`
`To cite this article: REHA UZSOY , CHUNG-YEE LEE & LOUIS A. MARTIN-VEGA
`(1992) A REVIEW OF PRODUCTION PLANNING AND SCHEDULING MODELS IN THE
`SEMICONDUCTOR INDUSTRY PART I: SYSTEM CHARACTERISTICS, PERFORMANCE
`EVALUATION AND PRODUCTION PLANNING, Iie Transactions, 24:4, 47-60, DOI:
`10.1080/07408179208964233
`To link to this article: https://doi.org/10.1080/07408179208964233
`
`Published online: 31 May 2007.
`
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`https://www.tandfonline.com/action/journalInformation?journalCode=uiie21
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1026, IPR2022-00681, Pg. 1
`
`

`

`A REVIEW OF PRODUCTION PLANNING AND SCHEDULING MODELS
`IN THE SEMICONDUCTOR INDUSTRY
`PART I: SYSTEM CHARACTERISTICS, PEIU'ORMANCE EVALUATION
`AND PRODUCTION PLANNING
`
`REHA UZSOY
`School of Industrial Engineering. Purdue University. West Lafayette. IN 47907
`
`CHUNG-YEE LEE
`Department of Industrial and Systems Engineering. University of Florida, Gainesville. FL 32611
`
`LOUIS A. MARTIN-VEGA
`National Science Foundation, Washington. DC 20550
`Florida Institute of Technology, Melbourne, FL (on leave)
`
`Although the national importance of the semiconductor industry is widely acknowledged. it is only recently that the production
`planning and scheduling problems encountered in this environment have begun to be addressed using industrial engineering and
`operations research .techniques. These problems have several features that make them difficult and challenging: random yields
`and rework. complex product flows, and rapidly changing products and technologies. Hence their solution will contribute con(cid:173)
`siderably to the theory and practice of production planning and control. In a two-part project we present a review of research
`in this area to date. discuss the applicability of the various approaches and suggest directions for future research. In this paper.
`Part I. we describe the characteristics of the semiconductor manufacturing environment and review models related to perform(cid:173)
`ance evaluation and production planning. Part II will review research on shop-floor control in this industry to date.
`
`• The miniaturization of electronic components by
`means of Very Large Scale Integration (VLSI) technol(cid:173)
`ogies has been one of the most significant technological
`developments of the last fifty years. Improving tech(cid:173)
`nologies and decreasing prices have led to integrated
`circuits appearing in all walks of life. The computer
`revolution of the past two decades is a direct result of
`the ability to develop and fabricate these components
`economically. The development of Computer-Integrated
`Manufacturing (CIM) systems, essential to the mainte(cid:173)
`nance of competitive edge in today's highly competitive
`global markets, is directly linked to the availability of
`the integrated circuits necessary for their implementa(cid:173)
`tion. Integrated circuits are also used in a wide range
`of industries such as domestic appliances, cars and avi(cid:173)
`onics. Although the industry is facing heavy competi(cid:173)
`tion from overseas, especially from the Pacific Rim
`countries, it is only recently that the operational aspects
`of semiconductor- manufacturing have been addressed
`and attempts made to apply industrial engineering and
`operations research techniques to these problems.
`The goal of this paper is to provide an overview of
`the semiconductor manufacturing process, its character(cid:173)
`istics and management objectives and review research
`efforts in production planning and scheduling in this
`
`industry to date. We classify this work based on the
`problems addressed. The problem areas we consider
`are the following:
`
`1. Performance evaluation. Models whose objective
`is descriptive rather than prescriptive in nature, used
`for understanding the behavior of a given system;
`
`2. Production planning. Long-term, more aggregate
`production planning with a time horizon of months
`or weeks;
`
`3. Shop-floor control, which addresses the questions
`of how much material to start into the facility and
`how to control the material once started.
`
`Clearly, there are several. applications that fit more
`than one of these categories. The literature on shop(cid:173)
`floor control is further subclassified by the approaches
`used as input regulation and dispatching rules, deter(cid:173)
`ministic scheduling algorithms, control-theoretic ap(cid:173)
`proaches and knowledge-based systems. The structure
`of this classification is shown in Figure I. In this paper
`we discuss the manufacturing process and management
`objectives, and review performance evaluation and pro-
`
`September 1992, lIE Transactions, Volume 24, Number 4
`
`0740-817X/92/$3.00x.OO © 1992 "lIE"
`
`47
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1026, IPR2022-00681, Pg. 2
`
`

`

`I
`
`Performance
`Evaluation
`
`I~~
`
`J
`
`IE
`
`PrOOuClion
`Planni::lland
`SChedulng
`
`Shop-Floor
`Control
`
`PrOOuction
`Planning
`
`Knowledge(cid:173)
`Based
`Approaches
`
`Detenninistic
`SCheduling
`
`Control
`Theoretic
`Approaches
`
`Dispatching and
`InputRegulation
`
`Agure 1. Classification of production planning and scheduling research
`
`itations, it is highly likely that some contributions have
`been inadvertently omitted, for which we apologize in
`advance.
`
`The Semiconductor Manufacturing Process
`
`The process by which very large-scale integrated cir(cid:173)
`cuits are manufactured can be divided into four basic
`steps: wafer fabrication, wafer probe, assembly or pack(cid:173)
`aging and final testing (Figure 2).
`Wafer fabrication is the most technologically com(cid:173)
`plex and capital intensive of all four phases. It involves
`the processing of wafers of silicon or gallium arsenide
`in order to build up the layers and patterns of metal
`and wafer material to produce the required circuitry.
`The number of operations can be well into the hundreds
`for a complex component. such as a microprocessor.
`Many of these operations have to be performed in a
`clean-room environment to prevent particulate contami(cid:173)
`nation of the wafers. The facility in which wafer fab(cid:173)
`rication takes place is referred to as a waferJab. Product
`moves through the fab in lots, often of a constant size
`
`Packaged
`Circuit
`
`Tested Circuit
`
`Testing
`Brand
`Bum-in
`. Quality
`Assurance
`
`duction planning models. Research on shop-floor con(cid:173)
`trol problems is reviewed in Part II [69].
`We have focused on production planning and sched(cid:173)
`uling applications in the semiconductor industry at the
`expense of other important areas such as product de(cid:173)
`sign and chip allocation [3], [35], [62], process mod(cid:173)
`eling and improvement (e.g., [52]) and implementation
`of Just-in-Time manufacturing [49]. We have also not
`included the extensive literature on lot-sizing in the
`presence of random yields since a survey of this liter(cid:173)
`ature has already been carried out by Yano and Lee
`[76]. There is also a large body of industrial engineering
`and operations research literature which is relevant to
`the problems encountered in the semiconductor indus(cid:173)
`try. In order to avoid diversifying into a survey of the
`entire area of production planning and scheduling, we
`shall not review this literature in detail but instead give
`references and discuss its relevance to problems in the
`semiconductor industry, with the hope of bringing them
`to the attention of practitioners and researchers. While
`we have made every effort to make this survey as com(cid:173)
`prehensive as possible within the above-mentioned lim-
`
`Die
`
`mt
`
`l±1I
`
`Wafer
`
`Wafer Fabrication
`
`Wafer Probe
`
`Assembly
`
`Final Test
`
`Figure 2. Basic steps of the semiconductor manufacturing process
`
`48
`
`lIE Transactions, September 1992
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1026, IPR2022-00681, Pg. 3
`
`

`

`based on standard containers used to transport wafers.
`While the specific operations may vary widely depend(cid:173)
`ing on the product and the technology in use, an idea
`of the processes in wafer fabrication can be seen in Fig(cid:173)
`ure 3 [14]. Brief descriptions of the various operations
`are given in the Appendix. This sequence of operations
`is repeated for each layer of circuitry on the wafer. De(cid:173)
`tailed descriptions of the technologies used in wafer fab(cid:173)
`rication can be found in texts on this subject such as
`Sze [68] and Runyan and Bean [60].
`In wafer probe, the individual circuits, of which there
`may be hundreds on each wafer, are tested electrically
`by means of thin probes. Circuits that fail to meet speci(cid:173)
`fications are marked with an ink dot. The wafers are
`then cut up into individual circuits and the defective
`circuits discarded.
`Wafer fabrication and probe are generally referred
`to as "front-end" operations. The following stages, as(cid:173)
`semblyand final test, are referred to as the "back-end."
`In the back-end operations, lots may vary in size from
`several individual circuits to several thousand. The ac(cid:173)
`tual sequence of operations a lot will go through de(cid:173)
`pends on the product and on customer specification.
`These characteristics are due to the fact that a lot is gen(cid:173)
`erally more closely associated with a particular order
`and customer than is the case in wafer fab or probe.
`In assembly the circuits are placed in plastic or ce(cid:173)
`ramic packages that protect them from the environment.
`There are many different types of packages, such as
`plastic or ceramic dual in-line packages, leadless chip
`carriers, and pin-grid arrays. Since it is possible for
`a given circuit to be packaged in many different ways,
`there is a great proliferation of product types at this
`stage. Once the leads have been attached and the pack(cid:173)
`age sealed and tested for leaks and other defects, the
`product is sent to final test.
`
`The goal of the testing process is to ensure that cus(cid:173)
`tomers receive a defect free product by using automated
`testing equipment to interrogate each integrated circuit
`and determine whether it is operating at the required
`specifications. While the specific product flow varies
`considerably, a broad idea can be formed from Figure
`4. Brief descriptions of the main operations taking place
`in the testing area are given in the Appendix.
`An important characteristic of the testing process from
`a production planning standpoint is the downgrading
`or binning that takes place here. A circuit, when tested,
`may not meet the specification it was originally built
`for, but may meet another less rigorous one. For ex(cid:173)
`ample, a microprocessor intended to operate at 20MHz
`may fail at that frequency but may pass tests at 16MHz.
`Thus when a lot is tested a number of differentgrades
`of product may emerge, resulting in not enough of the
`desired product being available and unwanted inventory
`of the lower grade product. Itis also possible to use
`inventory of higher-grade product to meet demand of
`a lower-grade product.
`We can highlight the following factors that make pro(cid:173)
`duction planning and scheduling in the semiconductor
`industry particularly difficult. Similar discussions can
`be found in Bai and Gershwin [4] and Hughes and Shott
`[36].
`
`1. Complex Product Flows: The number of process
`steps is high, and a number of these steps take place
`on the same production equipment. For example,
`a wafer may have to visit the photolithography work(cid:173)
`station eight or nine times to have all layers of cir(cid:173)
`cuitry fabricated. These product flows, where a lot
`visits a workcenter more than once, are known as
`. reentrant product flows.
`
`Cleaning
`
`Oxidation
`Deposition
`Metallization
`
`Uthography
`
`Inspection
`and
`Measurement
`
`Etching
`
`1
`
`Ion
`Implantation
`
`1
`
`Photoresist
`Strip 1 -
`
`Figure 3. Basic operation sequence for wafer fabrication
`
`September 1992, lIE Transactions
`
`49
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1026, IPR2022-00681, Pg. 4
`
`

`

`Figure 4. Example product flow through final testing facility
`
`2. Random Yields: Process yields are uncertain and vary
`due to environmental conditions, problems with pro(cid:173)
`duction equipment or material. In the testing stage
`there is also the issue of downgrading described
`above. Yields for well-established products may be
`predicted using historical data, but the constant in(cid:173)
`troduction of new products and technologies makes
`yield estimation a major problem. Cunningham [18]
`provides a survey and comparison of statistical yield
`estimation models in use in industry. Another detri(cid:173)
`mental effect of yield problems is the large amount
`of engineering hold time on both lots and equipment
`while troubleshooting is in progress.
`
`3. Diverse Equipment Characteristics: The character(cid:173)
`istics of the equipment used in semiconductor man(cid:173)
`ufacturing vary widely. Some machines have signifi(cid:173)
`cant sequence-dependent setup times, while others
`do not. Some workcenters such as etching and bum(cid:173)
`in consist of batch processing machines, where a
`number of lots are processed simultaneously as a
`batch. There are critical time windows between sev(cid:173)
`eral processes, such as between bum-in and test
`where a lot has to be tested within 96 hours of leav(cid:173)
`ing burn-in or repeat the entire bum-in sequence.
`
`4. Equipment Downtime: The production equipment
`used in semiconductor manufacturing is technologi(cid:173)
`cally extremely sophisticated. It requires extensive
`preventive maintenance and calibration, and is still
`subject to unpredictable failures. It is estimated that
`the main cause of uncertainty in semiconductor man(cid:173)
`ufacturing operations is due to unpredictable equip(cid:173)
`ment downtime [34], [45], which is also cited as a
`major contributor to the cost advantage of overseas
`manufacturers,
`
`50
`
`5. Production and Development in Shared Facilities:
`Due to the constant development of new products
`and processes, very often the same equipment is used
`for both production lots and engineering test and
`qualification lots. The conflicting goals of the man(cid:173)
`ufacturing and the engineering organizations add to
`the confusion.
`.
`
`6. Data Availability and Maintenance: The sheer vol(cid:173)
`ume of data in a semiconductor manufacturing fa(cid:173)
`cility makes data acquisition and maintenance an
`extremely time-consuming and difficult task. Sulli(cid:173)
`van and Fordyce [67] give the transaction volume
`in an IBM wafer fab as 240,000 per day. For each
`operation a product undergoes, information like proc(cid:173)
`essing times and yields has to be stored. The con(cid:173)
`stant introduction of new product types to keep up
`with the changing markets further complicates this
`problem, which is also compounded as one moves
`from the front-end towards the final testing stages
`due to multiple packaging and co-production possi(cid:173)
`bilities.
`
`The main focus of manufacturing strategies in the
`semiconductor industry is on minimizing production
`costs and increasing productivity while improving both
`quality and delivery time performance, Major factors
`affecting costs are yield, labor, materials, inventory,
`equipment and facility depreciation and number of starts
`per week [36]. The major forces in the industry to date
`have been the manufacturers of standard products in
`fairly high volumes. In these operations, a common ap(cid:173)
`proach has been to buffer the wafer fabs against flue(cid:173)
`tuations in the external demand by holding inventories
`of probed die, referred to as die-bank inventories, be(cid:173)
`tween the front-end and back-end operations. Hence
`
`lIE Transactions, September 1992
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1026, IPR2022-00681, Pg. 5
`
`

`

`wafer fabs have tended to operate in a make-to stock
`mentality, with production lots rarely being associated
`with a specific customer order or due date. Together
`with the high capital costs of equipment, this has resulted
`in a major emphasis on maintaining high throughput
`and equipment utilization, while reducing both the mean
`and the variance of cycle times (the time between a lot
`being started into the fab and the completion of the lot)
`and inventories.
`However, there is fair agreement [34], [36], [45] that
`the Application-Specific Integrated Circuit (ASIC) mar(cid:173)
`ket, in which small lots of custom circuits are designed
`and manufactured on a one-time basis, will gain impor(cid:173)
`tance in the future. In these facilities, a much broader
`range of products is produced, and each order is often
`clearly identified with a specific customer. Hence the
`fab becomes more tightly coupled to the back-end op(cid:173)
`erations, since the application specific nature of orders
`will render it impossible to hold die-bank inventories
`between the front-end and back-end operations. As a
`result, ASIC manufacturers will be under heavy pres(cid:173)
`sure to achieve good cycle time and delivery perform(cid:173)
`ance and to increase yields with a much broader product
`mix than the current volume manufacturers. The ope(cid:173)
`rational control problems in these facilities will thus
`be different from those in the high volume manufactur(cid:173)
`'ing environments.
`Assembly and final test have until recently been fairly
`low investment, labor-intensive operations with short
`cycle times compared to fabrication. As a result, the
`vast majority of research efforts in production planning
`and control in the semiconductor industry have been
`directed towards wafer fab at the expense of these op(cid:173)
`erations. However, the problems here are no less dif(cid:173)
`ficult than those in fab. Complex, reentrant product
`flows, uncertain yields and unreliable equipment are
`also present here. The more sophisticated devices be(cid:173)
`ing developed are leading to more complex testing and
`packaging machinery, which is increasing the capital(cid:173)
`intensity of these operations. The fact that these ope(cid:173)
`rations are closer to the customer means that lots are
`associated with specific customers and due dates which
`must be met for good delivery performance to be
`achieved. Hence, due date based performance measures
`are appropriate for these operations, with due consid(cid:173)
`eration to controlling cycle times and WIP levels. In
`addition, there are many more different products that
`must be produced and tracked, due to the fact that a
`given die can be packaged in many different ways and
`can have different test specifications associated with it.
`The increasing investment level, pressure to provide
`good customer service and the tight coupling of these
`
`operations with the front-end in ASIC manufacturing
`will result in effective management of these operations
`becoming much more critical to a company I S success
`than they have been perceived to be to date.
`While there seems to be broad agreement throughout
`the industry on the corporate-level goals cited above,
`there seems to be no consensus on how to go about
`achieving these goals. A major issue is how to translate
`corporate objectives into appropriate performance meas(cid:173)
`ures for individual departments and managers, and how
`to implement these in planning and scheduling systems.
`Many departments seem to have potentially conflicting
`objectives. For example, marketing personnel are of(cid:173)
`ten evaluated on the number of orders they generate,
`while shop floor management is measured on meeting
`production goals expressed as quantities and deadlines.
`As a result,
`it may be possible for the marketing de(cid:173)
`partment to book more orders than the production ca(cid:173)
`pacity can possibly handle, which leads to degeneration
`of the production planning and control mechanisms. Har(cid:173)
`rison et al. [34] give an extremely interesting discus(cid:173)
`sion of these issues, pointing out that in order to be
`successful, the issues of production control, shop-floor
`control and appropriate incentives and goals for person(cid:173)
`nel have to be considered in an integrated manner. The
`fact that operations are often distributed among differ(cid:173)
`ent plants in different locations, and often different coun(cid:173)
`tries, accentuates this problem [44].
`In order to address the complexities and performance
`pressures in the industry. automation towards Computer(cid:173)
`Integrated Manufacturing (CIM) has been advocated for
`some time. Hughes and Shott [36], Levinstein [45], Reid
`et al. [58] and Wise [75] describe the need for auto(cid:173)
`mation and research efforts in progress in this area.
`Many manufacturers have adopted fairly complex fac(cid:173)
`tory automation (FA) systems already [16]. These sys(cid:173)
`tems address many different aspects of automation, from
`the automation of individual process steps to the devel(cid:173)
`opment of integrated, automated factories. However.
`this complete integration of the automated factory has
`not yet been achieved, and the existing systems do not
`reflect the state of the art in industrial engineering and
`operations research.
`
`Performance Evaluation
`
`In this section we discuss models used for evaluating
`the performance of a given system configuration rather
`than optimizing some measure of system performance.
`These models are discussed first because the insights
`they offer form an important input into the production
`planning and scheduling function. Examples of their
`
`September 1992, lIE Transactions
`
`51
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1026, IPR2022-00681, Pg. 6
`
`

`

`use are the evaluation of different machine configura(cid:173)
`tions and types based on throughput using queueing net(cid:173)
`works or examining the effects of extra capacity at
`bottleneck workcenters using simulation. Simulation
`models have also been used extensively to evaluate the
`performance of production planning and scheduling
`strategies, which we shall discuss later and in Part 2
`of this paper [69].
`
`Queueing Models
`Queueing networks [70] have been used extensively
`to model semiconductor manufacturing facilities. Bur(cid:173)
`man et al. [14] report applications of these models, and
`point out a number of features such models must have
`to be applicable in semiconductor environments: multi(cid:173)
`server nodes, general service times, general interarriv(cid:173)
`al times, customer routing and batching and splitting
`of lots. The assumptions that need to be made in order
`to render these models analytically tractable sometimes
`limit the accuracy of these models, but Burman et al.
`[14] report the use of software packages like QNA [74]
`and PANACEA [57] in a number of applications. The
`values of the parameters of interest obtained from the
`queueing models deviated from the values obtained from
`simulation by between 7 % and 20 %, but run times were
`much shorter than the simulations.
`Chen et al. [15J develop a queueing network model
`of a research and development wafer fab operation. A
`network with a number of different types of customer,
`corresponding to different lot types, is presented. En(cid:173)
`gineering hold time is modelled as an infinite server
`node. The model is of a mixed nature, that is, open
`for certain classes of customers (representing regular
`production lots) and closed for others (representing re(cid:173)
`search and development lots). After defining parameters
`such as expected number of visits to each station and
`station service rates, an iterative procedure is used to
`arrive at throughput rates for the entire network and
`other quantities of interest such as average throughput
`time per customer at each station. The results obtained
`from the model are compared with actual observed data
`and found to be in close agreement. This model is also
`interesting in that it addresses the presence of both pro(cid:173)
`duction and development lots in the same facility.
`In a unique paper, Wein [73J examines the relation
`between yield and cycle time using a simple queueing
`model of a wafer fab. He modifies the Poisson yield
`model [18], which assumes that defects are uniformly
`distributed on the die, by assuming that the mean num(cid:173)
`ber of defects per die is a linear function of the time
`the wafer spends in the fab. Defining throughput rate
`to be the mean number of non-defective die produced
`
`per unit time, he derives a closed-form relation between
`the mean time the wafers spend in the fab and the
`throughput rate. In particular, he shows that through(cid:173)
`put rate is not a monotonically increasing function of
`start rate and that increasing the start rate above a cer(cid:173)
`tain critical level actually causes a significant decrease
`in the output of non-defective die. While the queueing
`model used is simple, the intuitive results of this paper
`are of great interest since they are the first to address
`analytically the interrelations between scheduling and
`yield. A similar analysis has been undertaken by Ber(cid:173)
`trand and Wortmann [10], which shows that very slight
`improvements in cycle time due to better scheduling
`can lead to substantial yield improvements.
`
`Simulation Models
`Digital simulation is one of the most extensively used
`. operations research tools in the semiconductor industry
`today [1], [2], [9], [14], [19], [20], [21], [24], [271,
`[28], [29J, [30], [37J, [42], [43], [47J, [50J, [51], [53],
`[54], [55], [59], [65], [71]. The reasons for this are
`the intractability of detailed analytical models of the
`semiconductor manufacturing process, the uncertainties
`inherent in the manufacturing process itself, and the
`steady improvement
`in computer technology which
`makes building simulation models easier and reduces
`the computational expense of the resulting models. Sim(cid:173)
`ulation models can also be developed at different levels
`of detail: a highly detailed model of a particular proc(cid:173)
`ess step or workcenter, or a more aggregate model of
`an entire facility or subsystem.
`Considerable effort has gone into the development
`of simulation models for wafer fabs and their use to
`analyze the effects of different control strategies and
`equipment configurations. As many of these efforts are
`discussed in Part II, we shall only describe a number
`of applications not dealing directly with control strat(cid:173)
`egies in this section.
`In some of the earliest work on simulating wafer fabs,
`Dayhoff and Atherton [19], [20], [21] present simula(cid:173)
`tion models of wafer fabs and use them to analyze sys(cid:173)
`tem performance in a number of different ways. Since
`their approach appears to be representative of many
`other such efforts, we shall describe it in some detail.
`This approach is based on modelling a fab as a queue(cid:173)
`ing network. The components of the model are wafer
`lots, products and process flows. Each product is as(cid:173)
`sociated with a sequence of process steps, called a prod(cid:173)
`uct flow. Lots move from workstation to workstation
`according to the product flow. Batch processing is al(cid:173)
`lowed, where a number of lots may be processed to(cid:173)
`gether, or a large lot broken up into smaller lots
`
`52
`
`TIE Transactions, September 1992
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1026, IPR2022-00681, Pg. 7
`
`

`

`according to machine capacity. This model is then used
`as a basis for analyzing system performance. In a se(cid:173)
`ries of two papers [20], [21] these authors make use
`of a technique called signature analysis to characterize
`. the behavior of wafer fabs and to examine the effects
`of different dispatching rules. The signature of a fab
`is obtained by plotting the cycle time, inventory level
`and throughput obtained from simulation runs against
`the start rate of wafers into the fab. The authors give
`examples of the use of the signatures by discussing at
`length the signatures obtained from the simulation of
`an example fab. The model discussed above has been
`extended into the ACHILLES software system [2],
`which is commercially available.
`Spence and Welter [65] use a simulation model to
`examine the performance of a photolithography work(cid:173)
`cell based on a similar throughput-cycle time tradeoff.
`This is claimed to be preferable to signature analysis
`for the study of long-term steady-state behavior. The
`effects of adding resources such as operators and ma(cid:173)
`chines, improving the process by reducing setups and
`rework, and various operational rules are examined.
`Adding resources was found to reduce cycle time,
`though diminishing returns were noted. Effective ca(cid:173)
`pacity increased substantially as setups and rework were
`reduced, and cycle times improved greatly as lot sizes
`were reduced.
`A number of researchers have developed specialized
`languages for wafer fab simulation. Such a language
`is described by Pollak [541. who develops a preproces(cid:173)
`sor that is then linked to the SIMAN simulation lan(cid:173)
`guage. Resende [59] describes a specialized language
`for wafer fab simulation called FabSim, which was used
`in the evaluation of the Bottleneck Starvation Avoidance
`rule [28], [29]. An object-oriented simulation package
`developed at UC Berkeley has been used in semicon(cid:173)
`ductor environments with considerable success. This
`package, called the Berkeley Library of Objects for Con(cid:173)
`trol and Simulation (BLOCS) is described by Adiga and
`Glassey [1] and Glassey (27]. Leachman and Sohoni
`[43] and Najrni and Lozinski [51] describe the use of
`this system as part of a participative management sys(cid:173)
`tem by a major semiconductor manufacturer. The sys(cid:173)
`tem is used to set shift production targets and to enable
`rapid performance evaluation and troubleshooting, and
`has been successfully implemented.
`Phillips et al. (53] describe a manufacturing produc(cid:173)
`tivity workstation used for the design and analysis of
`wafer fabs. The approach of the 'system is to model the
`fab as a network of queues. The system's process flow
`analysis module is used to obtain rough-cut analyses
`of the system such as bottleneck machine identification
`
`and costing. The equilibrium flow rates obtained from
`this module are then input to a detailed queueing anal(cid:173)
`ysis module. Further analysis using simulation is pos(cid:173)
`sible via a special-purpose simulation language devel(cid:173)
`oped for this purpose. The results of all the three mod(cid:173)
`ules can also be used for cost analysis.
`
`Conclusions .and Future Directions
`The area of performance evaluation modelling seems
`to be the most technologically mature of the three prob(cid:173)
`lem areas considered in this review. There has been
`substantial progress both in the areas of queueing net(cid:173)
`works and simulation. Both techniques are extensively
`used in practice and complement one another. with
`queueing models being used for fast, approximate anal(cid:173)
`yses while simulation models are developed for detailed
`studies which take considerably longer. The most vis(cid:173)
`ible problems here are the restrictive assumptions upon
`which many of the queueing models are based, and the
`long time necessary to develop and run the large sim(cid:173)
`ulation models required to model complex facilities. An
`interesting approach to combining the advantages of both
`these methods is the work on hybrid models combining
`analytical and simulation components which would pro(cid:173)
`vide an interesting direction for future research in this
`area. Some examples of this type of model are described
`by Shanthikumar and Sargent [61].
`
`Production Planning
`
`In this section we examine systems used for high-level,
`comparatively long-term production planning, with a
`planning horizon of months or weeks. A number of these
`systems, notably the control-theory based hierarchy of
`Bai et al. [8] and the constraint-based system of Hadavi
`and Voigt [32] also contain shop-floor control compo(cid:173)
`nents. However, in contrast to the models described
`in the next section, these systems all try to take into
`account long-term goals and translate these into mean(cid:173)
`ingful task assignments for lower-level planning systems.
`As was mentioned in the previous section, factory
`automation systems have been implemented in a large
`number of facilities. From the point of view of produc(cid:173)
`tion planning and scheduling. these systems typically
`[16] provide real-time WIP tracking capabilities and
`have production planning and scheduling components.
`However, the capabilities are somewhat limited. The
`production planning components generally assume the
`availability of a feasible master production schedule,
`while the shop-floor co