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`(19) Japan Patent Office (JP)
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`(11) Japanese Unexamined Patent
`Application Publication Number
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`(12) Japanese Unexamined Patent
`Application Publication (A)
`
`H4-40702
`
`(51) Int. Cl.5
`
`Identification
`codes
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`JPO file numbers
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`(43) Publication date February 12, 1992
`
`
` H03F 3/60 8836-5J
`
` H01P 5/08 L 7741-5J
`
` H03F 3/19 8326-5J
`
`Request for examination: Not yet requested Number of claims: 1 (Total of 7 Pages)
`
`(54) Title of the invention
`
`MICROWAVE CIRCUIT
`
`
`
`(21) Japanese Patent Application
`
`H2-148933
`
`(22) Date of Application
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`June 6, 1990
`
`(72) Inventor
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`YOSHIMASU, Toshihiko
`
`℅ Sharp Corp.
`22-22 Nagaike-cho, Abeno-ku, Osaka City, Osaka-fu
`
`Sharp Corp.
`
`22-22 Nagaike-cho, Abeno-ku, Osaka City, Osaka-fu
`
`(71) Applicant
`
`(74) Agent
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`SPECIFICATION
`
`
`1. TITLE OF THE INVENTION
`Microwave Circuit
`2. PATENT CLAIMS
`A microwave circuit wherein an active element for
`amplifying a microwave input signal and an
`impedance matching circuit for matching an
`input/output impedance of an active element to an
`impedance of a neighboring input/output circuit are
`formed on a substrate, wherein:
`the impedance matching circuit includes:
`an input transmission line for transmitting a
`microwave input signal to the active element;
`an output transmission line for transmitting a
`microwave output signal from the active element;
`a diode, connected in parallel to the active element,
`for correcting a capacitance variance in the active
`element; and
`control voltage supplying means for supplying a
`control voltage to the active element and the diode so
`as to change, inversely in respect to each other, the
`capacitance of the active element and the capacitance
`of the diode.
`3. DETAILED EXPLANATION OF THE INVENTION
`[FIELD OF APPLICATION IN INDUSTRY]
`The present invention relates to a microwave
`circuit, and, in particular, relates to a microwave
`circuit comprising an active element for amplifying a
`microwave signal and an impedance matching circuit
`for matching the input/output impedance of the active
`element to the impedance of an adjacent input/output
`circuit.
`
`Patent attorney FUKAMI, Hisao
`
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`and 2 others
`
`[PROBLEM SOLVED BY THE PRESENT INVENTION]
`In recent years, with advancements in development
`of field-effect transistors (hereinafter termed "FETs")
`and modulation doped field-effect transistors that use
`GaAs or InP as the materials, at various sites there
`have been active attempts to form these transistors
`and the matching circuits or biasing circuits
`monolithically on semiconductor substrates. These
`monolithic ICs are known as MMICs (Monolithic
`Microwave Integrated Circuits), and are smaller, with
`higher reliability, than the hybrid microwave
`integrated circuits (MIC: Microwave Integrated
`Circuit) that have been used primarily for
`microwaves in the past. Because of this, there has
`been development in various places of MMICs such
`as a variety of low-pass noise amplifiers, mixers,
`oscillators, and the like that operate in frequencies
`from the UHF band to milliwaves, contributing to
`miniaturization of microwave transceivers, and the
`like.
`In an MMIC, the active elements (FETs, bipolar
`transistors, or the like) and passive elements such as
`microwave lines, capacitors, resistors, and the like,
`are integrated onto a semiconductor substrate. In this
`case, the physical sizes of microwave lines and
`capacitors are large, and thus can be manufactured
`with very little variability using semiconductor
`processing. However, because the active elements
`such as FETs, bipolar transistors, and the like, require
`ultrafine processing, there will inevitably be
`variability in the device characteristics. Specifically,
`in FETs there have been advances in miniaturization
`of the gate electrodes in recent years, with gate
`
`EXHIBIT 1008
`
`1
`
`

`

`Japanese Unexamined Patent Application Publication H4-40702 (2)
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`lengths shortened down to 0.1 µm. However, it is
`difficult to manufacture a 0.1 µm gate electrode with
`good repeatability, so there will be some degree of
`variability. Because the drain current in an FET is
`inversely proportional to the gate length, it is
`necessary to vary the operating voltage of the gate
`depending on the gate length in an operating state
`wherein the gate current is to be a constant. Moreover,
`because the gate length and gate capacitance are
`essentially proportional, the input impedance of the
`FET is controlled by the gate length.
`FIG. 5 is a diagram depicting the frequency
`characteristics (1 through 12 GHz) of the S parameter
`with a gate length of about 0.1 µm and a gate width
`of 250 µm. In this figure, 50 indicates the S11
`component of the S parameter, and 51 indicates the
`S22 component of the S parameter. As indicated by
`the frequency characteristics, the input side S11 of
`the FET can be represented as a resistance
`component Rin and a capacitance component Cin that
`are connected in series, and the output side S22 can
`be represented as a resistance component Rout and a
`capacitance component Cout that are connected in
`parallel. Given this, in this FET Rin is 8 Ω, Cin is
`0.2 pF, Rout is 150 Ω, and Cout is 0.1 pF, where the
`transformer conductance gm is 60 mS. The
`equivalent circuit of the FET described above is
`depicted in FIG. 6.
`FIG. 7 is a circuit diagram depicting a conventional
`example of a 12 GHz-band MMIC amplifier that uses
`the FET described above. This MMIC amplifier
`includes an FET 1 wherein the source is grounded, an
`input terminal 10, an output terminal 11, an input
`matching circuit 16, an output matching circuit 17, a
`gate biasing circuit 18 for applying a bias voltage to
`the gate of the FET 1, and a drain voltage applying
`circuit 19 for applying a drain voltage to the FET 1.
`The input matching circuit 16 described above
`includes an input transmission line 2 that is
`connected between the input terminal 10 and the gate
`of the FET 1, and a capacitance 70 that is connected
`between the input terminal 10 and GND. The
`matching circuit 17 includes an output transmission
`line 3 that is connected between the output terminal
`11 and the drain of the FET 1, and a capacitance 12
`that is connected between the output terminal 11 and
`GND. The gate biasing circuit 18 includes a bias
`terminal 8 for supplying a DC voltage to the gate of
`the FET 1, a capacitance 6 that is connected between
`this terminal 8 and GND, and a choke coil 4 that is
`connected between the bias terminal 8 and the input
`transmission line 2. Additionally, the drain voltage
`applying circuit 19 has a bias terminal 9 for
`supplying a DC voltage to the drain of the FET 1, a
`capacitor 7, and a choke coil 5.
`
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`Note that, in this circuit, if that which is depicted in
`FIG. 5, described above, is used as the FET 1, the
`circuit constants are set as follows.
`Input transmission line 2: Characteristic impedance
`= 50 Ω, electrical length = 67° (where the electrical
`length θ = l/λ · π, where l is the physical length of the
`line and λ is the wavelength within the line).
`Input circuit 70: 1.0 pF
`Output transmission line 3: Characteristic
`impedance = 50 Ω, electrical length = 95°.
`Output side capacitance 12: 0.35 pF
`The 12-gigahertz gain of the MMIC amplifier,
`when the circuit constants are set as described above,
`will be 18.8 dB, and the input/output reflection
`coefficient will be essentially zero.
`However, when there is variability in the gate
`length, as described above, resulting in a distribution
`of input capacitances Cin in the range of 0.18-0.22 pF
`across the wafer, there will be variability in S11 at
`12 GHz. This state of variability is depicted in FIG. 4.
`In FIG. 4, points A, B, and C correspond,
`respectively, to Cin = 0.22, 0.20, and 0.18 pF.
`Moreover, A', B', and C' (the circle marks) indicate
`the respective complex conjugate impedances at the
`points A, B, and C.
`As depicted in FIG. 4, notwithstanding the
`variability in S11, the matching circuit in the MMIC
`is set based on point B, producing a problem in that
`S11 will have an increasingly large match loss the
`further from B.
`The results of calculating the MMIC gains and
`input reflection coefficients for the circuit in FIG. 7
`when Cin of the FET 1 varies to 0.18, 0.20, and
`0.22 pF are given in Table 1. Note that in order to
`simplify the discussion, only Cin is varied, and the
`other equivalent circuit constants are held constant.
`Moreover, the input reflection coefficients are
`reflection coefficients when the FET 1 is viewed
`from the terminal D of FIG. 7.
`
`
`TABLE 1
`0.18 0.20 0.22
`Cin (pF)
`18.8 18.8 17.2
`Gain (dB)
`Input Reflection Coefficient 0.41 0.00 0.36
`
`In this way, there will be variability in the
`microwave characteristics of the MMIC due to the
`variability of the gate length, and thus it is necessary
`to adjust the matching circuit for the MMIC
`depending on the variability of the microwave
`characteristics after MMIC manufacturing. However,
`in order to adjust the matching circuit after
`manufacturing of the MMIC it would be necessary,
`indispensable, that the length and/or width of the
`input transmission line 2 and/or of the output
`transmission line be varied, or that the capacitances
`
`2
`
`

`

`Japanese Unexamined Patent Application Publication H4-40702 (3)
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`12 and 70 be varied. This has been a factor that has
`reduced the performance and yields of MMICs.
`The present invention contemplates the problem set
`forth above, and the object thereof is to provide a
`microwave circuit that can prevent a reduction in
`performance or yield of MMICs despite variability in
`the active element and, in particular, variability of the
`microwave characteristics.
`[MEANS FOR SOLVING THE PROBLEM]
`In order to achieve the object set forth above, the
`microwave circuit according to the present invention
`is a microwave circuit wherein an active element for
`amplifying a microwave input signal and an
`impedance matching circuit for matching an
`input/output impedance of an active element to an
`impedance of a neighboring input/output circuit are
`formed on a substrate, wherein:
`the impedance matching circuit includes:
`an input transmission line for transmitting a
`microwave input signal to the active element;
`an output transmission line for transmitting a
`microwave output signal from the active element;
`a diode, connected in parallel to the active element,
`for correcting a capacitance variance in the active
`element; and
`control voltage supplying means for supplying a
`control voltage to the active element and the diode so
`as to change, inversely in respect to each other, the
`capacitance of the active element and the capacitance
`of the diode.
`[OPERATION]
`Given the present invention, of the structure set
`forth above, because a diode is connected in parallel
`with the active element, when there is a variance in
`the control voltage of the diode, the capacitance of
`the diode and the active element will vary, and the
`current in the active element will vary at the same
`time as well. Because, for the variance in
`capacitances, there is an inverse relationship between
`the increases and decreases for the diode and the
`active element, if the capacitance of the active
`element is smaller than the desired value, then the
`capacitance of the diode is increased through
`increasing the control voltage, and, conversely, if the
`capacitance of the active element is greater than the
`desired value, the capacitance of the diode is
`decreased through adjusting the control voltage to be
`smaller. This makes it possible to carry out self-
`adjusting impedance matching in respect to the
`variability of the capacitances of the active elements.
`[EMBODIMENTS]
`The present invention will be explained in detail
`using the embodiments set forth below.
`FIG. 1 is a circuit diagram depicting one
`embodiment of the present invention. Referencing
`this figure, the points of difference between the
`
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`microwave circuit of this embodiment and the
`microwave circuit of FIG. 7 are that a diode 13, for
`structuring an input matching circuit together with
`the transmission line 2, is connected between the
`input terminal 10 and the capacitance 14 that shorts
`in the microwave band, and a bias terminal 15 that
`applies a control voltage for impedance matching is
`connected to the anode of the diode 13.
`That which has a Schottky barrier between an n-
`type semiconductor and a metal (such as, for example,
`Al and Ti) is used for the diode 13. Here the carrier
`density of the n-type semiconductor is about 3 x
`1017 cm-3, and the Schottky electrode area is about
`1000 µm². The Schottky electrode of the diode 13 is
`connected to the bias terminal 15, and, on the other
`hand, the ohmic electrode is connected to the
`transmission line 2.
`In the bias terminal 15, described above, the Va in
`the present embodiment, wherein a voltage Va that is
`less than the voltage Vgs is applied between the gate
`and the source of the FET 1 (which normally is about
`0 to -1 V in an MESFET), is about -1.5 V.
`Structuring the input matching circuit as described
`above causes the bias voltage Va to be less than the
`gate-source voltage Vgs, so that if Vgs varies the
`capacitance of the diode 13 and the input capacitance
`of the FET will be varied inversely.
`Note that even if using a diode other than a diode
`that uses a Schottky barrier of an n-type
`semiconductor and a metal, the diode is connected so
`that the increases and decreases in the capacitances of
`the active element and the diode will be opposite of
`each other to set the control voltage Va.
`The graph for the voltage and capacitance of the
`diode shown in FIG. 3 will be z referenced to explain
`in greater detail the embodiment described above.
`The reflection coefficient (S11) when the FET is
`viewed from D in FIG. 1 will be point B in FIG. 4, as
`described above, at Rin = 8 Ω and Cin = 0.2 pF. The
`characteristic impedance of the transmission line 2
`for matching with this S11 is a diode capacitance of
`1.0 pF and an electrical length of 67° at 50 Ω. In this
`case, the reflection coefficient wherein the diode side
`is viewed from D will be the point B' in FIG. 4,
`achieving a complex conjugate match. However,
`when there is variability in the gate length of the FET
`1, Cin will be between 0.18 and 0.22 pF, and at this
`time the gate-source voltage Vgs will be, respectively,
`about -0.5 through -0.7 V, so that S11 will vary in the
`range of points A through C of FIG. 4. However, in
`this embodiment the diode 13 is used in the
`impedance matching circuit, and the capacitance of
`the diode 13 will vary, as shown in FIG. 3, depending
`on the variance in Vgs. That is, when Vgs varies from -
`0.5 V to -0.7 V through the variability in the gate
`length of the FET 1, at this time the capacitance of
`
`3
`
`

`

`Japanese Unexamined Patent Application Publication H4-40702 (4)
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`the diode 13 will be about 0.8 through 1.3 pF, as
`shown by curve 31 of FIG. 3. Consequently, the
`reflection coefficient when the diode side is viewed
`from D in FIG. 1, when Vgs is -0.5, -0.6, and -0.7,
`will be the points A1, B1, and C1 (indicated by X
`marks) in FIG. 4. Additionally, the points A', B', and
`C' in FIG. 4 are the reflection coefficients wherein
`the complex conjugate impedances of S11 of the FET
`1 Vgs are -0.5, -0.6, and -0.7.
`In the conventional example depicted in FIG. 7, the
`reflection coefficient when the left side is viewed
`from the node D' will always be the point B, even if
`there is a change in Cin (Vgs) of the FET, where if
`Cin goes to 0.18 pF (Vgs = -0.7 V), the distance
`between the points B' and C' in FIG. 4 will be the
`match loss, and if Cin goes to 0.22 pF (Vgs = -0.5 V),
`the distance between points B' and A' in FIG. 4 will
`be the match loss.
`However, in this embodiment, at Cin = 0.18 pF, the
`distance between points C1 and C' in FIG. 4 will be
`the match loss, and at Cin = 0.22 pF, the distance
`between point A1 and point A' in FIG. 4 will be the
`match loss, and thus the match loss will be less than
`in the conventional example. The specific
`comparison of the above is given in Table 2. Note
`that the input reflection coefficient is that wherein the
`FET side is viewed from the terminal 10 in FIG. 1
`and FIG. 7. Moreover, while the calculations were
`performed holding the values of the parameters of the
`FET, with the exception of Cin, constant, there is no
`large difference for the relative values of the input
`reflection coefficients and the gains between the
`conventional example and the embodiment.
`
`
`TABLE 2 (a)
`
`Cin (pF)
`Gain
`(dB)
`
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`
`
`Conventional
`Example
`Embodiment
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`0.18 0.20 0.22
`18.8 18.8 17.2
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`19.5 18.8 17.8
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`0.18 0.20 0.22
`0.41 0.00 0.36
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`TABLE 2 (b)
`
`
`Conventional
`Example
`
`Cin (pF)
`Input
`Reflection
`Coefficient
`
`
`
`Embodiment
`
`0.14 0.00 0.12
`
`As can be appreciated from the tables above, both
`the gains and the input reflection coefficients in the
`embodiment are better than those of the conventional
`example, and the use of the diode 13 has the effect of
`reducing the match loss. Consequently, appropriately
`choosing the capacitance of the diode 13 of the
`matching circuit causes the diode 13 to absorb the
`variability of the gate capacitance of the FET, acting
`to prevent a negative effect on the gain and the
`
`
`
`reflection coefficient of the MMIC, and also
`improving the MMIC yield.
`FIG. 2 is a circuit diagram depicting another
`embodiment of the present invention. The points of
`difference from the embodiment in FIG. 1, described
`above, are that the lower portion 20 is connected to
`the input transmission line 2, the lower portion 21 is
`connected to the output transmission line 3, and the
`bias circuit of the FET 1 is used also by the lower
`portions 20 and 21. In this embodiment, the diode 13
`is connected in parallel with the FET 1, without
`passing through the input/output transmission paths 2
`and 3. Consequently, when there is a variance in the
`gate operating voltage Vgs, selecting a diode so as to
`correct the variance in the input capacitance of the
`FET 1 eliminates the need to adjust the matching
`circuit because essentially no variance will occur in
`the capacitance at point E in FIG. 2. Additionally,
`because the absolute value of the capacitance change
`of the FET 1 is small, the area of the diode 13 for
`making the correction may also be small.
`Furthermore, unlike in FIG. 1, the capacitance
`changes in the FET 1 and the diode 13 will occur in
`the same phase, making it possible for the diode 13 to
`correct the capacitance of the FET 1 even when a
`large signal is inputted from the input terminal 10.
`This makes it possible to apply the microwave circuit
`of FIG. 2 to supplying electric power of a large
`amplitude.
`Note that while the present invention was
`explained focusing on the input capacitance of the
`FET in FIG. 1 and FIG. 2, above, the present
`invention is not limited thereto, but rather can be
`applied also to FET output capacitance and to bipolar
`transistors, and the like, and the diode is not limited
`to the use of a Schottky junction between an n-type
`semiconductor and a metal, but rather may use a pn
`junction diode, or the like. Additionally, the present
`invention is not limited to MMICs, but may produce
`the same effect even when applied to a hybrid
`integrated circuit.
`[EFFECTS OF THE INVENTION]
`As explained above, the present invention makes it
`possible to correct the variability in capacitances of
`active elements through diodes that are connected in
`parallel to the active elements and control voltages
`that are applied to the diodes and the active elements,
`so there is the effect of improving the performance
`and yields of MMICs. Moreover, even if there is a
`change in the bias point of the active element, the
`match loss is reduced through adjusting the
`capacitance of the diode, producing the effect of
`enabling application not only to small signal
`amplifiers, but to a broad range of microwave circuits
`such as large signal amplifiers and variable
`control/variable gain amplifiers.
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`4
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`

`

`Japanese Unexamined Patent Application Publication H4-40702 (5)
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`4. BRIEF DESCRIPTIONS OF THE DRAWINGS
`FIG. 1 is a circuit diagram of an MMIC amplifier
`depicting one embodiment according to the present
`invention; FIG. 2 is a circuit diagram of an MMIC
`amplifier depicting another embodiment of the
`present invention; FIG. 3 is a diagram depicting the
`voltage-capacitance characteristics of a diode; FIG. 4
`is a diagram depicting the variability of S11 in
`respect to the variability of the input capacitance of
`the FET, and the reflection coefficient of the
`
`FIG. 1
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`matching circuit; FIG. 5 is a diagram depicting the
`frequency characteristics of S11 and S22 of an FET;
`FIG. 6 is an equivalent circuit diagram of an FET;
`and FIG. 7 is a circuit diagram depicting a
`conventional example of an MMIC amplifier.
`In the figures, 1 is an FET, 2 is an input
`transmission line, 3 is an output transmission line, 13
`is a diode, and 15 is a control voltage applying
`terminal.
`
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`FIG. 4
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`FIG. 3
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`[VERTICAL AXIS] Capacitance (pF)
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`FIG. 5
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`[LOWER RIGHT] Increasing frequency
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`FIG. 6
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`[UPPER LEFT] Gate
`[LOWER LEFT] Source
`[UPPER RIGHT] Drain
`[LOWER RIGHT] Source
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`37
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`45
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`5
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`

`

`Japanese Unexamined Patent Application Publication H4-40702 (6)
`
` 1
`2
`FIG. 7
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`47
`48
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`3
`4
`5
`6
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`11
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`PROCEDURAL AMENDMENT
`August 20, 1990
`[STAMPED: Conforming]
`Commissioner of the Patent Office
`1. Case Descriptor
`Patent application H2-148933
`
`
`2. Name of Invention
`Microwave Circuit
`
`
`3. Amended by:
`Relationship to Case: Patent Applicant
`Address: 22-22 Nagaike-cho, Abeno-ku, Osaka
`City, Osaka-fu
`Name: (504) Sharp Corporation
`Representative: TSUJI, Haruo
`
`4. Agent
`Address: Sumitomo Bank Minamimorimachi
`Building, 2-1-29 Minamimorimachi, Kita-ku,
`Osaka City
` Telephone: Osaka (06) 361-2021 (Switchboard)
`Name: Patent Attorney (6474) FUKAMI, Hisao
`
`5. Date of Amendment Order
`Self-initiated
`
`Procedural Inspection (Osugita)
`[Stamped by the Japan Patent Office, August 22,
`1990, Application Filing Section, Haramiya]
`
`6. Items Amended
`Detailed Explanation of the Invention
`
`7. Details of Amendment
`(1) Amend "low-pass noise amplifier" to "low-
`noise amplifier" in line 2 of block 3 of the
`Specification.
`(2) Remove the "z" in line 20 of block 11 of the
`Specification.
`(3) Correct "FIG. 1" to "the… point in FIG. 1" in
`line 2 of block 12 of the Specification.
`
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`6
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`