SiGesedD
`
`SIMULATION
`
`APPLE ET AL. EXHIBIT 1010
`
`R. Jacob Baker Harry W.Li David E. Boyce
`
`Bh
`=F
`ote
`ae
`
`IEEEPress Series on Microelectronic Systems
`Stuart K. Tewksbury, Series Editor
`
`1
`
`APPLE ET AL. EXHIBIT 1010
`
`

`

`Process Information for Hand-Calculations
`
`GNAONNOS
`
`COSTA POS
`
`App. C
`App. C
`App. A
`App. A
`5 ee ee
`.
`sv
`
`VDD (VSS=0) V SV
`
`
`Vv.
`2
`[2eC 50ee
`
`0
`17
`
`iV(006sSm|OG6TeeLSSympSd
`TVae
`
`oy|tm|tm|ms
`oF
`
`~L,
`
`0.14 ym
`
`30um
`
`0:16 um
`
`2
`
`2
`
`Multipliers
`
`kilo
`
`Nor (MEG)
`k
`
`2
`
`

`

`Physical Constants
`
`Name|Symbot|Value/Units|
`es
`[Vacuumdielectric
`fy
`8.85 aF/um
`constant
`
`Silicon dielectric
`constant
`
`SiO, dielectric
`constant
`
`Ey
`
`nx
`
`En;
`
`11.7e,
`
`3.97,
`
`l6e,
`
`
`
`ISIN,dielectric
`constant
`Electronic charge|ql 16x10"C
`
`
`[femperamre==|COCTCLCK
`|Thermal voltage
`Vi,
`kT/g
`
`
`=26mvV @ 300K
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Equations
`
`a=)
`
`NMOSequationsin terms of BSIM1 parameters
`
`for PMOSuse V,,, Vig, Vas, and Vinp
`
`[PHI+ Veg —K2-(PHI+Vsp)
`VEB + PHI+K1-
`Ch—ieeTOxSSCS~—~SSCSCSY
`Cox
`KP
`
`ap
`
`2
`Vps
`
`, (triode)
`
`
`
`Lit)
`
`
`
`dec
`VosS Ves— Venn 6ve~Vruw)Vps — 5 ) (for Long L)
`Z,, (saturation)
`B(V,
`Vin)?
`_
`os — Vraw) (1+Vos—Vossar)] (for Long L)
`Vos 2 Ves— Vow
`{2
`B(Vas—Vraw) = J2Blp or Ip /(Vr - NO)
`=
`
`3
`
`

`

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`4
`
`

`

`CMOS
`Circuit Design, Layout, and Simulation
`
`R. Jacob Baker, Harry W. Li and David E. Boyce
`Department ofElectrical Engineering
`Microelectronics Research Center
`The University of Idaho
`
`IEEEPress Series on Microelectronic Systems
`Stuart K. Tewksbury, Series Editor
`
`IEEE Circuits & Systems Society, Sponsor
`IEEE Solid-State Circuits Society, Sponsor
`
`IEEE
`PRESS
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`5
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`© 1998 by the Institute of Electrical and Electronics Engineers,Inc.
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`without written permission from the publisher.
`
`Printed in the United States of America
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`6
`5
`4
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`
`ISBN 0-7803-3416-7
`IEEE Order Number: PC5689
`
`Library of Congress Cataloging-in-Publication Data
`
`Baker, R. Jacob (date)
`CMOScircuit design, layout, and simulation / R. Jacob Baker,
`Harry W. Li, and David E. Boyce.
`p.
`cm. -- (IEEE Press series on microelectronic systems)
`Includes bibliographical references and index.
`ISBN 0-7803-3416-7
`
`1, Metal oxide semiconductors, Complementary--Design and
`construction,
`2. Integrated circuits--Design and construction.
`3. Metal oxide semiconductorfield-effect transistors,
`I. Li,
`Harry W.
`II. Boyce, David E.
`III. Title.
`IV. Series
`TK7871.99.M44B35
`1997
`621.3815--DC21
`
`97-21906
`
`CIP
`
`6
`
`

`

`
`
`32 Part I CMOS Fundamentals
`
`Layout (top view)
`
`(b)
`
`A
`
`B
`
`Figure 2.9 (a) Figure for the calculation of the resistance of a corner section and
`(b) layout to avoid corners.
`
`2.3.1 The N-well Resistor
`
`At this point, it is appropriate to show the actual cross-sectional view of the n-well after
`all processing steps are completed (Fig. 2.10). The n+ and p+ implants are used to
`increase the threshold voltage of the field devices; more will be said on this later in Ch.
`4, Notice in Appendix A, the Orbit electrical parameters, that the sheet resistanceof the
`n-well is measured with the field implant in place, that is, with the n+ implant between
`the two metal connections in Fig. 2.10. Not shown in Fig. 2.10 is the connection to
`substrate. The field oxide (FOX; also known as ROX or recessed oxide) will be
`discussed in Ch. 4 when wediscuss the active and poly layers.
`
`Metal
`
`Metal p+ field implant
`
`n+ field implant
`
`p-substrate
`
`n+ active implant
`
`Figure 2.10 Cross-sectional view of n-well showing field implant. The
`field implantation is sometimes called the “channel stop implant’.
`
`2.4 The N-well/substrate Diode
`
`it is important to
`in the p-substrate forms a diode. Therefore,
`Placing an n-well
`understand how to model a diode for hand calculations and in SPICE simulations.
`In
`particular,let's discuss diodes using the n-well/substrate pn junction as an example [2].
`The DCcharacteristics of the diode are given by the Shockley diode equation,or
`
`7
`
`

`

`Chapter 2 The Well
`
`a
`
`Ip = Ise a 1)
`
`33
`
`(2.4)
`
`The current J, is the diode current; J, is the scale (saturation) current; V, is the voltage
`across the diode where the anode (p-type material) is assumed positive with respect to
`the cathode (n-type); and V, is the thermal voltage which is given by ea where k =
`Boltzmann's constant (1.3806 x 10°joules per degree kelvin), T is temperature in
`kelvin, n is the emission coefficient (a term that is related to the doping profile and
`affects the exponential behaviorof the diode), and q is the electron charge of 1.6022 x
`10"? coulombs. The scale current and thus the overall diode current are related in
`SPICE byan area factor. The SPICEcircuit simulation program assumesthat the value
`of I, supplied in the model statement was measured for a device with a reference area of
`1. If an area factor of 2 is supplied for a diode, then J, is doubled in Eq.(2.4).
`
`2.4.1 Depletion Layer Capacitance
`
`N-type silicon has a number of mobile electrons, while p-type silicon has a number of
`mobile holes (a vacancy of electrons in the valence band). Formation of a pn junction
`results in a depleted region at the p-n interface (Fig. 2.11). A depletion region is an
`area depleted of mobile holes or electrons. The mobile electrons move across the
`junction, leaving behind fixed donor atoms and thus a positive charge. The movement
`of holes across the junction,
`to the right
`in Fig. 2.11, occurs for
`the p-type
`semiconductor as well with a resulting negative charge. The fixed atoms on each side
`of the junction within the depleted region exert a force on the electrons or holes that
`have crossed the junction. This equalizes the charge distribution in the diode,
`preventing further charges from crossing the diode junction and also gives rise to a
`parasitic (depletion) capacitance.
`
`Anode —_>t— Cathode
`
`
`
`Twoplates of a capacitor
`
`Figure 2.11 Simple illustration of depletion region formation in a pn junction.
`
`The depletion capacitance, C,, of a pn junction is given by
`Cio
`
`Cj =
`
`[- ()}
`
`(2.5)
`
`8
`
`

`

`
`
`34 Part I CMOS Fundamentals
`
`Cj» is the zero-bias capacitance of the pn junction, that is, the capacitance when the
`voltage across the diode is zero. V, is the voltage across the diode, m is the grading
`coefficient (showing how the silicon changes from n- to p-type), and oo is the built-in
`potential given by
`
`$0 = Vr-In[Mate
`
`N.
`
`nj
`
`(2.6)
`
`where N, and WN, are the dopings for the p- and n-type semiconductors, respectively, V,,
`is the thermal equivalent voltage (26 mV @ room temperature), and n, is the intrinsic
`carrier concentration ofsilicon (n, = 14.5 x 10° atoms/cm’).
`
`
`Example 2.3
`Sketch schematically the depletion capacitance of an n-well/p-substrate diode
`100 x 100 um? square given that the substrate doping is 10'S atoms/cm? and the
`well doping is 10'* atoms/cm’. The measured zero-bias depletion capacitance of
`the junction is 100 aF/m’, and the grading coefficient is 0.333. Assume the
`depth of the n-well is 3 um.
`
`Wecan begin this problem bycalculating the built-in potential using Eq. (2.6):
`16
`16
`do = (.026)-In—0--10= a7
`(14.5 x 10°)
`
`The depletion capacitance is made up of a bottom component and a sidewall
`componentas shownin Fig. 2.12.
`
`+Va=
`
`aT
`Bottom capacitance
`
`BK.
`Sidewall capacitance
`p-substrate
`
`Figure 2.12 A pn junction on the bottom andsides of the junction.
`
`The bottom zero-bias depletion capacitance, C,,, is given by
`
`Cy, = (Capacitance per Area) - (Bottom Area, which, for this example,is
`Cjoo = (100 aF/um?)- (100 um)? = 1 pF
`
`The sidewall zero-bias depletion capacitance, C,,,, is given by
`Cjos = (Capacitance per Area) - (Depth of the Well) - (Perimeter of the Well)
`
`or
`
`9
`
`

`

`Chapter 2 The Well
`
`35
`
`Cjos = (100 aF/um?)- (3 um) - (400 um) = 120 fF
`
`The total diode depletion capacitance between the n-well and the p-substrate is
`the parallel combination of the bottom and sidewall capacitances, or
`0p gr ce ee,a
`b-G)P b-@P b-@]
`
`C
`
`Ss
`
`Crp
`
`+
`
`Substituting in the numbers, we get
`Cm 1 pF + 0.120 pF
`~
`(-@)”
`
`A sketch of how this capacitance changes with reverse potential is given in Fig.
`2.13. Notice that when we discuss the depletion capacitance of a diode,it is
`usually with regard to a reverse bias. When the diode becomes forward-biased
`minority carriers, electrons in the p material and holes in the n material, injected
`across the junction, form a stored charge in and around the junction and give
`rise to a storage capacitance. This capacitance is usually much larger than the
`depletion capacitance. Furthermore,
`the time it takes to remove this stored
`charge can be significant. @
`
`Cj, diode depletion capacitance
`
`Cy, zero-bias depletion capacitance
`
`1.12 pF
`
`Vu, diode voltage
`
`Figure 2.13 Sketch of diode depletion capacitance against diode reverse voltage.
`
`2.4.2 Storage Capacitance
`
`Consider the charge distribution of a forward-biased diode shown in Fig. 2.14. When
`the diode becomes forward biased, electrons from the n-type side of the junction are
`attracted to the p-type side (and vice versa for the holes). After an electron drifts across
`the junction, it starts to diffuse toward the metal contact.
`If the electron recombines,
`that is, falls into a hole, before it hits the metal contact, the diode is called a "long base
`diode." The time it takes an electron to diffuse from the junction to the point the
`electron recombines is called the carrier lifetime. For silicon this lifetime is on the
`order of 10 ps. If the distance between the junction and the metal contact is short, such
`that the electrons make it to the metal contact before recombining, the diode is said to
`be a "short base diode."
`In either case, the time between crossing the junction and
`
`10
`
`10
`
`

`

`
`
`36 Part I CMOS Fundamentals
`
`Metal contact
`
`Storage capacitance
`
`Minority carriers
`
`Figure 2.14 Charge distribution in a forward-biased diode.
`
`time, tr. A capacitance is formed between the
`recombining is called the transit
`electrons diffusing into the p-side and the holes diffusing into the n-side, that is, formed
`between the minority carriers.
`(Electrons are the minority carriers in the p-type
`semiconductor.) This capacitance is often called a diffusion capacitance or storage
`capacitance (due to the presence of the stored minority carriers around the junction).
`
`Wecan characterize the storage capacitance, C,, in terms of the minority carrier
`lifetime. Under DC operating conditions, the storage capacitance is given by
`Cs= Jp... tr
`nvr
`
`(2.7)
`
`I, is the DC current flowing through the forward-biased junction given by Eq. (2.4).
`Looking at the diode capacitance in this way is very useful for analog AC small-signal
`analysis. However, for digital applications we are more interested in the large-signal
`switching behavior of the diode. It should be pointed outthat in general, for a CMOS
`process,
`it
`is undesirable to have a forward-biased pn junction.
`If we do have a
`forward-biased junction, it usually means there is a problem, for example, electrostatic
`protection, capacitive feedthrough possibly causing latch-up, and so on. These topics
`are discussed in more detaillater in this chapter.
`
`In the following diode switching analysis, we will assume
`Consider Fig. 2.15.
`that V, >> 0.7, V, < 0 and that the voltage source has been at V,. long enoughto reach
`steady-state condition; that is, the minority carriers have diffused out to an equilibrium
`condition. At the time f, the input voltage source makes an abrupttransition from V,, to
`V,, causing the current to change from = to “e, The diode voltage remains at 0.7 V
`since the diode contains a stored charge that must be removed . Attime ¢, the stored
`charge is removed. At this point, the diode basically looks like a voltage-dependent
`capacitor that follows Eq. (2.5).
`In other words for ¢ > t,
`the diode depletion
`capacitance is charged through R until the current in the circuit goes to zero and the
`voltage across the diode is V,. This accounts for the exponential decay of the current
`and voltage shownin Fig. 2.15.
`
`11
`
`11
`
`

`

`Chapter 2 The Well
`
`37
`
`PC)
`
`7
`
`Diode current
`
`Diode voltage
`
`
`
`time
`
`Figure 2.15 Diodetestcircuit.
`
`The diode storage time, the time it takes to remove the stored charge, t, ,
`simply the difference in f, and t,, or
`
`is
`
`t,=t,-t,
`
`(2.8)
`
`This time is also given by
`
`
`(2.9)
`ts=tr-In ER
`—iR
`de
`ep
`oe ;
`‘
`Vets
`Ves
`where — =ir and — =ir = a negative numberin this discussion. Notethat it is quite
`easy to determine the minority carrier lifetime using this test setup.
`
`Defining a time t,, where t¢, > t,, when the current in the diode becomes 10
`percent of =, we can define the diode reverse recovery time, or
`i =i
`
`(2.10)
`
`2.4.3 SPICE Modeling
`
`The SPICE (simulation program with IC emphasis) diode model parameters are listed
`in Table 2.1. The series resistance, R,, deserves some additional comment. This
`resistance results from the finite resistance of the semiconductor used in making the
`diode and the contact resistance, the resistance resulting from a metal contact to the
`semiconductor. At
`this point, we are only concerned with the resistance of the
`semiconductor.
`For a reverse-biased diode,
`the depletion layer width changes,
`increasing for larger reverse voltages (decreasing both the capacitance and series
`resistance, of the diode). However, when we modelthe series resistance, we use a
`constant value. In other words, SPICE will not show usthe effects of a varying R,.
`
`Example 2.4
`Using SPICE, explain what happens when a diode with a carrier lifetime of 30
`ns is taken from the forward-biased region to the reverse-biased region. Use the
`circuit shown in Fig. Ex2.4 to illustrate your understanding.
`
`We will assumea zero-bias depletion capacitance of 1 pF. The SPICE netlist for
`this circuit is shown below.
`
`12
`
`12
`
`

`

`
`
`Chapter
`
`The MOSFET
`
`At this point we should have some appreciation for the parasitics, that is, capacitances
`and resistances, associated with a CMOS process.
`In this chapter we discuss the
`MOSFEToperation. To beginlet's define the symbols used to denote the n-channel and
`p-channel MOSFETs(see Fig. 5.1). When the substrate is connected to VSS and the
`well is tied to VDD, wewill use the simplified models shownat the bottom ofthe figure.
`It is important to keep in mind that the MOSFETis a four-termina! device and that the
`source and drain of the MOSFETare interchangeable.
`
`Gate
`
`Drain
`bib
`
`+ |
`Vas _
`Source
`
`Drain
`
`Ip
`
`Gate
`
`+
`Vig
`Ss _
`Source
`
`n-channel
`
`Substrate (bulk)
`
`Symbol used
`when substrateis
`tied toVss
`
`Vse
`— |
`Gate
`
`Vse r
`=
`Gate
`
`Well (bulk)
`
`Source
`
`y Ip
`Drain
`
`Source
`
`Symbol used
`when wellis
`J tied toVDD
`Is
`Drain
`
`p-channel
`
`Figure 5.1 Symbols used for n- and p-channel MOSFETs.
`
`13
`
`13
`
`

`

`
`
`84 Part I CMOS Fundamentals
`
`5.1 The MOSFET Capacitances
`
`Consider the MOSFET shown in Fig. 5.2 and its associated cross-sectional view.
`Associated with the drain and source regions to the substrate is a depletion capacitance
`that was discussed in the previous chapter.
`In this section we will concentrate on the
`capacitances associated with the gate electrode, that is, the capacitance from the gate to
`groundin Fig. 5.2.
`
`Vas
`
`o-substrate
`
`||
`LD
`
`Figure 5.2 Cross-sectional view of MOSFET used to calculate capacitances.
`
`5.1.1 Case I: Accumulation
`
`Let's first consider the case when V,., < 0 (Fig. 5.3). Under this condition, mobile holes
`from the substrate are attracted under the gate oxide. The thickness of the oxide in the
`SPICE MOSFET modelis given by the parameter TOX. The capacitance between the
`gate electrode and the substrate electrode is given by
`Leta
`(L-2:-LD)-W
`TOX
`
`(5.1)
`
`fox:
`
`Coz
`
`where €,x(= 3.97 - 8.85 aF/um) is the dielectric constant of the gate oxide, W is the
`drawn width (neglecting oxide encroachment), and L—2- LD is the effective channel
`length. The capacitance between the gate and drain or source is given by
`
`_ €o,-LD-W
`Cga.5 = Tox = Gate-drain (or source) overlap capacitance
`
`(5.2)
`
`neglecting oxide encroachment. The gate-drain overlap capacitance is present in a
`MOSFETregardless of the biasing conditions. This capacitance is specified in SPICE
`MOSFET models by the variables CGDO and CGSO with units of farads/meter.
`Estimation of C,,, or C,, using the measured BSIM model parametersuses
`
`14
`
`14
`
`

`

`Chapter 5 The MOSFET
`
`and
`
`Eox Hi LD
`Cea = CGDO-W= TOX
`
`Cys = CGSO-W
`
`(farads)
`
`85
`
`(5,3)
`
`(5.4)
`
`The total capacitance, independent of the width and length of the MOSFET, between
`the gate and groundin thecircuit of Fig. 5.2 is the sum of C,,, C,,, and C,, and is given
`by
`
`(5.5)
`(farads/meter’)
`Ch.= =
`is called the oxide capacitance, which for
`the CN20 process is
`The term C/,
`approximately 800 aF/um’. Knowing the width and length of a MOSFETgivesa total
`capacitance from the gate of the MOSFETin Fig. 5.2 to ground of
`
`
`
`Co = Cl. WL
`
`(farads)
`
`(5.6)
`
`There is a significant resistance in series with C,, in Fig. 5.3 from the resistivity of the
`p-substrate. The resistivity of the n+ source and drain regions tends to be small enough
`to neglect in most circuit design applications.
`
`Ves <0
`
`
`
`
`
`Gate
`
`Overlap capacitances
`P
`cap
`
`:
`Drain
`
`connection
`
`Gate to substrate (bulk)
`capacitance
`Figure 5.3 MOSFETin accumulation.
`
`p-sub
`
`5.1.2 Case Il: Depletion
`
`Referring again to Fig. 5.2, let's consider the case when V,,, is not negative enough to
`attract a large numberof holes under the oxide and not positive enoughto attract a Jarge
`numberof electrons. Under these conditions, the surface under the gate is said to be
`depleted. Consider Fig. 5.4. As V,, is increased from some negative voltage, holes will
`be displaced under the gate, leaving immobile acceptor ions that contribute a negative
`charge. Wesee that as we increase V, a capacitance between the gate and the induced
`channel under the oxide exists. Also, a depletion capacitance between the induced
`channel and the substrate is formed. The capacitance between the gate and the
`
`15
`
`15
`
`

`

`
`
`86 Part | CMOS Fundamentals
`
`source/drain is simply the overlap capacitance, while the capacitance between the gate
`and the substrate is the oxide capacitance in series with the depletion capacitance. The
`depletion layer shown in Fig. 5.4 is formed between the substrate and the induced
`channel. The MOSFET operated in this region is said to be in weak inversion or the
`subthreshold region because the surface under the oxide is not heavily n+.
`
`Gate Attracted electrons, Q pyain
`
`
`
`es i
`Tk Ea
`\
`Depletion layer
`
`thickness, Xd
`
`p-sub
`
`Depletion layer
`
`Depletion capacitance
`in series with oxide C
`
`Figure 5.4 MOSFETin depeletion.
`
`5.1.3 Case Ill: Strong Inversion
`
`WhenV,., is sufficiently large (> V,,,,, the threshold voltage of the n-channel MOSFET)
`so that a large numberofelectrons are attracted under the gate, the surface is said to be
`inverted, that is, no longer p-type. Figure 5.5 shows how the capacitance from the gate
`to ground changes as V,, changes for the MOSFETconfiguration of Fig. 5.2. This
`figure can be misleading. Remember that when the MOSFETis in the accumulation
`region the majority of the capacitance to ground, C,, , runs through the large parasitic
`
`Accumulation
`
`
`
`
`
` f
`Cox
`
`
`
`.
`Inversion
`
`Good cap area
`
`Vas, V
`
`Depletion Bad cap area
`
`
`
`Figure 5.5 Capacitance to ground at the gate terminal of the circuit shown in Fig. 5.2
`plotted against the gate-source voltage.
`
`16
`
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`Chapter 5 The MOSFET
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`resistance of the substrate. Also note that the MOSFET makes a very good capacitor
`when V,.> Vay, + a few hundred mV. Wewill make a capacitor in this fashion many
`times while we are designing circuits.
`
`Example 5.1
`If
`Suppose the following MOSFET configuration is to be used as a capacitor.
`the width and length of the MOSFETare both 100 um, estimate the capacitance.
`Are there any restrictions on the voltages we can use across the capacitor?
`
`geex
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`Gate}-— Source/drain
`—_-—
`
`WL = 100/100
`
`Since the MOSFETis to be used as a capacitor, we require operation in the
`strong inversion region, with the gate potential always at V,,,, + 100 mV above
`the source/drain potentials.
`The capacitance between the gate and the
`source/drain is then Cio = C4, -W-L. For the CN20 processthis results in
`
`Ctot = (800 aF/um?)(100 m)(100 um) = 8 pF
`
`Note that we did not concern ourselves with the substrate connection. Since we
`are assuming strong inversion, the bulk (substrate) connection will only affect
`the capacitances from the drain/source to substrate (those from the source/drain
`implant regions). We will see, however, that the connection of the substrate will
`significantly affect the threshold voltage of the devices. ™
`
`5.1.4 Summary
`
`is
`Figure 5.6 shows our MOSFET symbol with capacitances. The capacitance C,,
`associated with the gate poly overthe field region. The gate-drain capacitance, C,, and
`the gate-source capacitance C,, are determined by the region of operation (see Table
`5.1:
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`
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`
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`
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`Table 5.1 MOSFETcapacitances.
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`Chapter
`2/
`
`Dynamic Analog Circuits
`
`in reducing power
`Chapter 14 discussed dynamic digital circuits, which are useful
`dissipation and the number of MOSFETs used to perform a given circuit operation.
`Dynamic analogcircuits exploit the fact that information can be stored on a capacitor or
`gate capacitance of a MOSFETfor a period of time.
`In this chapter, we will discuss
`analog circuits such as sample and holds, current mirrors, amplifiers, and filters using
`dynamic techniques.
`
`27.1 The MOSFET Switch
`
`A fundamental component of any dynamiccircuit (analog or digital) is the switch (Fig.
`27.1). An importantattribute of the switch, in CMOSis that under DC conditions the
`gate of the MOSFETdoes not draw a current. Therefore, neglecting capacitances from
`the gate to the drain/source, we find that the gate control signal does not interfere with
`information being passed through the switch. Figure 27.2 shows the small-signal
`resistance of the switches of Fig. 27.1 plotted against drain-source voltage. The benefits
`of using the CMOStransmission gate are seen from this figure, namely, lower overall
`resistance. Another benefit of using the CMOSTG isthat it can pass a logic high or a
`
`i
`—{
`
`=
`
`3
`ae
`em
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`i S
`
`witch
`
`Figure 27.1 MOSFETsused as switches.
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`6
`L
`rT
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`
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`720 Part IV Mixed-Signal Circuits
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` Vos
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`1
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`2
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`3
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`4
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`5
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`Figure 27.2 Small-signal on-resistance of MOSFETswitches [1].
`
`logic low without a threshold voltage drop. The largest voltage an n-channel switch can
`pass is VDD — V,,,,, while the lowest voltage a p-channel switch can passis Vyyp.
`
`While MOSswitches may offer substantial benefits, they are not without some
`detraction. Two nonideal effects typically associated with these switches may ultimately
`limit the use of MOS switches in some applications (particularly sampled-data circuits
`such as data converters). These two effects are known as charge injection and clock
`feedthrough.
`
`Charge Injection
`
`Charge injection can be understood with the help of Fig. 27.3. When the MOSFET
`switch is on and V,,
`is small, the charge under the gate oxide resulting from the
`inverted channel is (from Ch. 5) Q',. When the MOSFETturns off, this charge is
`injected onto the capacitor and into v,. Since v,, is assumed to be a low-impedance,
`source-driven node,
`the injected charge has no effect on this node. However, the
`charge injected onto C,,,, results in a change in voltage acrossit.
`
`
`
`
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`Vin tL Ctoad—Vioad
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`Charge injection
`
`Figure 27.3 Simple configuration using an NMOSswitch to show charge injection.
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