`
`Machine Translation of JPH1174367A
`
`【0001】BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates
`to semiconductor devices and amplifiers for high frequency amplification.
`
`【0002】2. Description of the Related Art In general, high-frequency wideband amplifiers such as
`CATV (cable television) amplifiers and high-speed sensor amplifiers, and high-frequency high-output
`amplifiers such as communication and measuring instruments use field effect transistors (hereinafter
`referred to as FETs) as amplifying elements. There are many things.
`
`【0003】 In general, FETs of this type include MOSFETs with MOS (Metal-oxide-semiconductor)
`structure, JFETs with pn junctions, and MESs with metal-semiconductor contact Schottky barriers
`(barriers), depending on the gate structure. metal-semiconductor ) FETs. Furthermore, they can be
`classified into n-type and p-type according to the channel (current path) structure.
`
`【0004】 FIG. 6 is a vertical cross-sectional view of a conventional n-channel planar J (junction type)
`FET1. This FET 1 has an n-channel 3 made of, for example, an n-type semiconductor formed at the upper
`end in the drawing of a substrate 2 made of, for example, a p-type semiconductor. In addition, on the
`upper surface of the n-channel 3, a gate 4 (G) as an electrode and a source 5 (S) and a drain 6 (D) on both
`sides thereof are respectively fixed to form a planar shape. A p-type portion 7 made of a p-type
`semiconductor is formed in contact with the lower surface of the gate 4 in part of the n-channel 3 in the
`lower portion of the drawing.
`
`【0005】 FIG. 7 is a vertical cross-sectional view of a conventional n-channel MESFET 8. FIG. This
`FET 8 forms an n-channel 10 made of, for example, an n-type semiconductor on one surface of an
`electrically insulating substrate 9 (I), for example, and an electrode gate (G) 11 is formed on the upper
`surface of this n-channel 10 in the figure. , and the source (S) 12 and the drain 13 (D) on both sides
`thereof are adhered to each other.
`
`【0006】 As other FETs, the n-channels 3 and 10 of these FETs 1 and 8 are replaced with p-channels
`made of a p-type semiconductor, while the p-type part 7 is replaced with an n-type part made of an n-type
`semiconductor, p Some are configured as channel-type FETs.
`
`【0007】 FIG. 8 is a partial longitudinal sectional view of a conventional n-channel depletion type
`MOSFET 14. FIG. This FET 14 has a p-channel 16 made of, for example, a P-type semiconductor (which
`may be an n-type semiconductor) at the upper end in the drawing of a substrate 15 made of, for example,
`an n-type semiconductor (or a P-type semiconductor), and the top surface of which is the substrate 15. It
`is formed so as to be almost flush with the upper surface of the
`
`【0008】 On the upper surface of this p-channel 16, an electrode gate 18 (G) is arranged via an insulating
`oxide film 17, and on both sides of this gate 18, electrodes of a source 19 (S) and a drain 20 (D) are
`provided. and are attached respectively. Therefore, an equivalent MOS (Metal-Oxide-Semiconductor)
`diode is formed between the gate 18 and the p-channel 16 with the insulating oxide film 17 interposed
`therebetween.
`
`【0009】FIG. 9 is an equivalent circuit diagram of the FETs 1 and 8 when the sources are grounded, and
`an equivalent diode D1 is formed at the junction between the gate G and the drain D. As shown in FIG.
`
`APPLE 1025
`Apple v. Arigna
`IPR2022-00651
`
`1
`
`

`

`This equivalent diode D1 corresponds to a PN junction diode in JFET1, and corresponds to a Schottky
`barrier diode in MESFET8.
`
`【0010】 Since the equivalent diode D1 is biased in the opposite direction of the pn junction during
`source-grounded operation, a junction capacitance CJ is generated between the cathode and anode of the
`equivalent diode D1. , it changes according to the following formula (1).
`
`【0011】[Number 1]
`
`【0012】[Outside 1]
`
`【0013】 Moreover, since this junction capacitance CJ acts as a feedback capacitance from the drain D to
`the gate G, the signal feedback capacitance will eventually change. As a result, primarily second order
`asymmetric waveform distortion occurs in the drain output signal.
`
`【0014】 Also, since this waveform distortion is caused by the junction capacitance CJ of the equivalent
`diode D1, the larger the amplitude of the input signal, the higher the signal frequency, or the smaller the
`gain, the greater the ratio to the signal.
`
`【0015】 FIG. 10 is an equivalent circuit diagram of the depletion type MOSFET 14 shown in FIG. 8
`described above during source-grounded operation. The applied voltage to the formed equivalent MOS
`diode changes.
`
`【0016】 For this reason, the amount of signal feedback changes due to the nonlinearity of the equivalent
`capacitance of this equivalent MOS diode, so that the output signal output to the drain 20 mainly
`produces secondary asymmetric amplitude distortion.
`
`【0017】 That is, when the MOSFET 14 is source-grounded, the equivalent capacitance C of the
`equivalent MOS diode between the gate 18 and the p-channel 16 changes with respect to the voltage
`applied to the MOS diode according to the following formula (2).
`
`【0018】[Number 2]
`
`【0019】 Here, C1 and C2 are the equivalent capacitances of the insulator layer (oxide film) and
`semiconductor layer, respectively. The latter originates from the creation of a depletion layer. V is the
`potential difference between the gate 18 and the drain 20, which is V<0 in the case of n-channel and V>0
`in the case of p-channel.
`
`【0020】 Also, C2(|V|) can be approximately approximated by the following equation (3).
`
`【0021】[Number 3]
`
`【0022】[outside 2]
`
`【0023】 SUMMARY OF THE INVENTION Accordingly, the present invention has been made in
`consideration of such circumstances, and an object thereof is to provide a semiconductor device and an
`amplifier capable of reducing waveform distortion of an output signal, particularly secondary asymmetric
`waveform distortion.
`
`【0024】A semiconductor device according to claim 1 of the present invention comprises a field effect
`transistor having a gate, a source and a drain; and waveform distortion reducing means having a diode
`
`2
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`

`that is reverse biased. Here, the waveform distortion reducing means may be formed on one chip with the
`field effect transistor, or may be formed separately.
`
`【0025】 According to the present invention, when the field-effect transistor operates with its source
`grounded, the equivalent diode between the gate and the drain and the reverse-polarity diode are each
`reverse-biased. These junction capacitances act as feedback capacitances from the drain to the gate.
`
`【0026】 However, since the polarities of these two diodes are opposite to each other, the directions of
`capacitance change of these two diodes are also opposite and cancel each other out. Therefore, even if a
`signal is input to the gate, the change in the total feedback capacitance between the gate and the drain can
`be reduced, so that the waveform distortion of the output signal due to the change in the feedback
`capacitance can be reduced. Therefore, a diode with similar C-V (capacitance-voltage) characteristics of
`an equivalent diode should be used as the reverse-polarity diode, and reverse-biased so that the applied
`voltage of this reverse-polarity diode is approximately equal to the potential difference between the gate
`and the drain. Thus, it is possible to further reduce the second-order symmetrical waveform distortion of
`the output signal and improve the second-order symmetry of the output signal.
`
`【0027】 In the semiconductor device of the invention recited in claim 2, the waveform distortion
`reducing means comprises a series circuit of a reverse polarity diode and a capacitor connected in parallel
`to an equivalent transistor between the gate and the drain of the field effect transistor; and a DC power
`supply connected to a connection part with a resistor or an inductor via a resistor or an inductor.
`
`【0028】 According to the present invention, a reverse bias can be applied to a diode of opposite polarity
`by a DC power supply via a resistor or an inductor so that the applied voltage is approximately equal to
`the potential difference of an equivalent diode between the gate and the drain. Therefore, by the same
`action as the invention of claim 3, it is possible to reduce the change in the feedback capacitance between
`the gate and the drain, thereby reducing the waveform distortion of the output signal, especially the
`second-order asymmetric waveform distortion.
`
`【0029】 A semiconductor device according to claim 3 of the invention comprises: a depletion type
`MOS field effect transistor having a gate, a source and a drain; and waveform distortion reducing means
`having a MOS diode that produces an equivalent capacitance that is reverse-biased to . Here, the
`waveform distortion reducing means may be formed on one chip with the field effect transistor, or may be
`formed separately.
`
`【0030】 According to the present invention, when the depletion type MOS field effect transistor
`operates with its source grounded, a MOS diode is provided between the gate and the drain that generates
`an equivalent capacitance opposite in polarity to the equivalent capacitance of the equivalent MOS diode
`between the two. These equivalent capacitances act as feedback capacitances from the drain to the gate.
`
`【0031】However, since the polarities of these two equivalent capacitances are opposite to each other,
`the directions of change of these two capacitances are also opposite and cancel each other out. Therefore,
`even if a signal is input to the gate, the change in the total feedback capacitance between the gate and the
`drain can be reduced, so that the waveform distortion of the output signal due to the change in the
`feedback capacitance can be reduced. Therefore, the MOS diode is formed to have a C-V (capacitance-
`voltage) characteristic similar to that of an equivalent MOS diode between the gate and the drain, and is
`reversed so that the voltage applied to this MOS diode is approximately equal to the potential difference
`between the gate and the drain. Biasing can further reduce second-order symmetric waveform distortion
`of the output signal and improve the second-order symmetry of the output signal.
`
`3
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`【0032】 In the semiconductor device of the invention according to claim 4, the waveform distortion
`reducing means comprises a series circuit of a capacitor and a MOS diode interposed between the gate
`and the drain of the depletion type MOS field effect transistor; and a DC power supply connected to the
`connecting portion of the through a resistor or an inductor.
`
`【0033】 According to the present invention, a reverse bias can be applied to a MOS diode by a DC
`power supply via a resistor or an inductor so that the applied voltage is approximately equal to the
`potential difference of an equivalent MOS diode between the gate and the drain. Therefore, by the same
`action as the invention of claim 3, it is possible to reduce the change in the feedback capacitance between
`the gate and the drain, thereby reducing the waveform distortion of the output signal, especially the
`second-order asymmetric waveform distortion.
`
`【0034】 The semiconductor device according to the invention of claim 5 is characterized in that the
`waveform distortion reducing means is formed integrally with the substrate of the field effect transistor.
`
`【0035】 According to the present invention, the waveform distortion reducing means including the
`MOS diode is formed integrally with the substrate of the field effect transistor such as a depletion type
`MOSFET to form one chip. physical specifications such as C-V (capacitance-voltage) characteristics can
`be formed almost the same as those of the equivalent MOS diode. For this reason, the changes in the two
`opposite capacitances of the MOS diode and the equivalent MOS diode can be made more equal, so that
`the change in the feedback capacitance between the gate and the drain can be further reduced to further
`reduce the secondary asymmetric distortion of the output signal. can be done.
`
`【0036】 An amplifier according to the invention recited in claim 6 comprises the semiconductor device
`recited in any one of claims 1 to 5; and a feedback circuit inserted between the gate and drain of a field
`effect transistor. do.
`
`【0037】 According to the present invention, waveform distortion such as secondary asymmetric
`waveform distortion of the output signal can be reduced by reducing change in feedback capacitance
`between the drain on the output side and the gate on the input side. Since the semiconductor device
`according to claim 1 is used as an amplifying element, it is possible to reduce a change in capacitance of
`the feedback circuit when an input signal is superimposed on the gate, thereby reducing waveform
`distortion such as secondary asymmetric waveform distortion.
`
`【0038】BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present
`invention will now be described with reference to FIGS. 1 to 5. FIG. 1 to 5, the same reference numerals
`are given to the same or corresponding parts.
`
`【0039】 FIG. 1 is an equivalent circuit diagram of a semiconductor device according to a first
`embodiment of the present invention, and this semiconductor device has a source-grounded FET (Field
`Effect Transistor) 21. As shown in FIG. The FET 21 has a gate 22 (G) to which an input signal is input, a
`drain 23 (D) to which an output signal is output, and a grounded source 24 (S). A waveform distortion
`reduction circuit 25 is inserted between them.
`
`【0040】 This waveform distortion reduction circuit 25 has a diode 27 (DO) and a capacitor having
`similar C-V (capacitance-voltage) characteristics and opposite polarity to an equivalent diode 26 (D1)
`formed between the gate 22 and the drain 23. 28 (CO) is connected in parallel with this equivalent diode
`26 .
`
`4
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`【0041】 A DC power supply 30 (VB) is connected via a resistor 29 to the common connection portion
`of the reverse polarity diode 27 and capacitor 28 . This DC power supply 30 connects the reverse polarity
`diode 27 via a resistor 29 to its pn junction so that the voltage applied across the reverse polarity diode 27
`is approximately equal to the potential difference between the gate 22 and the drain 23 . bias, that is,
`reverse bias.
`
`【0042】 In FIG. 1, D2 represents an equivalent diode between the drain 22 and the source 24, L, C, and
`R represent inductance, capacitance, and resistance, respectively. Gate 22, source 24 are shown.
`Therefore, for example, Ld, Rg, and Ls represent the equivalent inductance of the drain 23, the equivalent
`resistance of the gate 22, and the equivalent inductance of the source 24, respectively, and Ids the current
`flowing between the drain 23 (D) and the source 24 (S). there is
`
`【0043】 FIG. 2 is a vertical cross-sectional view of a main part of a semiconductor device according to
`a second embodiment of the invention. This semiconductor device is characterized in that the FET 21 is
`configured as a source-grounded n-channel planar J (junction type) FET 21A. In this JFET 21A, an n-
`channel 32 made of an n-type semiconductor is formed flush with the upper end in the figure of a p-type
`substrate 31 made of a p-type semiconductor. The p-type portion 33 is formed flush.
`
`【0044】 The electrodes of the gate 22 are formed on the upper surface of the p-type portion 33 by metal
`deposition or the like, and the electrodes of the drain 23 and the source 24 are formed on the upper
`surface of the n-channel 32 on both the left and right sides of the gate 22 in the figure. It is formed by
`vapor deposition or the like.
`
`【0045】 At the upper end of the p-type substrate 31, beside the n-channel 32, a waveform distortion
`reduction circuit 25 having the reverse polarity diode 27, capacitor 28, and resistor 29 is arranged.
`
`【0046】 The diode 27 of the waveform distortion reduction circuit 25 has an n-type portion 34 made of
`an n-type semiconductor disposed near the n-channel 32 at a predetermined distance, and the upper end of
`the n-type portion 34 is made of a p-type semiconductor. The p-type portion 35 is formed flush. An anode
`36 electrode is formed on the upper surface of the p-type portion 35 by metal vapor deposition or the like,
`while a cathode 37 electrode is formed on the upper surface of the n-type portion 34 by metal vapor
`deposition or the like to form a diode 27. ing. Furthermore, the anode 36 of this diode 27 is electrically
`connected to the drain 23 by a conductor pattern or the like formed on the upper surface of the p-type
`substrate 31 .
`
`【0047】 On the side of this diode 27, on the upper surface of the p-type substrate 31, a second dielectric
`layer 39 and a resistor layer 40 are laminated and arranged side by side with a first dielectric layer 38
`interposed therebetween. It is Furthermore, one electrode 41 of a pair of capacitor electrodes is formed on
`the upper surface of the second dielectric layer 39, while the other electrode 42 is formed on the upper
`surface of the left end portion of the resistor layer 40 in the drawing. are respectively formed to form a
`capacitor 28. One electrode 41 is electrically connected to the gate 22 by a conductor pattern or the like,
`and the other electrode 42 is connected to the cathode electrode 37 of the diode 27 .
`
`【0048】 An electrode 43 is formed on the upper surface of the right end portion of the resistor layer 40
`in the figure to constitute the resistor 29, and the electrode 43 is connected to the DC power supply 30
`(VB).
`
`【0049】[outside 3]
`
`5
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`

`【0050】 However, the diode 27 is reverse biased by an external power supply 30 (VB) so that the
`voltage applied across the reverse polarity diode 27 is approximately equal to the potential difference V
`between the gate 22 and the drain 23, and the C-V Since the characteristics are similar to those of
`equivalent diode 26, the total feedback capacitance CF(V) between gate 22 and drain 23 is expressed by
`the following equation (4).
`
`【0051】[Number 4]
`
`【0052】 Then, when a signal is input to the gate 22 and the potential difference V between the gate 22
`and the drain 23 changes by ΔV, the total feedback capacitance CF(V+ΔV) is expressed by the following
`equation (5).
`
`【0053】[Number 5]
`
`【0054】 Therefore, the total feedback capacitance CF itself between the gate and the drain is
`approximately doubled, but since the direction of the capacitance change of the reverse polarity diode 27
`is almost symmetrically opposite to the direction of the capacitance change of the equivalent diode 26, the
`gate Even if a signal is input to 22, change in feedback capacitance can be reduced.
`
`【0055】 Therefore, it is possible to reduce the waveform distortion of the output signal, particularly the
`second-order asymmetric waveform distortion, caused by the change in the feedback capacitance.
`
`【0056】 Also, by arranging the reverse polarity diode 27 near the n-channel 32, waveform distortion
`can be reduced over a wide range of input power, frequency range and temperature range.
`
`【0057】 FIG. 3 is a vertical cross-sectional view of the essential parts of a third embodiment in which
`the FET 21 shown in FIG. 1 is configured as an n-channel MESFET 21B. This MESFET 21B replaces the
`P-type substrate 31 of the JFET 21A with an insulating substrate (I), while omitting the P-type portion 33
`in the n-channel 32 to form an MES-type structure. is characterized in that the equivalent diode 26 is
`formed as a Schottky barrier diode.
`
`【0058】Therefore, this MESFET 21B can also reduce the waveform distortion of the output signal,
`particularly the second-order asymmetric waveform distortion in the high-frequency, wide-band and high-
`output range.
`
`【0059】 FIG. 4 is a vertical cross-sectional view of a main part of a semiconductor device according to
`a fourth embodiment of the present invention, and FIG. 5 is an equivalent circuit diagram of the
`semiconductor device during source-grounded operation. It is characterized in that the reduction circuit 47
`is integrally formed on one chip.
`
`【0060】 This depletion-type MOSFET 21C has a p-channel 45 made of a p-type semiconductor at the
`upper end of the n-type substrate 44 made of an n-type semiconductor in the figure, and the upper surface
`of the p-channel 45 is almost flush with the upper surface of the n-type substrate 44 in the figure. It is
`formed as
`
`【0061】 An insulating oxide film 46a having a required size is formed on the upper surface of the p-
`channel 45, and an electrode for the gate 22(G) is formed on the upper surface of the insulating oxide film
`46a by metal vapor deposition or the like.
`
`6
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`

`

`【0062】 On both sides of the gate 22, the electrodes of the source 24(S) and the drain 23(D) are closely
`attached to the upper surface of the p-channel 45 and arranged by metal vapor deposition or the like.
`Therefore, an equivalent MOS (Metal-Oxide-Semiconductor) diode 22a is formed between the electrode
`of the gate 22 and the p-channel 45 with an insulating oxide film 46a interposed therebetween.
`
`【0063】 A waveform distortion reduction circuit 47 is arranged on the upper end of the n-type substrate
`44 near the MOS type FET 21C and is integrally formed on one chip. The waveform distortion reduction
`circuit 47 has a second MOS diode 48 arranged at the upper end of the n-type substrate 44 in the vicinity
`of the MOS-type FET 21C.
`
`【0064】 The second MOS diode 48 has a second p-type portion 49 made of a p-type semiconductor on
`the substrate 44 on the side near the MOSFET 21 so that the upper surface of the second MOS diode 48 is
`substantially flush with the upper surface of the substrate 44. is formed in A first electrode 50 is formed
`directly on the upper surface of the second p-type portion 49 by metal vapor deposition or the like, while
`a second electrode 51 is formed by metal vapor deposition or the like via an insulating oxide film 46b of a
`required size. is doing.
`
`【0065】 As a result, the second MOS diode 48 is formed of the three layers of the second electrode 51
`(Metal), the insulating oxide film 46b (Oxide), and the p-type portion 49 (Semiconductor). The drain 23
`of the MOSFET 21C is electrically connected to the second electrode 51 of the second MOS diode 48 by
`a conductor pattern (not shown) or the like.
`
`【0066】 Furthermore, on the side of this second MOS diode 48, on the upper surface of the n-type
`substrate 44, a second dielectric layer 53 and a resistor layer 54 are laminated with the first dielectric
`layer 52 interposed therebetween. are arranged side by side. Furthermore, one electrode 55 of a pair of
`capacitor electrodes is formed on the upper surface of the second dielectric layer 53, while the other
`electrode 56 is formed on the upper surface of the left end portion of the resistor layer 54 in the drawing.
`are respectively formed to constitute a capacitor 57 . One electrode 55 is electrically connected to the gate
`22 of the MOSFET 21C by a conductor pattern or the like (not shown), and the other electrode 56 is
`electrically connected to the first electrode 50 of the second MOS diode 48 by a conductor pattern or the
`like. ing.
`
`【0067】 An electrode 58 is formed on the upper surface of the right end portion of the resistor layer 54
`by metal deposition or the like to constitute a resistor 59, and the electrode 58 is electrically connected to
`a DC power supply 60 (VC). . The semiconductors of the n-type substrate 44, p-channel 45 and second p-
`type portion may be replaced with p-type or n-type semiconductors, respectively.
`
`【0068】 FIG. 5 is an equivalent circuit diagram of the semiconductor device configured as described
`above during source-grounded operation, showing a state in which the waveform distortion reduction
`circuit 47 is interposed between the gate 22 and the drain 23 of the depletion type MOSFET 21C. ing.
`
`【0069】 The equivalent circuit of this waveform distortion reduction circuit 47 connects the equivalent
`capacitance 61 (C2) of the second MOS diode 48 to the capacitor 57 (C1) in series, and the equivalent
`circuit of the capacitor 57 and the second MOS diode 48 is connected in series. A DC power supply 60 is
`electrically connected to the connection with the capacitor 61 via a resistor 59 . The DC power supply 60
`applies a voltage that is twice the voltage (VD) applied to the drain 23 (2VD) to about the same as the
`voltage (VG) applied to the gate 22 .
`
`7
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`

`【0070】 An equivalent MOS diode 22a is formed between the gate 22 of the MOSFET 21C and the p-
`channel 45, and an equivalent capacitance Cdg is formed in this equivalent MOS diode 22a.
`
`【0071】 Therefore, when a voltage of approximately 2VD to VG is applied from the DC power supply
`60 to the second MOS diode 48 such that the voltage between the electrodes becomes approximately
`equal to the potential difference between the gate 22 and the drain 23 of the MOSFET 21C, The total
`feedback capacitance CF between 23 is expressed by the following equation (6).
`
`【0072】[Number 6]
`
`【0073】 Also, when the potential difference between the gate and the drain changes by ΔV, the
`capacitance CF is expressed by the following equation (7).
`
`【0074】[Number 7]
`
`【0075】 Since C(|V|) is a monotonically decreasing and continuous function of |V| in the operating
`region of the MOSFET 21C, this equation (7) can be approximated by the following equation (8). can.
`
`【0076】[Number 8]
`
`【0077】[Number 9]
`
`【0078】 Therefore, even if the input signal is input to the gate 22, the change in the feedback
`capacitance can be reduced, so the secondary asymmetric waveform distortion of the output signal from
`the drain 23 can be reduced. Moreover, by making the physical specifications of the second MOS diode
`48 similar to the equivalent MOS diode between the gate and the channel and arranging this second MOS
`diode 48 in the vicinity of the p-channel 45, a wide input power can be achieved. And the second-order
`asymmetric amplitude distortion can be reduced in a wide frequency range and a wide temperature range.
`
`【0079】INDUSTRIAL APPLICABILITY As described above, according to the semiconductor device
`of claim 1 of the present application, when the source-grounded operation of the field-effect transistor is
`performed, the equivalent diode between the gate and the drain and the reverse-polarity diode are each
`reverse-biased. Therefore, junction capacitances are generated in these equivalent diodes and reverse
`polarity diodes, respectively, and these junction capacitances act as feedback capacitances from the drain
`to the gate.
`
`【0080】 However, since the polarities of these two diodes are opposite to each other, the directions of
`capacitance changes of these two diodes are opposite and cancel each other out. Therefore, even if a
`signal is input to the gate, the change in the total feedback capacitance between the gate and the drain can
`be reduced, so that the waveform distortion of the output signal due to the change in the feedback
`capacitance can be reduced. Therefore, a diode with similar C-V (capacitance-voltage) characteristics of
`an equivalent diode should be used as the reverse-polarity diode, and reverse-biased so that the voltage
`applied to this reverse-polarity diode is approximately equal to the potential difference between the gate
`and drain. Thus, it is possible to further reduce the second-order symmetrical waveform distortion of the
`output signal and improve the second-order symmetry of the output signal.
`
`【0081】 According to the semiconductor device of claim 2, a reverse bias can be applied to the reverse
`polarity diode by a DC power supply via a resistor or an inductor so that the applied voltage is
`substantially equal to the potential difference between the gate and the drain. . Therefore, by the same
`effect as the invention of claim 1, it is possible to reduce the change in the feedback capacitance between
`
`8
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`

`the gate and the drain, thereby reducing the waveform distortion of the output signal, especially the
`second-order asymmetric waveform distortion.
`
`【0082】 According to the semiconductor device of claim 3, when the depletion-type MOS field effect
`transistor operates with its source grounded, the MOS diode generates an equivalent capacitance opposite
`in polarity to the equivalent capacitance of the equivalent MOS diode between the gate and the drain. ,
`these equivalent capacitances act as feedback capacitances from the drain to the gate.
`
`【0083】 However, since the polarities of these two equivalent capacitances are opposite to each other,
`the directions of change of these two capacitances are also opposite and cancel each other out. Therefore,
`even if a signal is input to the gate, the change in the total feedback capacitance between the gate and the
`drain can be reduced, so that the waveform distortion of the output signal due to the change in the
`feedback capacitance can be reduced. Therefore, the MOS diode is formed into a diode that has a C-V
`(capacitance-voltage) characteristic similar to that of an equivalent MOS diode between the gate and
`drain, and the voltage applied to this MOS diode is reversed so that the potential difference between the
`gate and drain is approximately equal. By biasing, it is possible to further reduce second-order symmetric
`waveform distortion of the output signal and improve the second-order symmetry of the output signal.
`
`【0084】 According to the semiconductor device of claim 4, a reverse bias is applied to the MOS diode
`by a DC power supply via a resistor or an inductor such that the applied voltage is substantially equal to
`the potential difference of the equivalent MOS diode between the gate and the drain. can be done.
`Therefore, by the same action as the invention of claim 3, it is possible to reduce the change in the
`feedback capacitance between the gate and the drain, thereby reducing the waveform distortion of the
`output signal, especially the second-order asymmetric waveform distortion.
`
`【0085】According to the semiconductor device of claim 5, since the waveform distortion reducing
`means including the MOS diode is formed integrally with the substrate of the field effect transistor such
`as a depletion type MOSFET and formed on one chip, the MOS diode and an equivalent MOS diode
`between the gate and the drain, and physical specifications such as C-V (capacitance-voltage)
`characteristics can be formed almost the same. For this reason, the changes in the two opposite
`capacitances of the MOS diode and the equivalent MOS diode can be made more equal, so that the
`change in the feedback capacitance between the gate and the drain can be further reduced to further
`reduce the secondary asymmetric distortion of the output signal. can be done.
`
`【0086】 According to the amplifier of claim 6, it is possible to reduce the change in the feedback
`capacitance between the drain on the output side and the gate on the input side, thereby reducing
`waveform distortion such as secondary asymmetric waveform distortion of the output signal. 6. Since the
`semiconductor device according to any one of 1 to 5 is used as an amplifying element, the capacitance
`change of the feedback circuit when the input signal is superimposed on the gate is reduced to reduce
`waveform distortion such as secondary asymmetric waveform distortion. can be done.
`
`[Brief description of the drawing]
`
`【Figure 1】 1 is an equivalent circuit diagram of the semiconductor device according to the first
`embodiment of the present invention; FIG.
`
`【Figure 2】 FIG. 2 is a vertical cross-sectional view of essential parts when the embodiment shown in
`FIG. 1 is applied to an n-channel J-type FET;
`
`9
`
`

`

`[Fig.3] FIG. 4 is a vertical cross-sectional view of essential parts of a semiconductor device according to a
`second embodiment of the present invention;
`
`[Figure 4] FIG. 10 is a vertical cross-sectional view of essential parts of a semiconductor device
`according to a third embodiment of the present invention;
`
`[Fig.5] FIG. 5 is an equivalent circuit diagram of the semiconductor device shown in FIG. 4 during
`source-grounded operation;
`
`[Fig.6] Partial vertical cross-sectional view of a conventional n-channel JFET.
`
`[Fig.7] FIG. 3 is a partial vertical cross-sectional view of a conventional n-channel MESFET;
`
`[Fig.8] FIG. 2 is a partial vertical cross-sectional view of a conventional depletion-type MOSFET;
`
`[Fig.9] FIG. 7 is an equivalent circuit diagram of the conventional n-channel planar J-type FET shown in
`FIG. 6 and the conventional n-channel MESFET shown in FIG. 7 during common-source operation;
`