Attorney Docket No.
`
`[249115US2
`
`
`
`HIGH VOLTAGE INTEGRATED CIRCUIT
`
`oO
`
`1.
`
`2. HH Specification
`
`Total Sheets
`
`
`
`
`
`b.
`
`.
`
`i 52’oOO
`
`.
`
`See 37 CFR 1.27
`
`
`oS
`UTILITY
`
`
`
`
`PATENT APPLICATION
`
`—"
`TRANSMITTAL
`
`
`
`E
`(Off
`2. new nonprovisional applications under 37 CFR 1.53(b))
`
`
`
`
`
`.
`Commissioner for Patents
`
`
`\
`APPLICATION ELEMENTS
`ADDRESS TO: Mail Stop Patent Application
`De
`See MPEP chapter 600 conceming utility patent application contents
`
`
`
`Alexandria, Virginia 22313
`
`
`
`RS
`ACCOMPANYING APPLICATION PARTS
`[Ef Fee Transmittal Form (e.g. PTO/SB/17)
`(Submit an original and a duplicate for fee processing)
`7. #@ Assignment Papers (cover sheet & document(s)
`
`
`
`8. HI Application Data Sheet. See 37 CFR 1.76
`
`
`
`9. & 37 C-F.R. §3.73(b) Statement
`oO Powerof
`
`
`(when there is an assignee)
`Attorney
`
`
`
`Drawing({s) (35 U.S.C. 113) Total Sheets
`10. 0 English Translation Document(if applicable)
`
`.
`;
`;
`1. information Disclosure
`ry Copies of IDS
`
`Statement (IDS)/PTO-1449
`Citations (1)
`
`
`
`Total Pages
`4. 9 Oath or Declaration
`
`12. O Preliminary Amendment
`a.
`
`
`ME Newly executed (original)
`13. HJ White Advance Serial No. Postcard
`0 Copy fromapriorapplication (37 C.F.R. §1.63(d))
`
`14. Certified Copy of Priority Document(s) (1)
`(for continuation/divisiona! with box 17 completed)
`.
`(if foreign priority is claimed)
`
`i. OO DELETION OF INVENTOR(S)
` 15.0 Applicant claims small entity status.
`Signed statement attached deleting inventor(s) namedin
`the prior application, see 37 C.F.R. §1.63(d)(2) and
`1,33(b).
`. HE Other: Request for Priority
`
`CD-ROM or CD-Rin duplicate, large table or Computer
`Program (Appendix)
`
`Nucleotide and/or Amino Acid Sequence Submission
`(if applicable, all necessary)
`
`Oo |Computer Readable Form (CRF)
`
`
`Specification or Sequence Listing on:
`i.
`[CD-ROM or CD-R (2 copies); or
`
`ii.
`OO) Paper
`
`c. © Statementsverifying identity of above copies
`
`
`
`17.
`\fa CONTINUING APPLICATION, check appropriate box, and supply the requisite information below:
`of prior application no.:
`0 Continuation
`0) Divisional
`0) Continuation-in-part (CIP)
`
`Prior application information:
`Examiner:
`Group Art Unit:
`
`
`For CONTINUATION ORDIVISIONAL APPSonly: The entire disclosure of the prior application, from which an oath or declaration is supplied under Box 4b,is
`
`considered a part of the accompanying continuation or divisional application and is hereby incorporated by reference. The incorporation can only be relied upon
`when a portion has been inadvertently omitted from the submitted application parts.
`
`18. CORRESPONDENCE ADDRESS
`
`Customer Number
`
`22850
`(703) 413-3000
`FACSIMILE: (703) 413-2220
`
`
`|Name:|marvinsspivkRegistrationNos|zagrs
`
`|signatwre:|AmWIGWend|vate:|2Clof
`|amesfTLReistationtosf
`“Cotrvin wicClelland
`Registration Number 21 124
`
`Page 1 of 216
`
`BMW EXHIBIT 1002
`
`BMW EXHIBIT 1002
`
`

`

`<—
`Degtet No.
`
`249115US2
`
`=
`IN THE UNITED STATES.PATENT AND TRADEMARK OFFICE
`INVENTOR(S) Kazuhiro SHIMIZU
`
`SERIAL NO:
`
`New Application
`
`FILING DATE: Herewith
`
`FOR:
`
`HIGH VOLTAGE INTEGRATED CIRCUIT
`
`COMMISSIONERFOR PATENTS
`ALEXANDRIA, VIRGINIA 22313
`
`
`FEE TRANSMITTAL
`
`
`
`TOTAL CLAIMS|26-2=|6‘|xsis=|$108.00
`INDEPENDENT CLAIMS|4 -3=|1|x$86=|$86.00
`CO MULTIPLE DEPENDENTCLAIMS(If applicable)
`$0.00
`O_LATE FILING OF DECLARATION
`$0.00
`
`
`
`
`
`BASIC FEE
`
`$770.00
`
`CALCULATIONS|
`
`
`
`
`
`
`
`TOTAL OF ABOVE CALCULATIONS
`(REDUCTION BY 50% FORFILING BY SMALL ENTITY
`
`O FILING IN NON-ENGLISH LANGUAGE
`a aQie)wnoS>a °Z O°7 > ”2QZzSmZ4
`
`+
`
`$40
`
`=
`
`$964.00
`$0.00
`
`$0.00
`
`$40.00
`
`
`
`
`— ee
`TOTAL
`$1,004.00 |
`
`‘
`
`Please charge Deposit Account No. 15-0030 in the amount of $0.00 A duplicate copy ofthis sheet is enclosed.
`
`A check in the amountof
`
`to coverthe filing fee is enclosed.
`
`Bmeoda The Director is hereby authorized to charge any additional fees which maybe required for the papers beingfiled
`
`Credit card paymentform is attached to coverthe filing fee in the amount of $1,004.00
`
`herewith and for which no check or credit card paymentis enclosed herewith, or credit any overpayment to Deposit
`
`Account No. 15-0030. A duplicate copy of this sheet is enclosed.
`
`Respectfully Submitted,
`
`OBLON, SPIVAK, McCLELLAND,
`MAIER & NEUSTADT,P.C.
`
`i
`
`Marvin J. Spivak
`Registration No.
`
`24,913
`
`C.Irvin McClelland
`Registration Number21,124
`
`Date:
`
`Z)t4loy
`
`.
`
`Customer Number
`22850
`Tel. (703) 413-3000
`Fax. (703) 413-2220
`(OSMMN 05/03)
`
`Page 2 of 216
`
`

`

`Attorney Docket No.
`
`[249115US2
`
`
`
`HIGH VOLTAGE INTEGRATED CIRCUIT
`
`oO
`
`1.
`
`2. HH Specification
`
`Total Sheets
`
`
`
`
`
`b.
`
`.
`
`.
`
`See 37 CFR 1.27
`
`
`oS
`UTILITY
`
`
`
`
`PATENT APPLICATION
`
`—"
`TRANSMITTAL
`
`
`
`E
`(Off
`2. new nonprovisional applications under 37 CFR 1.53(b))
`
`
`
`
`
`.
`Commissioner for Patents
`
`
`\
`APPLICATION ELEMENTS
`ADDRESS TO: Mail Stop Patent Application
`De
`See MPEP chapter 600 conceming utility patent application contents
`
`
`
`Alexandria, Virginia 22313
`
`
`
`RS
`ACCOMPANYING APPLICATION PARTS
`[Ef Fee Transmittal Form (e.g. PTO/SB/17)
`(Submit an original and a duplicate for fee processing)
`7. #@ Assignment Papers (cover sheet & document(s)
`
`
`
`8. HI Application Data Sheet. See 37 CFR 1.76
`
`
`
`9. & 37 C-F.R. §3.73(b) Statement
`oO Powerof
`
`
`(when there is an assignee)
`Attorney
`
`
`
`Drawing({s) (35 U.S.C. 113) Total Sheets
`10. 0 English Translation Document(if applicable)
`
`.
`;
`;
`1. information Disclosure
`ry Copies of IDS
`
`Statement (IDS)/PTO-1449
`Citations (1)
`
`
`
`Total Pages
`4. 9 Oath or Declaration
`
`12. O Preliminary Amendment
`a.
`
`
`ME Newly executed (original)
`13. HJ White Advance Serial No. Postcard
`0 Copy fromapriorapplication (37 C.F.R. §1.63(d))
`
`14. Certified Copy of Priority Document(s) (1)
`(for continuation/divisiona! with box 17 completed)
`.
`(if foreign priority is claimed)
`
`i. OO DELETION OF INVENTOR(S)
` 15.0 Applicant claims small entity status.
`Signed statement attached deleting inventor(s) namedin
`the prior application, see 37 C.F.R. §1.63(d)(2) and
`1,33(b).
`. HE Other: Request for Priority
`
`CD-ROM or CD-Rin duplicate, large table or Computer
`Program (Appendix)
`
`Nucleotide and/or Amino Acid Sequence Submission
`(if applicable, all necessary)
`
`Oo |Computer Readable Form (CRF)
`
`
`Specification or Sequence Listing on:
`i.
`[CD-ROM or CD-R (2 copies); or
`
`ii.
`OO) Paper
`
`c. © Statementsverifying identity of above copies
`
`
`
`17.
`\fa CONTINUING APPLICATION, check appropriate box, and supply the requisite information below:
`of prior application no.:
`0 Continuation
`0) Divisional
`0) Continuation-in-part (CIP)
`
`Prior application information:
`Examiner:
`Group Art Unit:
`
`
`For CONTINUATION ORDIVISIONAL APPSonly: The entire disclosure of the prior application, from which an oath or declaration is supplied under Box 4b,is
`
`considered a part of the accompanying continuation or divisional application and is hereby incorporated by reference. The incorporation can only be relied upon
`when a portion has been inadvertently omitted from the submitted application parts.
`
`18. CORRESPONDENCE ADDRESS
`
`Customer Number
`
`22850
`(703) 413-3000
`FACSIMILE: (703) 413-2220
`
`
`i 52’oOO
`
`|Name:|marvinsspivkRegistrationNos|zagrs
`
`|signatwre:|AmWIGWend|vate:|2Clof
`|amesfTLReistationtosf
`“Cotrvin wicClelland
`Registration Number 21 124
`
`Page 3 of 216
`
`

`

`<—
`Degtet No.
`
`249115US2
`
`=
`IN THE UNITED STATES.PATENT AND TRADEMARK OFFICE
`INVENTOR(S) Kazuhiro SHIMIZU
`
`SERIAL NO:
`
`New Application
`
`FILING DATE: Herewith
`
`FOR:
`
`HIGH VOLTAGE INTEGRATED CIRCUIT
`
`COMMISSIONERFOR PATENTS
`ALEXANDRIA, VIRGINIA 22313
`
`
`FEE TRANSMITTAL
`
`
`
`TOTAL CLAIMS|26-2=|6‘|xsis=|$108.00
`INDEPENDENT CLAIMS|4 -3=|1|x$86=|$86.00
`CO MULTIPLE DEPENDENTCLAIMS(If applicable)
`$0.00
`O_LATE FILING OF DECLARATION
`$0.00
`
`
`
`
`
`BASIC FEE
`
`$770.00
`
`CALCULATIONS|
`
`
`
`
`
`
`
`TOTAL OF ABOVE CALCULATIONS
`(REDUCTION BY 50% FORFILING BY SMALL ENTITY
`
`O FILING IN NON-ENGLISH LANGUAGE
`a aQie)wnoS>a °Z O°7 > ”2QZzSmZ4
`
`+
`
`$40
`
`=
`
`$964.00
`$0.00
`
`$0.00
`
`$40.00
`
`
`
`
`— ee
`TOTAL
`$1,004.00 |
`
`‘
`
`Please charge Deposit Account No. 15-0030 in the amount of $0.00 A duplicate copy ofthis sheet is enclosed.
`
`A check in the amountof
`
`to coverthe filing fee is enclosed.
`
`Bmeoda The Director is hereby authorized to charge any additional fees which maybe required for the papers beingfiled
`
`Credit card paymentform is attached to coverthe filing fee in the amount of $1,004.00
`
`herewith and for which no check or credit card paymentis enclosed herewith, or credit any overpayment to Deposit
`
`Account No. 15-0030. A duplicate copy of this sheet is enclosed.
`
`Respectfully Submitted,
`
`OBLON, SPIVAK, McCLELLAND,
`MAIER & NEUSTADT,P.C.
`
`i
`
`Marvin J. Spivak
`Registration No.
`
`24,913
`
`C.Irvin McClelland
`Registration Number21,124
`
`Date:
`
`Z)t4loy
`
`.
`
`Customer Number
`22850
`Tel. (703) 413-3000
`Fax. (703) 413-2220
`(OSMMN 05/03)
`
`Page 4 of 216
`
`

`

`
`
`TITLE OF THE INVENTION
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`
`
`
`
`
`HIGH VOLTAGE INTEGRATED CIRCUIT
`
`
`
`BACKGROUNDOF THE INVENTION
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`5
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`Field of the Invention
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`The present invention relates to a semiconductor device, and more particularly,
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`to a high voltage integrated circuit.
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`Description of the Background Art
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`10~—great functionality and cost reduction in the field of mechatronics including motor
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`A high voltage integrated circuit (HVIC) is a device indispensable for achieving
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`control.
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`For instance, an HVIC is employed as a gate driver in a powertransistor such as
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`an IGBT(Integrated Gate Bipolar Transistor) used for performing bridgerectification of a
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`power line.
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`In this HVIC, when a high side IGBT and a low side IGBT are broughtinto
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`15
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`an on state at
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`the same time (which is called a “shoot-through” phenomenon),
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`short-circuit occurs between arms (powerlines) to cause a large current to flow into the
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`IGBTs, which are therefore damaged.
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`To prevent this, the HVIC is controlled such that a high side gate driver output
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`and a low side gate driver output are complementarily outputted. However, since the
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`20~—sgate driver outputs are not monitored in practice, the high side IGBTis short-circuited in
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`the case where a potential at a node between the high side IGBT and low side IGBT
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`(hereinafter referred to as “potential VS”) is short-circuited to a ground potential (GND)
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`(i.e., ground-fault occurs) due to failure in loads or the like while the high side gate driver
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`continues outputting (i.e., while the high side IGBT is in an ON state). Therefore, the
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`‘high side IGBT needs to be tumed off immediately, however, the HVIC is incapable of
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`Page 5 of 216
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`Page 5 of 216
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`

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`2
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`determining that the potential VS has become GND,and therefore causes the high side
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`gate driver to continue outputting.
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`To prevent this, simply saying, the potential VS may be monitored. However,
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`the potential VS usually reaches several hundred volts.
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`Thus,it is impossible to monitor
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`5
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`the potential VS within the HVIC.
`For instance, Japanese Patent Application Laid-Open No. 9-172358 (1997)
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`discloses detecting overcurrent in the case where an emitter terminal of a high side IGBT
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`is short-circuited to GND, thereby controlling the high side IGBT on the basis of a
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`detection signal (see columns 6-7, Figs. 1-3). With this method, however, a certain
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`10___—period of time is required until a control signal is applied to the high side IGBT, during
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`which short-circuit continues. Therefore, the high side IGBT needsto have resistance to
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`a short-circuit state for a certain period of time, which is a contributing factor responsible
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`for increase in manufacturing costs.
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`15
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`SUMMARY OF THE INVENTION
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`An object of the present invention is to provide a high voltage integrated circuit
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`for preventing damage to a semiconductor device used for performing bridge rectification
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`of a powerline.
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`A first aspect of the present invention is directed to a semiconductor device
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`~—sincluding a high potential part, a low side logic circuit, first and second level shift parts
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`and a voltage detecting device, and performs drive control of first and second switching
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`devices connected in series and interposed between a high main powerpotential and a
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`low main power potential. The high potential part includes a control part configured to
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`control conduction/non-conduction of a high side switching device which is one of the
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`first and second switching devices. The low side logic circuit is provided in a low
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`Page 6 of 216
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`Page 6 of 216
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`

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`3
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`potential part operating on the basis of the low main power potential and configured to
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`generate a control signal on the basis of a signal applied from outside, the control signal
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`having a first state indicating conduction of the high side switching device and a second
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`state indicating non-conduction of the high side switching device, and to generate first
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`an
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`and secondpulse signals on the basis of the control signal in correspondence with thefirst
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`level-shift the first and second pulse signals to the high potential part to obtain first and
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`second level-shifted pulse signals,
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`respectively.
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`The voltage detecting device is
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`provided in the low potential part and configured to detect a potential at an output line of
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`at least one of the first and second level shift parts and to supply a logic value based on
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`the potential for the low side logic circuit, thereby controlling an operation of the low side
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`logic circuit.
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`The voltage detecting device provided in the low potential part detects the
`potential at an output line of at least one of the first and second level shift parts, thatis,
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`phase fault protection for the high side switching device can be realized at low costs.
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`A second aspect of the invention is directed to a semiconductor device
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`20=including a high potential part, a reverse level shift part and a voltage detecting device
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`conduction/non-conduction of a high side switching device which is one of the first and
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`second switching devices. The reverse level shift part is configured to level-shift a
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`output line of the reverse level shift part and to supply a logic value based on the potential
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`10=and second switching devices, the control part controls the high side switching device for
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`device is immediately brought into a non-conducting state. Thus, phase fault protection
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`for the high side switching device can effectively be achieved.
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`a high side switching device which is one of the first and second switching devices. The
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`main power potential and configured to generate a control signal on the basis of a signal
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`applied from outside, the control signal having a first state indicating conduction of the
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`high side switching device and a second state indicating non-conduction of the high side
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`switching device, and to generate first and second pulse signals on the basis of the control
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`Page 8 of 216
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`detecting device is provided in the low potential part and is configured to detect a
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`potential at an output line extending out of the high potential part outputting the high
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`main power potential and to supply a logic value based on the potential for the low side
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`logic circuit, thereby controlling an operation of the low side logic circuit.
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`The voltage detecting device detects the potential at an output line extending
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`out of the high potential part and outputting the high main powerpotential, that is, the
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`high main potential. Therefore,
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`in the case where ground-fault occurs at the node
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`between.the first and second switching devices, the second pulse signal is generated at
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`that timing to bring the high side switching device into a non-conducting state. Thus,
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`10s
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`phase fault protection for the high side switching device can be achieved. Further,
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`detection of the potential at the output line extending out of the high potential part
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`increases flexibility in arrangementof the voltage detecting device.
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`A fourth aspect of the invention is directed to a semiconductor device including
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`a high potential part and a voltage detecting part and performs drive control offirst and
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`second switching devices connected in series and interposed between a high main power
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`potential and a low main powerpotential. The high potential part includes a control part
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`configured to control conduction/non-conduction of a high side switching device which is
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`one of the first and second switching devices. The voltage detecting device is provided
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`in the high potential part and inserted between the high main power potential and a node
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`20=between the first and second switching devices. The voltage detecting device is
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`configured to detect a potential at the node between the first and second switching
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`devices and to supply a logic value based on the potential for the control part, thereby
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`causing the control part to control conduction/non-conduction of the high side switching
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`device. The voltage detecting device includes at
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`least one MOS transistor whose
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`conduction/non-conduction is controlled on the basis of a potential at an output line
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`Page 9 of 216
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`Page 9 of 216
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`extending out of the low potential part outputting the low main powerpotential.
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`The voltage detecting device detecting the potential at the node between the
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`first and second switching devices for controlling conduction/non-conduction of the high
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`side switching device is provided in the high potential part. Therefore, in the case where
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`5—ground-fault occurs at the node between the first and second switching devices, the
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`control part is caused to control the high side switching device for bringing it into a
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`non-conducting state at that timing, so that the high side switching device is immediately
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`brought into a non-conducting state. Thus, phase fault protection for the high side
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`switching device can effectively be achieved.
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`10
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`These and other objects,
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`features, aspects and advantages of the present
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`invention will become more apparent from the following detailed description of the
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`present invention when taken in conjunction with the accompanying drawings.
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`BRIEF DESCRIPTION OF THE DRAWINGS
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`Fig. 1 is an explanatory view illustrating the circuit configuration of an HVIC
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`accordingto a first preferred embodimentof the present invention;
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`Figs. 2 and 3 are timing charts explaining the operation of the HVIC according
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`Fig. 4 is a plan view illustrating the structure of the HVIC accordingto thefirst
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`20sipreferred embodiment;
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`Fig. 5 is a sectional! view illustrating the structure. of the HVIC according to the
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`Fig. 6 is a plan view illustrating the structure of a voltage detector of the HVIC
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`according to the first preferred embodiment;
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`Fig. 7 is a sectional view illustrating the structure of the voltage detector of the
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`Page10 of 216
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`Page 10 of 216
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`HVICaccording to the first preferred embodiment;
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`Fig. 8 is an explanatory view illustrating the circuit configuration of a second
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`modification of the HVIC accordingto the first preferred embodiment;
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`Fig. 9 is a table explaining the operation of a majority logic circuit;
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`Fig. 10 is an explanatory view illustrating a third modification of the HVIC
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`according to the first preferred embodiment;
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`Fig. 11 is a plan view illustrating the structure of a voltage detector of the third
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`modification of the HVIC accordingtothe first preferred embodiment;
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`Figs. 12 and 13 are sectional views illustrating the structure of the voltage
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`detector of the third modification of the HVIC according to the first preferred
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`Fig. 14 is an explanatory view illustrating the circuit configuration of a fourth
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`modification of the HVIC according to the first preferred embodiment;
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`Fig. 15 is a plan view illustrating the structure of a voltage detector of the
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`15
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`fourth modification of the HVIC according to the first preferred embodiment;
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`Fig. 16 is a sectional view illustrating the structure of the voltage detector of the
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`fourth modification of the HVIC accordingto the first preferred embodiment;
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`modification of the HVIC according to the first preferred embodiment;
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`detector of the fourth modification of the HVIC according to the first preferred
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`Fig. 20 is a plan view illustrating a voltage detector of a fifth modification of
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`the HVIC accordingto the first preferred embodiment;
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`Fig. 21 is a sectional view illustrating the voltage detector of the fifth
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`modification of the HVIC accordingto the first preferred embodiment;
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`Fig. 22 is a graph explaining the operation of the voltage detector of the fifth
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`modification of the HVIC according to the first preferred embodiment;
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`modification of the HVIC accordingto the first preferred embodiment;
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`Fig. 24 is an explanatory view illustrating the configuration of a bias voltage
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`output circuit;
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`Fig. 25 is an explanatory view illustrating the circuit configuration of an HVIC
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`according to a second preferred embodimentof the invention;
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`Fig. 26 is a plan view illustrating the structure of the HVIC according to the
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`Fig. 27 is a sectional view illustrating the structure of the HVIC according to ~
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`Fig. 28 is an explanatory view illustrating the circuit configuration of an HVIC
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`according to a third preferred embodimentof the invention;
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`Fig. 29 is a plan view illustrating the structure of the HVIC according to the
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`Fig. 30 is a sectional view illustrating the structure of the HVIC according to
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`the third preferred embodiment;
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`Fig. 31 is an explanatory view illustrating the circuit configuration of an HVIC
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`according to a fourth preferred embodimentof the invention;
`Fig. 32 is a plan view illustrating the structure of the HVIC according to the
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`fourth preferred embodiment; and
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`Fig. 33 is a sectional view illustrating the structure of the HVIC according to
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`the fourth preferred embodiment.
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`Page 12 of 216
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`Page 12 of 216
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`DESCRIPTION OF THE PREFERRED EMBODIMENTS
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`First Preferred Embodiment
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`1. Circuit Configuration
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`5
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`Fig. 1 illustrates the configuration of a high voltage integrated circuit (HVIC)
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`100 according to a first preferred embodimentof the present invention.
`In Fig. 1, power devices 12 and 13 such as IGBTs (integrated Gate Bipolar
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`Transistors) are totem-pole-connected between a high side (HV) powerline and a low
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`(ground potential GND) side power line,
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`to form a half-bridge power device. Free
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` ~=wheel diodes D1 and D2 are connected inversely in parallel to the power devices 12 and
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`13, respectively. Then, a load (an inductive load such as a motor) is connected to a node
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`N1 between the power devices 12 and 13.
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`In Fig. 1, the power device 12 switches between a potential at the node N1 used
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`aS a reference potential and the potential (HV) at a high side powerline, and is called a
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`high side power device.
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`The power device 13 switches between the ground potential used as a reference
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`potential and the potential at the node N1, andis called a low side powerdevice.
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`Therefore, the HVIC 100 shown in Fig. 1 is divided into a high side power
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`device driving circuit HD and a low side powerdevice driving circuit LD.
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`The high side power device driving circuit HD includes a PMOStransistor 24
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`and an NMOStransistor 25 constituting a complementary MOS transistor (CMOS
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`transistor) with their source electrodes being respectively connected to two electrodes of a
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`capacitor 10 which is a power supply of the driving circuit HD, and complementarily
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`turns on/off the PMOStransistor 24 and NMOStransistor 25 to switch on/off the power
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`device 12. A voltage at a node between the PMOStransistor 24 and NMOStransistor
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`Page 13 of 216
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`Page 13 of 216
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`10
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`25 is called a high side output voltage or control signal HO.
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`In order to drive the PMOStransistor 24 and NMOStransistor 25, the high side
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`power device driving circuit HD further includes a pulse generator 3 generating a
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`pulse-like ON signal S2 and OFF signal S3, respectively, in response to positive and
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`5
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`negative level
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`transitions of a pulse-like control signal S1 (having first and second
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`potential states) supplied from an interface circuit 1 and generated on the basis of the
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`ground potential as the reference potential. The interface circuit 1 generates control
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`signals S1 and SO respectively on the basis of a high side contro! signal (HIN signal) and
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`a low side control signal (LIN signal) sent from a microcomputer provided outside.
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`10=Although illustration is omitted, the HVIC 100 also has the function of receiving a
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`reversely level-shifted si