WO FONT EGS?
`
`BCTAUSTENNERTER
`
`micromeiees, B copier oy gold aced Jayer 14)3 having a thickness benvesn G-008 and 00
`
`mierameters oe the adhesion layer 1412, and an electroplated cogper.or gold layer 1405 on the
`eopnerlor gold sed dayer P4ER. Nahe dayer 1405s elicieapined copper an optional nickel
`
`lever 1414 formed by amiable process or precesses. eg. by ac electroplating ar dlectraless
`
`slating process. tan be provided arrthe electrapiated copper dayer]40S, and ad apticnal gokl
`
`isyer 1415 formed bye suliable process or procaaaes, 6g, by an siectroglating ar clectraless
`plating progesy can be provided an the nickel layer 1414. Optionally, each of the DRAM
`
`
`
`eitps (192 may contain another potymer 1416,suchas ees or beazocycisbutene (ACB) Raving 3 thickness hebseta 2 aad 3) mlorsoeters on the
`
`on the sobamer layer 1409,.and openings 14177 in the polymer lever 1414 are aver the contact
`pobus F4b8, confleured for witebanding, of the redistributionchoult layer 14 Hy and che
`Pea
`coniuel points 2478 are at bottenss. af the openings 117, ARernatively the polymer layer
`
`Fhe rediswibuting ciroult layer 1401 can he provided directly cn the
`7408-can beomined.
`?
`passivation fayer3 and there de oa polyeer layer Gotweer the passivation layer A and the
`redistrindion circuit layer }441. Anmatively, the oalymer layer [416 can be audued and
`
`
`there is no polyinier Inver over tie redigthiindion cick Laver 147)
`
`PREIZEA, Figs, 488 and 480 show top perspective wews of the BRAM chip 1392
`according fa fed embodiments Referringto Fig, 4443 thecontact points 1408 are arranged in
`x
`acenter ine [403 ofthe DRAM chip [392 parallel wih two opposiie edges [2928 and 1392
`ihe
`ofthe DRAM chip, ARernatively, referring to Fig, 488, the contact points 408 are drrangs
`
`in xe certer lines 142) and £422 Jefe and. sight awayfrans the center Hine 1403 ofthe DRAM
`
`chip E802, respectively, and parallel avah the lew opposite edges [3928 amd PaG.tb of the
`
`DRAM chip, The roghwt 1499 shown In. Figs, 488 and $80 enclosed by det lines indicates-a
`
`resion afinp aurface df the silicon semiconductor subsiraie (, inwhish the of-ohin drivers or
`
`receivers. 42 are growded, that is, there can be offechip drivers or receivers 42 ata horizantal
`
`plane dower than thal of the carmtact points 1408and each of the offchip drivers ar raceivers
`
`#2 is connected to and positioned sloge to ons of the contact points T408, as shown in Figs.
`
`in a cass, there Ds nse oe driver ar cecelververtically under the
`$8C48F and 4RH-4EK.
`eantacta 7408, as shown in Pigs.4B, ASE,48H and 48), Porexarmpls, the ef-cbip driver
`
`pr renciver 42, as shodin Figs. 480 and 488, ie ata horizontal plane lower than that ofthe
`contact pudal 1408 nunnecied te the ofchhy driver or receiver 42 and has g horizontal offset g
`
`fram the carter of the contact point 1408 by a range. feen His 250 micrometers, with the
`contact points E408 chown in Fig. 488 arranged indwe center lines 14) aad 1422 leh ahd
`aSi
`
`Ex.1002
`APPLEINC./ Page 744 of 1071
`
`Ex.1002
`APPLE INC. / Page 744 of 1071
`
`

`

`We? 2URT LAGS?
`
`PCTAUISOTRG
`
`right way from the center Hine 1409 of the DRAM hie 1292, rapeetively, Also. when the
`comact points 1408, as shows in Fig 486 are aanged in a camer Dime 1405 afthe DRAM
`chip 907 parallel with two opposite edges 12928 dnd 13925 of the DRAMchip, the off-chip
`avivey or reesiver 42 ata horizontal plane lower tear that of the cenisct point 1408 connected
`io the diPchip driver or receiver 42 may Have « horizental affect p from the center ofthe
`
`eontact palm 1408 by a range dom OM} to 50 ndcrommviers, as shown in Figs. 48Hand 483.
`
`In another case, there can be off-chip drivers or recwivers 82 verdoally under tee
`{981284}
`contact points 1408, Ab shown in Fig, 48D) aad 4BF, the confact paints 1408 can be vertically
`aver aod connected to the wdPohin driver.or receiver
`42, adih the. contact points }408 chown in
`Fig. 488 axeanged ie (aay Center Hines 42) amd 1422 feft and sight away fram the center ine
`
`103 afthe DRAM chip Pa92, reapechy fy aid a width or diameter Dye? the apening [407 oir
`=
`ihe pussivation Inver 5 can be. as.smail as
`
`possible, and, for ssample, can be between G2 and
`
`20 misrometers, and areferably hetewodn GA and § pdcromefers.Algo, whon We contact points
`(408, as shown in Fig. 480, are arrangedin a certer Hoe 1453 of the DRAM chip 12parallel
`wih fvo appaiite Giges $502aval P263b athe DRAM ship,
`the coofact points T4408, ge
`shewot iy Figg. 48] and ISR, aan be vertlosihy over and connected to the afbchip driver or
`recelver.42, and a width or diameer D ofthe opening P40) Inthe passivation layer S can be as
`small av puasible, aad, for examele,
`can be between U2 and 20 micrometers, and preferably
`Senvern. 8.9 and Smictosieter:iw
`
`{GG283} Referrinwie Pigs, 28and 48G, the distance s helween the lefborright alge and
`the center Ene 1403 ofthe ORAM chip $392 may range from: [50 and SOD mricrometers. Four
`of the eight memory banks 1404 great the defi aide ofthe region [4/9 and the other fur of the
`eighimemory banks 1404 are. atthe right side: of the region 1419. Referring toFig. 48Q, the
`¥
`redistibution ciecull Javer 14/1 canbe patterned with rmultiple rediairibated traces 14] 1a eactbei
`connecting one of the contact poneL408 4a one of the contact pointe 1418, configured for
`wireGonding, arranwed.
`in a Hine cloge to the edge 13504. Aernatively, referring to Fig. SBE,
`the rediguithaiod oeod Jayer 1411 cad Ge patiemied with nnmiple redietnbuted wacce 14a
`
`gach comecting one of the contact paints /408 to one of the contact points 1478, configured
`
`for wirebonding, arranged jn two Hanes cloge to.ihs eige [Gea,
`
`PGINS] A plaraliy of the previously deserihed DRAM chip #392 as Wlvetrated in.
`Pigs4eR-GSK can besidcked.
`for exanmple, there
`cand be Roar, elght, aintean ar thirty Reo
`oF DERLAMohipe [392 are stacked, as desoribed belnw:
`
`482
`
`Ex.1002
`APPLEINC./ Page 745 of 1071
`
`Ex.1002
`APPLE INC. / Page 745 of 1071
`
`

`

`WO FONT EGS?
`
`BCTAUSTENNERTER
`
`
`2 pan be mounted onte
`JOGIINT] Reterring to Fig. 48A, the bationumost PRAM chip 19
`the BGA subsiraie 1301 by adhering thesilicon semivonductmy substrate | afthe bettormnost
`DRAM chip 138200 the top side af the BGA substrate [381 asing a fim 1420 of @ ghie
`oS
`material, such as a polytier Gr an epaxy-based material, with a chickeces, between | and A
`micromteimrs, The apger DRAM chip 1392 con be mounted onte the lower INEAM chip 1392
`y adhering te. silorm substrate | of theupper DRAM chip $392 to the tog-dide of the lower
`ne
`mS,
`chip 1/392 sag anathes fim 1400 of the glue moterial The control chip 1996 can be mounted
`»*
`op side of the
`
`onto the tonrmast DRAMshie 1392 by adhering ths contra! chip F990 to the
`
`topmost DRAM chip (382 usiig another fifty 1420 of the glue material, The upper DRAM
`
`ship 1392 has a right partion overhanging the lower DRAM chip 7392, and the lower DRAM
`chip }392 has a JeR. portion net vertically Grater tho-agger DRAM chip 1992. The apper
`
`DRAM chy [302 hava def sidewall recessed {fom that of the flower DRAMohip (382. The
`
`wrebonded wites 1394 each may have an ed bonded with the contact point [418 of the upper
`DMAM chip, 1392 oc dhe sertaci point 1494 of the euntrol chip 1996 and anether end bonded
`whh the contact point P4178of the lower DRAM chip 1392 or with a metal pad 1399 af the
`
`SOA substrate 7991, Particularly,
`
`in case die wirchanded wires 1594 are copper wires,
`
`the
`
`wirebonded wires {394 each may haysiaretad bonded with the elentroplatead copper layer 1405
`
`of the-upper GRAM. chip 1392-09 with cbtiper of the contact paint 1432 of the contra) chip
`1996 and another end bonded with the electroplated copper layer 1405 of the Inwer DRAM
`chip 4992 a7 with eupper of thé metal pad 1399 of the BGA aubstrete 1301. Incase the
`wirebonded. wires 1304 are gold wires, the wirebanded wites [364 each may have ancend
`boarded with ibs Sprdered ahiminuni layer 400, the elecirsplated ealddayer 1408 ofthe goul
`isver [414 ofthe upper DRAM chip 1392 or with gad or alamnum. ofthe
`ce. 1433
`4 re,
`OZ, the
`
`of the contyol chip JO96 ard another end borded with the sputtered aluminum lays
`electroplated gold layer (405 or the gold layer [415 ef'the lower DRAM chip 1392 oP wih
`S
`soli ofthe memal pad 1299 atthe BGAsubstrate (391,
`
`
`
`(OUI88) The previously deseibed module 137 shown in Fig 373A, 378.370, STEN BBA,
`ine 8, 38 or 38 may inchide only ene procegar unit HS on ahe substrate. 301 or BGA
`ie
`ostraie I02, Allernatively, the manlule 127 may inclade.a phialily of the peoovsuer unit 309
`on ihe subsirate SUL or1 BUA substrate S02, and the way i assenibly ekher aneof the processor
`Hates S03 and to design the stouitad oiler ane of the proceases auntiy 203 ean be referented te
`1B
`as either Gne of the wave io assembly the processor unk 303 shown dy Ply. J7A, 278, 37C,
`
`463
`
`Ex.1002
`APPLEINC./ Page 746 of 1071
`
`Ex.1002
`APPLE INC. / Page 746 of 1071
`
`

`

`Wed QURAN L468
`
`PCTS20102 FHS
`
`x
`SD, SHA, TSB, SBCor TED and to design the circuit of the processar uni JOY chownin Pig.
`384,39H, 391 or OE
`
`(801289) For example,
`the module
`137 may include three progessor units 303 on the
`substrate 30] or BGA substrate 302. The& oop 3i3an oneof the pracesser unite 303 can be a
`cata
`emrakprocessingwuni? (EPL) chip desyried by XBG architecture ar degigned by na x86
`architecuires,
`the chip 393.
`in anather ane
`oof
`the processoy units 302 can be
`2
`sraphicesprocessing-und QGPL) ehip; and the chip S19 in the other ane of the processor anits
`
`33 can be a baseband chin,
`
`{QEF8OE Alternatively dhe module (37 mey Include two processor ante GO3 on the
`
`aubsttate 20} of BGA substrate 302- The chip 383 in one of the processor unite 303 can bee
`
`aystereon chip (SOC) inchwding a ographies-provessingaunl GGPD) ciroult black, a wireless
`
`Rieabarod hefiwork: GYLAN sircult block and « centralkpracessime-unn (CPU) circuit bhsck
`
`designed byx86 archiestare or by nog 2BA archilectures, amd the chip 323 ircthe other. one of
`
`the paieessur units 209 can be a baseband clip,
`
`{OGI29] Ahernatively, che module 137 may inchde oxo srocesser unis 302 on the
`substrate 301 o¢ BGA substrate 300. The chin 3323 inonc ofthe processor uns 303 can bea
`
`ayster-on ohin (SOCy inching « basehand. circult block, a wireless focal area network
`
`OWLANY civsult Block and a sehtrabprecessing-unlt (OPO olredii binok designed by x86
`
`architecture ar lymin SRG architectures, and the ohip 313 io the other one. af the processor
`
`wets J03 can bee praphica-procesaageant COPUY chip.
`Ree The previously deserbed module 137 shawn in fig. SPA, OTR, FIC, SPER SBA,
`
`JAof 38D), the previnnely deacribed chip-package module }18 shown In Fig. 326A, the
`he.
`
`prosiqushydescribed chipspackage module 18a shown in Fig: 36M, the previously desettbe:
`chip-gackage module 1] Rb shown tv Fie. $6,the previously déseribad chippackape mince
`HSe ghewn in Fig. 26G0.. dhe previousiy described sexmicentiietor ainps shown in Figs,
`2GA-I97,
`the previously described semiconductor chig ou fom the previously described
`aemigondictor wefer 1Gand the previously descrifeed chip package including the previously
`“déscfihed seminondiotot ship out fod the ofeviously described semloenductor wafer 10 can
`
`be used for a isephone, a coniiess phone a mobilephone, a smart phone, a netbook gomputer,
`a Rotdhook computer,
`€ digial Guvtera, a digital viden <cariera, a dipial plenire frame, a
`¥
`&
`‘
`‘
`Pp
`Pp
`f
`i
`{
`tersonal digkal assistant {PDA}, & pocket personal samputer, 8 portable personal computer, an
`
`tlectwanic Hook, 3 digital Gook, 2 deshiog odmoater, « tablet ar alate comipater, an antomobile
`
`a&4
`
`Ex.1002
`APPLEINC./ Page 747 of 1071
`
`Ex.1002
`APPLE INC. / Page 747 of 1071
`
`

`

`WO FONT EGS?
`
`BCTAUSTENNERTER
`
`dexvenic product, a mablic Inferaet dewee (MID). a mobile television a prajectar, a mobile
`praleciar, a.pice projesior, eamartproiecior a 3G video display, a FDtelevision (OPV), a gl
`vided ganw player A mobile ccinputer device, a nonble cammyniphone: (ale called mobilez
`phoneouicr or mattis personal camputer phone) which is aaevice or a aysiem- combining and
`providing, functions of computers arel phones, or a high performance and/or tow power
`
`computer or server, Tor gaample, used for chaud computing.
`
`7807293] When the module 137 shown in Fig. 374, 37R, 97, 37D, SEA, SERRA or
`38D ts used forthe motile eomipuphons, the memory size of the mass Serage previdedby the
`wisebontded sucked memory BGA parkege 138
`is larger than 4 pipabytes, Such as behween ¥
`yGuabvtes and | iiiien bytes, and the memary gee of de main menmary provided bythe
`Stacked DRAM. BCA packabe F360 is larger than HOO phegabytes, sach as Pepesen NO
`
`megabytes and: 258 giesbytes, and preferably berween 250 megabytes and O4 sigsbytes,
`
`HIN] When the module 137 shown in Big, SPA, 37, STO, 37D,IRA, SSR, SBCor
`38h: is used for the high perfarntaniece anor iow power scmputer or aerver,
`the 3D video
`dissiay, such ae SD telewiahart {3D TV), or ths 3D video game Blayver, and the high performance
`and/or dow power conipater Gy server, for example, can be ased far cloud caraputing, the
`
`memacy size ofthe mass storages provided by the wirebandsd eiacked memury EGA package
`ay 38 4s latger than ¢ gigabyies. gneh as benvesn 4 gigabytes and 128 iriition bytes, and
`&
`preferably between GA ggabvies and | diihun bytes. andahe
`sremiory alge af the sain meraery
`&
`provided by the atacked DRAM BOA package 199 (s targer Than 245 mepabytes, such as
`between 256 mogabyies and Jirilion bytes, and preferably between 1 are 256 pleahytes.
`
`fG1295}] When the module 137 shown in Fig IA, 378, 37C, S712, SBA, 28B, BCor
`SSD ie used for
`the mobile conipuphone,
`¢he cache memory chip 311
`can be a
`dynam le-random-acegssmemory
`JDRAND
`shin,
`3
`oF
`syachronous-dynanic-randonracessaHory
`(SDRAM)
`chip
`&
`Sldtistioramdom-accesementary (SRAM) chip, and the memorysize of the cache mamory chip
`
`31.
`
`is between HL) megabyies arid 22 pleabstes, aid preferably between 100. negabytes and 4
`
`2. f
`HMGLISH) When the module
`137 shown jn Pig: STA, SPR, JC, S704 SRA, IER GSE or
`3BE3 is uesed for ihe Meh performance andfor law pewar computer or server, the 3D video
`display Gr
`ahe FO video gare player,
`the
`cache memory chip JU can
`be
`a
`dynam k-random-acresssmeniry DRAM) chip, a sidiistc-random-arcesomemory (SRAM)
`46te
`
`Ex.1002
`APPLEINC./ Page 748 of 1071
`
`Ex.1002
`APPLE INC. / Page 748 of 1071
`
`

`

`Way DONT EGRT
`
`BCTUSARTOS0
`
`clip or a spnchronouadynamic-random-acceagememary (SDRARG chip, and ihe memory size
`4
`cea
`of the cache memory chip 321 is Gehveen: 1) megebyies atul 32 gigabytes, and preferably
`behveen LQG megabytes and 4 pinabyies,
`
`{QI287} The module 137 shown in Fig. STA, 378, 370, 37D, JRA, SRE, JSC of 38D, for
`
`example, oan-be crovide-for a Nigh. perfermanoe video display, especially for 9 video display,
`303
`
`add can be connected to. art imegite (Dailin} video display or in-gity (hullkin}
`oe
`aroun he connected to an external 319 video display, sack as 3D TY oc > video game player
`
`video diaplay,
`
`(OOPESS! Alernatively in Fig. S7A, 978, 39C) 37D, 384, JER, 38O or 38D, the chip 315
`
`niay bea memory chip, such as synchronous-dynamic-randearaceeesomermary (SDRAM) chip,
`
`aulistic-raidamaccessamémeary (SMAM) chip or dynanmiccrandom-accassanemory (ORAM)
`
`chip while che chip J1f may be a cenrabprooessing-aunlt (CPL) okup slesigned by x86
`arshitenture,.a sentral-processing-anit (CPUS chip designed by now aSé architentures, auch a8
`ARM, Strong ARM. cr MIPs, a baseband chip, « graphics-provessing-unit (GPU) chip, 3
`
`digtalsignalpeasessing GOSP} chip,
`a wireless docs ares nsfwark (WAN)
`thip, 8
`gicbal-gositioning-aystem (GPS) chip, » blmetoath chin, a aysiem-on chip (00) ieNGIO 3
`araphica-proceasinp-unl (GPU) cirenly bidck, a wireless face!) rea metwork (WLAN) tircul
`%
`black anda cénrafl-processing-unit GOPU) elroult block designed bys archilccture. or by non
`xSG architecnwes, bat not
`including any baseband circuit black, 3 systenian efip (SOC)
`
`iaiilaiaasbaseband circuit block a wireless local area network (QYLAN} circuit block and a
`
`eetirabbprooessing-und CCPL circuit. block designed by. 386 architecture or Oy non aft
`
`achiigntures, bul nat Inching arty gruphieapricessingind GOPLA circuit dock, a eystemeart
`p(hOOFincloding a baschand circuit:loch, a graphics-pronesgingainie (GPU) sleaull black
`and a conttal-grocessingiaie (CPi) circult block designed by x86 arclilecture ar by non x86
`
`architectures, bat net including any wirciess focal area metwork (WLAN) cirewit block, 3
`
`aystem-on chiy (00) inclading 8 baseband ciradt block and a wireless. fecal area nelwork
`rn
`OWLAN) oircalt block, but nat inoiuding any graphics-proceasing-ardt (GPU) clroull block and
`aay cénivalproesssingsunt GIPO} eircalt Block, a syatetiean chip (SOC)
`inchiding
`sraphice-praveggingauna (GPU) circuit Heck amd a wireless incal area network (WLAN)
`ironbhick, fat noi Including any baseband circult block and any central-processing-unit
`{CPU} circu’ black, a sisiermon chip (SOO) inching a graphice-prscesesg-unlt (OPUS
`tireait block,
`€ baselshd clrouit Mock, a digitalsignal-processing (OSP) circuit block, «
`
`aivelegs Inésl acca nenwork CWLAN) clrauls biaok and a centval-processing-umt (EU) ciroult
`
`block desiened by x88 architeeture oy by Row s8@ carchisecuures, ar a chip including
`866
`
`Ex.1002
`APPLEINC./ Page 749 of 1071
`
`Ex.1002
`APPLE INC. / Page 749 of 1071
`
`

`

`War ZURT LAGS?
`
`POTUSES F886
`
`fEPU irewit
`
` , }
`globsl-pasitioniig-aystem (GPS) revit black, a graphics-processing-unt (OPU} cerauit black,
`a baseband circuit block,
`wo dighalsipnal-processitig (DSP) ciecait block, and/er a winciess
`local avéa Remvork (WLAN) sitculs ifock. 4 is noted that dite archHechture can be also
`
`«Neck.
`
`a
`
`binefasth
`
`orca
`
` binsk,
`
`a
`
`désigned with the cireulls ustraied in Fig. PQA, JOR IT ar 39),
`
`{H0F296) According!s, aspedte and embadiments of the proscat dischwure can provide
`
`benciits and advardages over previous techniques
`
`features, benefits and advantages than have Geen
`RNHIGG] The componenis, steps,
`Mecwsaed are merely Hhuswative. None of them, ner adhe discussions relating to them, ars
`
`intended to Haut the scope of protection in any way. Namerous other embodiments are aisa
`canteripiated. Thess Inchide embodiments that have fewer, additional, and/or different
`scabiponents, gleos, featured, henalits und advantiges. Thies alse include embadimente in which
`fhe components andar stepeare arranged and/ororicred difierently,
`
`{86431 (no-veading the present disclosure, one skilled in the art will appreciate that
`ayobodigwras of the proserd disclosure. sun be iraplemented in ar Janiliated by computer
`
`hardware, software. finnwars, ar any combinalinns cf such, and over coor mare networks.
`
`Sulishis
`
`sofiware can duclade: cosmputerreadable.
`
`oF machineréadable Instractiony for
`
`performing methods and technignes (and, portions theres! of designing andlor cantralling the
`fabrisation of chip etrnciures in asversdarcie with the present disclosure. Any suitable sofware
`language
`(Gmachibedenendest
`er machine-imdependent!? may
`be
`aofizei. Morvover,
`embodiments efthe present diselosure cay he mecluded in or carriedbyvarious signals, €.2.,
`a8
`syansmitted over.a wireless RP of ER commmneiications Hak or d@wninaded tearm the Internet
`
`positions,
`ratings,
`ali measiremenis, valoes,
`$e0R382 Unless. otherwise sted,
`or
`magnitudes, sises, ard other spcoffioationythat areger forth in this soecl fication, inching hivthke.
`olaines that follow, areipgrenimate or ofa nominal value and not necessarily enget they8
`intended to: haved‘yeasonable range that ig someistent with the functions ta whickheyrelates and
`with what iss cmabryio the art by winch they pertain,
`
`{UGTSOR{ All articles, patents, patent applications, and e or publications which bave-been
`ched in this discloaureare hereby incorparated herein byreference.
`
`86?
`
`Ex.1002
`APPLEINC./ Page 750 of 1071
`
`Ex.1002
`APPLE INC. / Page 750 of 1071
`
`

`

`Wed QURAN L468
`
`PCTS20102 FHS
`
`isG2304] Nawhing that has been ated or iilustisted is intended or shuuld be iderprated to
`sausé adedicatinn of any component, sieg, feature, obec! benait, advantage car equivaltal t%
`
`the public, regardless ofwhether it igvecded in dhe clainyy.
`
`[803368] Tho acope efproiedtian is Nimited salebybythe claims. That scope is htendedand
`
`should beinterpreted ic be as broad ag ie edngiatent with the axdinary meaning of the language
`that is ased in che claves wher imerpretad In ight af ibs spveilieation and the prosecution
`
`Hatory thar falliows and io encompass sl structural and functional equivalents.
`
`Ex.1002
`APPLEINC./ Page 751 of 1071
`
`Ex.1002
`APPLE INC. / Page 751 of 1071
`
`

`

`WEP 201 GST
`
`CTUNR7880
`
`CLALoe
`
`What is claimed is:
`
`{. Agvoudule cormprisin
`
`a substrates
`
`& processor wut casasabstrata, whoreht said processor uri, compwises a first cache
`
`memory chip ovir said substrate and a processar chip over said firet-cache mmemary chip,
`
`wherein sekdipet cache memory clip in connected to said processor chip through « plurality o
`
`
`
`suicrobumps betwee: gaid firat cache mermuny Chap and seid procesuer
`behveer a neighboring two of said Muralily afnuerobunigs 6 srealler than 60 nkcronieters:
`
`chip, wherein a
`
`@ BhSs Storage wn sald substrate, wherein sd suas Siorage comprises] frat memory chin
`
`over said audbetraiccaid a second momarg chips over said first anerory clip. wherein said Aret
`x
`%
`ihrauidy st {east cne fret wireboncded
`meniay chip is somnecied iy saad second memory chip t
`
`we:
`
`@. weain momory on sald substrate, whereit said mein yhemory complees = flirt
`
`dynancvandamedrcessmemory
`
`chip
`
`dyer
`
`accom
`sak
`.
`4
`w
`dynadiit-raadem-aceessmcinary chip over said 1
`
`si dynami¢-rindom-doceas-mmemery chip:
`
`substrate
`
`amd
`
`oo
`
`and
`
`gonhector connectedf said substrate:
`
`2. Thessodileafclain {wherein the nendaleds implamnentead ina comprter,.a mobile phoma,
`
`acmobile compauphone, « camer. an dectronic book, a dightal pictire frame: an automobile
`
`sleetranic nroduet, a 2D video dishey a 31 talevision, & 3D aidoo game player, a prsiector, or
`
`a server used for chad computing:
`
`a. Vhe mrouhde of chim J, owhorcur saul processor chiy composes a cangal-procassime-tuut
`cywepit bluck designed “by sBG archivegturé or ty nom x84 architectures
`
`G’PU)
`
`graphics-prnceusingsundt
`
`TOPO)
`
`circu
`
`block,
`
`«
`
`baeeband
`
`chewh block,
`
`digthl-si@nealborocessing (DS) ciread. block, or aavireloss local area network ONLANG oigcudt
`
`bok,
`
`any
`
`Ex.1002
`APPLEINC./ Page 752 of 1071
`
`Ex.1002
`APPLE INC. / Page 752 of 1071
`
`

`

`WEP 201 GST
`
`CTUNR7880
`
`*
`4. The modufe of claim 1 wherein seid nrocesscr ship oompriags a central-procesainginit
`
`CPUS chin designed by x84 architecture or by non ABS wehtiecares,
`
`3. The mobs of chem 1. whercit sail processor chip oeruprines..« syeic ram éhip (SOC)
`cuntrismg @ bacabend Circablock, 8 wide dice! ufos metwork (WLAN) aiscutt binck and 3
`
`ocniral-praccssimg-uie, GOPL cimsud Bloch designad by s8G avchdenture ar by aoa «NG
`BPChHOChures, bul not conigreing anyeraphios-pracessing-un iCOP) emount block.
`
`& Vie miaigie of clam 1, wherent Said
`
`first
`
`cache
`
`Uynaniic-raidom-agcean-neraory
`
`(ORAM)
`
`sypchronous-dyaspucrandoneaccess -pepory
`
`PSORAN
`
`
`
`cing,
`
`<liyy,
`
`or
`
`a
`
`g
`
`statepandoim-seress-memeary (SRAM} chips,
`
`ce
`Y. Vievwmodule of chin (, wherein sak firet cache siomory chip hes a senuiry sie: between
`
`TO megubytes amb 32 gioabvtes:
`
`The module afelm 1 wherein sand first cache memory chin we conageted to sakl sahstraie
`
`through at loget.one scound wirebondad wire,
`
` cache piamiory chip comprises a silicon sukatrato,
`
`a plenty of dirgiugh-sdigon vias in sald eihoon sebstrate, a bodescheme at @ backsale a
`£
`“
`
`OW sidhotrate and iesakl plandstyof dirough-aiioan ving, a fist dinlecinic Laver overa
`
`fay side of said silioon substrate. a frat piatal laver over said first dislectric layer. a scound
`
`dielectric Jayer over said Tirst metal
`
`
`laver.@ secomd. metal layer averssaul sccond dic
`
`lever, and a passivation layor over said ton skle of said sihcon subsinas, over said fret and
`
`avedsad delgetric keyors and over said first aad second pial lagers, wherein gach ofpluraley
`
`ofopenings in saidpassivationsaverWA Overkksespectveoneofaphiralit
`Hurabty of cantect ponds teat hoonof ani pheality of Senicrabumes is comeciad to said plorality af contact paynis
`
`-of.contact porta of
`
`has. whoreht said tsstiom schorme cotnywists: « motel benip
`between said aticon.auhetraic and suid substrate, wherein said flret ceehe memory chig 1s
`commected to said auhutrate thaiwek sand pistel inenp
`
`aya
`
`Ex.1002
`APPLEINC./ Page 753 of 1071
`
`Ex.1002
`APPLE INC. / Page 753 of 1071
`
`

`

`WEP 201 GST
`
`CTUNR7880
`
`10. Vie modide ofclain L, whareit wud first mentarychip comprises « Hashumemory chip.4
`
`chynamicrandon-aressmemory (ORANG chin,
`
`11. The modde ef claim }, wherein sail pruceasur wilt Barter cumprince -@ sedeanel cache
`
`ein owherpar said seoond cache ragowiry chipconneeted
`
`12, The mode of chim 1, ywhercsad sccend memory clip hac areht parton dverhangine:
`sakd dirst memory chig, and sail firet momory chip hes a led portion no
`
`gecond momary chap, wherein said second qiomory chis hus adit sidewall rong
`
`nN
`
`afsaid frst morary ois,
`
` & radio Pequency.ck
`
`ta. SHe moduleofclaim 1 wherein said firet dhyaancorandonmbacesse-meniory Chip oomyrises
`
`
`a tint gHicowanhsirats, a dest disteetrio layer aver sed flint silicon aubstrade, atust motel lage
`
`sever Said Tirst digleciric layer, asecond dishoeicic eer aver suid fii sel layer, a sacar]
`s
`motal layer over Soil second disiecirie lover ad a first Gaseivation Inyer over said first abcon
`
`subsinal, over said fret and second sheleotens|
`
`iayers, wherein cach of aqdurality af apeninas oak
`
`found facie
`
`over eragpocine ae of
`
`a phaaliny af contadt points of sad seodnd ndal Tepar aad cakd pheality if contact points 8 af
`
`
`
`Datum af saul phivaltty of ayaaegs, wher gacvnd <ynaiaio-randoinacecss-mn
`x.
`chip comprises & sendand silicon aubsteaic, a plarainy of theowgh-silicon vias bt said second
`
`silicon mubstraic, a botia- scherng a1 & backsxke of sant sceond silicon substrate and in said
`
`piurality Of throughesilicgn vies, a died diskctric layer aver a top side of said sscond silicon
`
`substrate, aibid metal layer over said third dielvetric layer, « fnth dielectree heyer over said
`re
`Hand metal leyer, a fourth eieralleger over said taeth didleainic Jaye ands seoond passivation
`
`layer cover aakddon aide of said second silicon aubatrate, over said third and doarth Helectric
` lavers-and over said duced and |
`wherein said bottom: scheme
`
`métah
`
`humo
`
` béfeden
`
`suid
`
` sonond
`
`aitoun
`
`Subeiraic
`
`aad
`
`dynam is-random-aeciss-mnemory clip, whereis said metal home bb commadtied a7 dad Of said
`¥
`plerahiy af contact poms through oss af seid plerality of-ccpenings, wherei sad sbcond
`
`AQ
`
`Ex.1002
`APPLEINC./ Page 754 of 1071
`
`Ex.1002
`APPLE INC. / Page 754 of 1071
`
`

`

`WEP 201 GST
`
`CTUNR7880
`
`chnamksrandoapaccsssonary
`
`ship
`
`38
`
`z
`eomeccesd
`
`i
`
`said
`
`feat
`
`dynam k-random-socossmnemary ohip throueh seid rieial barny
`
` {s.-
`slayer,a display, or a toloviaken
`
`. whereip gail connector is -yead Tor cinpecthigto s charger, a geEe
`
`1é& The -omdule of claim 1, whe
`
`jcumbeersal serial bus (USBI fighatefiniiian maimed
`
`CORRECT,
`
`iP. Thernoduleafclabn L whercin seid diet cache menmary chip comprises a first nial pad, 3
`
`second metal pad. @ istingIpterfaee circalt having a flest node connected to-said first metal
`pad,a first interchip Dudlér connected t) said first rocial pad aud iG said-flest node of geldcy
`
`f tende cornedied tO @ second sade of
`twahhe inerikce chow, an of-ohip butler having a fi
`
`sabl tegting: bverface circuit and a asoand sade commocied fo subi scoond oietal ped and. ay
`
`afechin elective siatic slischarge (ESDbcireult comecied to said sceand sudeof sand off-chip
`
`baler and fo suid second metal pad, wherein one Gf saul ploraliy of raktrobanps ia on said
`
`first- metal pad, whorent Saul one of said plaruliiy of micriininips is cunbectel
`
`iferebhy baller and ty saul Hirst node of said isting interface cimathrough ead firs reetel
`&
`ped, whorin said socond octal pad Js mat connected upwanis to sak processor wip through
`i
`any onicrobamp between said firshoxchsecmry clip ara 6
`
`.Theonoduls of glean 1%, wher mm sad olfohin be
` and sakl diest otesohip buffer comprises & second N
`x}
`physical chansel-width iv a physical channel Jeseth of cid
`
`
`than a ratio of a ahivsical channel widtly i: a physical channel leseth of seid sccond NMOS
` + bY more than 3 tenes.
`
`The module of claim TP, wherein said procossar chin comprises «third mortal pad anal a
`
`Rucrchip butler camectial te said third metal pad wherein said one af said Sluralgyof
`
` 4
`
`miktvobtange@ is-bebeadn said firat-and third metal pads, wherein sald aos of sakt phvality of
`
`avcrabdimps i comnectsd ah Said second interchip. buffer daeagh sari third metal pad,
`
`wherein said fast inwrchin bolfer & cosnected de sakd secund interehip budfer through. i
`
`Ex.1002
`APPLEINC./ Page 755 of 1071
`
`Ex.1002
`APPLE INC. / Page 755 of 1071
`
`

`

`We? 2URT LAGS?
`
`BOT
`
`
`SEVERTERE
`
`
`aid phirality of microbamps, asad said third metal
`sequined, said Hirst ietal pad, sald onc of
`
`
`
`Oe
`
`rodule of cldim 2O, wheren there 18 no electra static decherve
`SD) eimnait
`
`
`cosnediad inipath bowach said fest interchin buffer and said secomd interciip buffer
`
`Ex.1002
`APPLEINC./ Page 756 of 1071
`
`Ex.1002
`APPLE INC. / Page 756 of 1071
`
`

`

`WO) 20 HYTLEGS7
`
`PCTAUSNEGA886
`
`AMENDED CLAIMS
`received by ite Internationa) Bureau an TO dub 2G9D 710 OF SOREeo
`
`What is eluimed ist
`
`i,
`
`(Currently Amended) A clip package cosaprising:
`a first chin:
`a second chip vertivally over ssid first chip, whereinsaidsecond chip commrises 9 silicon
`substrate aid a mictal
`intercmimect in a through-siioon vis passing through said ailicon
`smibatrate:
`
`a est metal bump between said first and second chips, wherein a inaf¥er of said. socond
`chip ie comnected to a boffer of said flat chip through said first metal bum, wherein an
`ouiput Capacitance aconfrom said buffer ofsaid saoand chip is emailer than 2 pFs and
`& second metal bump hefween said Hirst and sscomf chips, wherein said metal
`intetconnentis connected i said first chip throughsaid second mefal bump.
`
`4. {irmrently Amended) The chip package of claim 1 further comprislie an iederSil
`between said. first and second chips, whereitt sald wnderfill encloses said first and second
`sista! buaps.
`
`(Currenty Amended} The chips paxkage of claim 1 further comprising « thin’ chip
`3.
`‘vertically over said seoond chip, anda third netal Sump berwaer self second and diird chips,
`wherein said third chip is comiected to said mets! intercommect through said third metal
`buna.
`
`‘The chip package of clsiex J finther comprising an wudedtill
`4. {Currently Amended}
`betweedsaid esoomd and third chips, wherein sald? anderfill encloses sald thitd metal burp,
`
`S. {Currently Amended) The chip package of claim 3, wherein ssid thind metal bom
`comprises a first nickel layer, a second nickellayer and a Haccontaining layer horweon said
`fest and second nickel levers.
`
`§, {Currently Amended) The chip packageof Gaim 4, wherein said first nickel layer has 9
`thickness between 2 ard 20) micrometers.
`
`Avs
`
`AMENDED SHEET (ARTICLE 79}
`
`Ex.1002
`APPLEINC./ Page 757 of 1071
`
`Ex.1002
`APPLE INC. / Page 757 of 1071
`
`

`

`WO QOHYELON?
`
`PITTS USDG TRAE TING
`
`3. Qherently Amended) The chip package of claim S$, .wherein asid first aickel layer has a
`thickness hetween 2 and 20 yaicrometers, and said second nickel layer hay a thickness
`
`Renvedn 2 anid 2h micentioiers,
`
`&.
`
`(Currently Amendal) Thechip package of clabn 1, wherain said butler of sald second
`
`chip comprises. driver, and acid Sulfer of said frat chip commrises a receiver,
`
`8. Currently Amemiod) The chip packese of'claim i, wharcin seid buller of sald ssoond
`chip comprises a tri-state buffer, ancl oxid butter of saidfirst chip comprises. anuther tistais
`udfer,
`
`10,ementy Amended) The ohis peckage of claim 1, wherein said metal inferconmoct
`
`cornprises a-onpper layer imsald throughsilicon Va.
`
`tb. (Oerently Amended) The chip package of claim 10, whereik said mictal interconnect
`
`further eormprivesa titaaitim-containing beyerin saidthrowgh-silicon vis, at a sidewall of said
`
`throuvh-sfficon via and bebween sald copper layer and aaid silicon auhetrete.
`
`Le. (Cosrenthy Amended) The chip packaze of claim 1, when aaid aecond chip compriges. a
`metal layer under said alicon substtste, wherein sald through-silicon wa is aver a sotiact
`
`point of said oetel layer, ard sald comiact polmtia ata Bolom of said fhroughallican vic,
`
`wherein onid nistal Gvferconiert
`
`ie fiethar on sald contact gaint and over sald Siieun
`
`substrate.
`
`13. (Ounently Amendad) The chip package of claim 1, wherein said feet metal bomp
`comprises A Ha-conteining layer hetwess sand fir