(19) United States
`(12) Patent Application Publication (10) Pub. No.: US 2004/0174152 A1
`Hwang et al.
`(43) Pub. Date:
`Sep. 9, 2004
`
`US 2004O174152A1
`
`(54) PULSE-SKIPPING SWITCHING POWER
`CONVERTER
`(76) Inventors: Jeffrey H. Hwang, Saratoga, CA (US);
`Joe Wong, Daly City, CA (US)
`Correspondence Address:
`CHAMPION MICROELECTRONIC
`CORPORATION
`HSINCHU SCIENCE- BASED INDUSTRIAL
`PARK
`5F, No. 11, PARKAVENUE II
`HSINCHU CITY (TW)
`(21) Appl. No.:
`10/379,882
`(22) Filed:
`Mar. 4, 2003
`Publication Classification
`
`(51) Int. Cl. .................................................... G05F 1/40
`
`(52) U.S. Cl. .............................................................. 323/284
`
`(57)
`
`ABSTRACT
`
`The invention relates to a pulse-skipping power converter. In
`one aspect, a power converter has two Stages. When the load
`is high, both Stages are enabled. AS the load decreases, one
`or both of the Stages may enter pulse-skipping mode to
`improve efficiency. AS the load is reduced further, the one or
`both of the stages may be disabled. When both stages are
`disabled, an auxiliary power Supply may be enabled. In a
`further aspect, an error Signal is produced by comparing a
`Signal representative of an output voltage or current of the
`power converter relative to a level. A pulse-width modula
`tion (PWM) signal including a series of pulses is produced
`by comparing the error Signal to a ramp signal. The duty
`cycle of the PWM signal is compared to a reference duty
`cycle. If the duty cycle of the PWM signal is less then the
`reference duty cycle then the next pulse in the PWM signal
`is skipped.
`
`Stage 2
`Enters LOW
`
`
`
`Stage 1
`EnterS LOW
`Power Mode
`
`Region 2
`LOW Power
`
`Region 1
`Normal Operation
`
`20%
`Region 3
`Stand-by
`
`% of Max Load
`
`Samsung, EX1006, p. 1
`
`

`

`Patent Application Publication Sep. 9, 2004 Sheet 1 of 6
`
`US 2004/0174152 A1
`
`
`
`
`
`
`
`
`
`i
`:
`
`:
`
`
`
`Linear
`Converter
`(optional)
`1 O1
`
`-
`
`Controller
`is
`
`D
`
`Stage 1
`POWer Factor
`Correction
`102
`
`Stage 2
`Pulse Width
`Modulation
`103
`
`- -
`
`Stage 2
`Enters LOW
`POWer Mod
`
`
`
`Stage 1
`Enters Low F G 1
`POWer Mode
`
`Region 2
`Low Power ||
`
`Region 1
`Normal Operation
`
`Region 3
`Stand-by
`
`% of Max Load
`
`FIG. 2
`
`Samsung, EX1006, p. 2
`
`

`

`Patent Application Publication Sep. 9, 2004 Sheet 2 of 6
`
`US 2004/0174152 A1
`
`
`
`Controller
`306
`
`Load
`
`104
`
`-
`
`LOW POWer
`Detector H
`308
`
`
`
`s Vout
`
`--
`
`KO
`
`C2
`
`e
`
`Linear
`
`8--------- >Converter-
`|
`PWMSense
`
`| st
`PWM
`Controler
`I--------
`310
`...d...:311)
`--------------------------------------------------------- 2 - PWMdisable
`FIG. 3
`
`- - - - - -
`
`Samsung, EX1006, p. 3
`
`

`

`Patent Application Publication Sep. 9, 2004 Sheet 3 of 6
`
`US 2004/0174152 A1
`
`50% CLK
`
`408) —- PWMout
`:
`
`Vref
`
`PWMSense
`
`---------------------- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ----------------------- - - - - - - - -------------------------------
`
`PFCdisable
`
`PFCerror
`
`
`
`PWMisable
`
`PFCerror
`FIG. 6
`
`PFCCdisable
`
`Samsung, EX1006, p. 4
`
`

`

`Patent Application Publication Sep. 9, 2004 Sheet 4 of 6
`
`US 2004/0174152 A1
`
`
`
`Ramp - PWMerror
`
`- WSWO
`
`- 6% CLK
`
`Smaller
`
`bigger
`
`bigger
`
`Smaller
`
`Smaller
`
`O
`
`skip
`
`skip
`
`O
`
`O
`
`FIG. 7B
`
`
`
`
`
`
`
`Samsung, EX1006, p. 5
`
`

`

`Patent Application Publication Sep. 9, 2004 Sheet 5 of 6
`
`US 2004/0174152 A1
`
`
`
`PWMerror
`
`WSWO
`
`FIG. 8B
`
`
`
`
`
`FIG. 8C
`
`- 6% CLK
`
`Smaller
`
`bigger
`
`bigger
`
`O
`Skip
`
`skip
`next
`
`O
`skip
`
`W
`
`O
`skip
`
`O
`skip
`
`O
`skip
`
`FIG. 8D
`
`
`
`- PWMOut
`
`Samsung, EX1006, p. 6
`
`

`

`Patent Application Publication Sep. 9, 2004 Sheet 6 of 6
`
`US 2004/0174152 A1
`
`R7
`
`6% CLK
`
`
`
`FIG. 9
`
`FIG 1 OB
`
`- 6% CLK
`
`FIG 1 OC
`
`Samsung, EX1006, p. 7
`
`

`

`US 2004/0174152 A1
`
`Sep. 9, 2004
`
`PULSE-SKIPPING SWITCHING POWER
`CONVERTER
`
`FIELD OF THE INVENTION
`0001. The present invention relates to the field of Switch
`ing power converters. More particularly, the present inven
`tion relates to the control circuitry for power converters with
`high efficiency while under light loads.
`
`DESCRIPTION OF THE RELATED ART
`0002 A Switching power converter is a device that con
`verts an input signal with one power form factor into an
`output signal with a different power form factor. A Switching
`power converter typically includes a Switch, a reactive
`element, a controller, and a Sensor. The Sensor feeds a signal
`into the controller. The controller modulates the input Signal
`by opening and closing the Switch in an attempt to make the
`Sensor Signal match a reference Signal. The reactive element
`filters the modulated input signal producing a relatively
`constant output signal.
`0003) A typical Switch in a Switching power converter
`may be modulated by a Pulse Width Modulation (PWM)
`signal or a Pulse Frequency Modulation (PFM) signal. A
`PWM signal has a constant frequency and an adjustable duty
`cycle. A PFM signal has a constant duty cycle and an
`adjustable frequency. A typical goal for a power converter is
`to regulate the output Voltage independent of changes in the
`load or the input voltage. A power converter may do this by
`measuring an output voltage of the power converter, com
`paring the output voltage to a reference Voltage, and adjust
`ing the duty cycle of the PWM signal or the frequency of the
`PFM signal to compensate for any discrepancy between the
`desired output Voltage and the measured output voltage.
`0004. A typical Switching power converter can be a
`highly efficient device under heavy and medium loads.
`However, under light loads, a typical Switching power
`converter is often inefficient. One source of this inefficiency
`Stems from the parasitic capacitance and resistance of the
`Switch. One way to increase the efficiency of the power
`converter is to minimize the use of the Switch.
`0005 What is needed is an improved technique for
`pulse-skipping in a Switching power converter. It is to these
`ends that the present invention is directed.
`
`BRIEF SUMMARY OF THE INVENTION
`0006 The invention relates to a pulse-skipping power
`converter. In one aspect, a power converter has two stages.
`When the load is high, both stages are enabled. As the power
`load decreases, one or both of the Stages may enter pulse
`skipping mode to improve efficiency of the power converter.
`As the load power is reduced even further, the one or both
`of the stages may be disabled. When both stages are dis
`abled, an auxiliary power Supply (e.g., a linear converter)
`may be enabled. Disabling one or more of the Stages during
`periods of low power consumption is expected to improve
`the efficiency of the converter.
`0007. In a further aspect of the invention, an error signal
`is produced by monitoring a signal representative of an
`output voltage or an output current of the power converter
`relative to a reference level. A pulse-width modulation
`(PWM) signal including a series of pulses is produced by
`
`comparing the error Signal to a ramp signal. The duty cycle
`of the PWM signal is compared to a reference duty cycle. If
`the duty cycle of the PWM signal is less then the reference
`duty cycle then the next pulse in the PWM signal is skipped.
`These and other aspects of the invention are described in
`more detail herein.
`
`BRIEF DESCRIPTION OF DRAWINGS
`0008 FIG. 1 illustrates a block diagram of a two-stage
`power converter in accordance with an aspect of the present
`invention;
`0009 FIG. 2 illustrates the various regions of operation
`for the two-stage power converter shown in FIG. 1A;
`0010 FIG. 3 illustrates a schematic block diagram of an
`embodiment of a two-stage pulse-skipping power converter;
`0011 FIG. 4 illustrates a schematic block diagram of an
`embodiment of a control circuit for a pulse-skipping PWM
`power converter;
`0012 FIGS. 5-6 illustrate schematic block diagrams of
`embodiments of low power detectors for use in two-stage
`pulse-skipping power converters,
`0013 FIGS. 7A-D illustrate leading edge timing dia
`grams for an embodiment of a pulse-skipping power con
`Verter,
`0014 FIGS. 8A-D illustrate trailing edge timing dia
`grams for an embodiment of a pulse-skipping power con
`Verter,
`0015 FIG. 9 illustrates a schematic block diagram of an
`embodiment of a circuit for producing a clock Single with an
`adjustable duty cycle;
`0016 FIG. 10A illustrates a ramp signal that may be used
`in an embodiment of the current invention;
`0017 FIG. 10B illustrates a CLK signal with an adjust
`able duty cycle, that may be used in an embodiment of the
`present invention, the period of the CLK is identical to the
`period of the ramp signal, the falling edge of the CLKSignal
`may be Synchronized to the falling edge of the ramp signal;
`and
`0018 FIG. 10C illustrates an inverted CLK signal with
`an adjustable duty cycle, that may be used in an embodiment
`of the present invention, the period of the inverted CLK is
`identical to the period of the ramp signal, the rising edge of
`the inverted CLK Signal may be Synchronized to the falling
`edge of the ramp signal.
`
`DETAILED DESCRIPTION OF A PREFERRED
`EMBODIMENT
`0019 FIG. 1 illustrates a block diagram of a two-stage
`power converter 100 in accordance with an aspect of the
`present invention. An AC input Signal is coupled to a power
`factor correction (PFC) stage 102 and an optional linear
`converter 101. The PFC stage 102 forces the input current to
`be Substantially proportional to the input voltage, while
`providing a Substantially constant intermediate DC output
`voltage. The intermediate DC output voltage of the PFC
`stage 102 may be coupled into a PWM stage 103, which
`produces a regulated output. The output of the PWM stage
`103 and an output of the optional linear converter 101 may
`
`Samsung, EX1006, p. 8
`
`

`

`US 2004/0174152 A1
`
`Sep. 9, 2004
`
`be coupled to a load 104. A controller 105 may be coupled
`to the PFC stage 102, the PWM stage 103, the load 104, and
`the optional linear converter 101.
`0020 Thus, the two-stage power converter 100 may be
`an AC-DC converter in which the first stage 102 may
`provide power factor correction (PFC), while the second
`Stage 103 may provide output voltage regulation. ASSuming
`the input voltage has a sinusoidal waveform, the PFC Stage
`102 forces the input current substantially into a sinusoidal
`waveform in phase with the input Voltage.
`0021. The controller 105 may sense a signal that is
`representative of the Voltage or current delivered to the load
`104. Using this Sensed signal and by controlling a Switch in
`PWM stage 103, the controller 105 attempts to maintain a
`constant output voltage or current. The controller 105 may
`Sense Signals that are representative of an input voltage, an
`input current, an intermediate output voltage of the PFC
`stage 102; and an output voltage of the PWM stage 103. The
`controller 105 attempts to maintain a constant output voltage
`and to insure that the input current is proportional to the
`input voltage, thereby providing power factor correction.
`The controller 105 may sense a signal from the load 104 that
`indicates the level of the power drawn by the load 104. A
`standby signal from the load 104 may instruct the controller
`105 to enter standby mode. For example, where the load 104
`is a microprocessor or controller, it may enter a Standby or
`“sleep” mode during periods of low activity for power
`conservation. While in standby mode, the controller 105
`may disable the PFC stage 102. Also, while in standby
`mode, the controller 105 may cause PWM stage 103 to enter
`pulse-skipping mode or alternatively may disable the PWM
`stage 103 and enable the optional linear converter 101.
`0022. During low power conditions, pulse-skipping
`mode may be entered in both Stages. Twenty percent of a
`maximum expected load is a preferred level below which
`pulse-skipping may be enabled, although other levels may
`be used. It is expected that output regulation will be mini
`mally affected during pulse-skipping.
`0023. During standby conditions, the first stage 102 may
`be disabled while the second stage 103 may remain in
`pulse-skipping mode. In an alternate embodiment, both
`Stages may be disabled during Standby, and the auxiliary
`power Supply 101 may be enabled. The power converter 100
`may enter standby mode below approximately 0.5–1% of
`maximum load, although other boundary points may be
`used. It is expected that output and/or input regulation will
`be minimally affected during Standby.
`0024 FIG. 2 illustrates a graph that shows modes of
`operation for the two-stage power converter shown in FIG.
`1. The graph ShowS efficiency verSuS percentage of maxi
`mum expected power drawn by the load. The graph may be
`divided into approximately three regions. In a first region,
`Region 1, normal operation occurs. Region 1 may be entered
`at times when the load power is above approximately 20%
`of its maximum. In Region 1, the first stage 102 and the
`Second Stage 103 may be actively Switching. Region 2 may
`be a low power region and may be entered when the load
`power is between approximately 0.5-1% and approximately
`20% of maximum. As shown in FIG. 2, the first stage 102
`and the second stage 103 may enter Region 2 at different
`levels of load power. For example, the first stage 102 may
`enter Region 2 at a higher load power level than the Second
`
`Stage 103; alternately, the Second Stage 102 may enter
`Region 2 at a higher level. In Region 2, both Stages maybe
`operating in a pulse-skipping mode. Region 3 may be a
`Standby region and may be entered when the load power is
`below 0.5–1% of its maximum expected load power. In
`Region 3, the first stage 102 may be disabled, while the
`Second Stage 103 may be in its pulse-skipping mode. In an
`alternate embodiment of the present invention, the first Stage
`102 and the second stage 103 may be disabled and the
`auxiliary linear converter 101 may be enabled. The follow
`ing tables Summarize the descriptions given above. More
`particularly, Table 1 summarizes the first embodiment
`described above in which the second stage 103 is in its
`pulse-skipping mode in Region3, while Table 2 Summarizes
`the alternate embodiment described above in which the
`second stage 103 is disabled in Region 3.
`
`TABLE 1.
`
`Region 1
`On
`On
`
`Region 2
`Pulse-skipping
`Pulse-skipping
`
`Region 3
`Off
`Pulse-skipping
`
`PFC Stage 1
`PWM Stage 2
`
`0025)
`
`TABLE 2
`
`Region 1
`
`Region 2
`
`Region 3
`
`PFC Stage 1
`PWM Stage 2
`
`On
`On
`
`Pulse-skipping
`Pulse-skipping
`
`Off
`Off
`
`0026 FIG. 3 illustrates an embodiment of the power
`converter 100 of FIG. 1 in accordance with an aspect of the
`present invention. The converter of FIG. 3 converts an AC
`input Signal into an output voltage acroSS the load 104. The
`controller shown in FIG. 1 may include a PFC controller
`306, a logic AND gate 307, a low power detector 308, a
`PWM controller 310, and a logic AND gate 311.
`0027. The PFC stage 102 may include a full wave bridge
`rectifier 305, an inductor L1, a diode D1, a Switch SW1, a
`capacitor C1, and resistors R1, R2 and R3. The AC input
`signal may be coupled to input terminals of the rectifier 305.
`A first output terminal of the rectifier 305 may be coupled to
`a first node of the inductor L1 for delivering the input current
`and to the PFC controller 306 for delivering a signal Vsense
`that is representative of the input Voltage. A Second output
`terminal of the rectifier 305 may be coupled to a first node
`of the resistor R3 and to the PFC controller 306 for deliv
`ering a signal Isense that is representative of the input
`current though the inductor L1. A Second node of the resistor
`R3 may be coupled to a ground node. A Second node of the
`inductor L1 may be coupled to a first node of a Switch SW1
`and an anode of a diode D1. A cathode of the diode D1 may
`be coupled to a first node of a capacitor C1 and to a first node
`of resistor R1. A DC intermediate voltage (e.g., 380v)
`formed at the first node of the capacitor C1 may be fed into
`the second PWM stage 103. A second node of the resistor R1
`may be coupled to a first node of a resistor R2, and to the
`PFC controller 306 for delivering a signal PFCsense that is
`representative of the DC intermediate Voltage. A Second
`node of the Switch SW1, a second node of the capacitor C1,
`and a Second node of the resistor R2 may be coupled to a
`ground node.
`
`Samsung, EX1006, p. 9
`
`

`

`US 2004/0174152 A1
`
`Sep. 9, 2004
`
`0028. The rectifier 305 may convert a bipolar AC input
`Signal into a unipolar Signal. The Signals PFCsense, Vsense,
`and Isense may be coupled into the PFC controller 306. The
`PFC controller 306 may cause the switch SW1 to be
`Switched on/off in an attempt to cause the AC input current
`to be Substantially proportional to the AC input voltage, and
`the intermediate output voltage of the PFC stage 102 to
`remain Substantially constant. The inductor L1 and the
`capacitor C1 act as a filter to reduce ripple in the interme
`diate output Voltage.
`0029. The PWM stage 103 may include an inductor L2,
`a diode D2, a Switch SW2, a capacitor C2, and resistors R4
`and R5. The intermediate output voltage of the PFC stage
`102 may be coupled to a first node of the inductor L2. A
`Second node of the inductor L2 may be coupled to a first
`node of a Switch SW2 and to an anode of the diode D2. A
`cathode of the diode D2 may be coupled to a first node of the
`capacitor C2 and to a first node of the resistor R4. An output
`voltage Vout for powering the load 104 may be formed
`acroSS the capacitor C2. A Second node of the resistor R4
`may be coupled to a first node of a resistor R5, and to the
`PWM controller 310 for delivering a signal PWMsense that
`is representative of the output voltage Vout. A Second node
`of the Switch SW2, a second node of the capacitor C2, and
`a Second node of the resistor R4 may be coupled to a ground
`node.
`0030 The signal PWMsense, representative of the output
`voltage Vout of the PWM stage 103 may be coupled into the
`PWM controller 310. The PWM controller 310 may cause
`the Switch SW2 to be switched on and off in an attempt to
`cause the output Voltage Vout to remain Substantially con
`Stant. The inductor L2 and the capacitor C2 act as a filter to
`reduce the ripple in the output voltage Vout.
`0031. The load 104 may be a smart load in that it may
`instruct the controller 105 to enter a standby mode. For
`example, the load 104 may include a microprocessor that
`may enter a Standby mode during periods of low activity or
`non-use. The load 104 may send a Standby Signal that may
`be interpreted by a low power detector 308. The low power
`detector 308 is thus able to implement the aspects of the
`invention shown in Region 3 of Table 1 and Table 2. The low
`power detector 308 may be coupled to the optional linear
`converter 101, an optional AND gate 311, and an AND gate
`307. When the low power detector 308 is instructed to enter
`standby mode by the load 104, it may send a digital low
`signal to the AND gate 307, thus disabling Switching in the
`PFC stage 102. The low power detector 308 may also send
`a digital low signal to the optional AND gate 311, thus
`disabling the PWM stage 103, while enabling the optional
`linear converter 101. Alternatively, the linear converter 101,
`and the AND gate 311 may be omitted, in which case, the
`PWM stage 103 may not be disabled.
`0032 FIG. 4 illustrates an embodiment of the PWM
`controller 310 in accordance with an aspect of the present
`invention. The controller 310 may include a differential
`amplifier 401, a comparator 403, AND gates 404, 406 and
`408, and flip-flops 405 and 407. The signal PWMsense that
`is representative of the output voltage Vout may be coupled
`to a non-inverting input of a differential amplifier 401.
`Alternately, to regulate the output current, a signal repre
`sentative of the output current delivered to the load 104 may
`be coupled to the non-inverting input of the differential
`amplifier 401.
`
`0033. A reference voltage Vref representative of the
`desired level for the output voltage Vout may be coupled to
`an inverting input of the differential amplifier 401. The
`output of the differential amplifier 401 may form an error
`signal PWMerror. The error signal PWMerror may be rep
`resentative of a difference between the output voltage Vout
`and a desired level for the output voltage; as represented by
`the reference signal Vref. Alternately, PWMerror may be
`representative of a difference between any signal that is
`coupled into the inverting input of the differential amplifier
`401 and any reference signal Vref. The controller 310 will
`attempt to minimize PWMerror. The signal PWMerror is
`shown in FIG. 7A.
`0034) Referring to FIG. 4, the error signal PWMerror
`may be coupled to an inverting input of the comparator 403.
`An oscillator 402 may produce a ramp signal, Ramp, which
`is also shown in FIG. 7A. The ramp signal Ramp may be
`coupled to a non-inverting input of the comparator 403. The
`output of the comparator 403 may form a PWM signal
`Vsw0, which is shown in FIG. 7B. The PWM signal Vsw0
`is formed by comparing the signals Ramp and PWMerror;
`the PWM signal Vsw0 may be a logical high voltage when
`the Signal PWMerror is greater then the ramp signal, Ramp,
`and may be a logical low voltage when the signal PWMerror
`is lower then the ramp signal, Ramp. Thus, the duty cycle of
`the PWM signal VSw0 changes in response to the error
`signal PWMerror. The duty cycle of the switch SW2 is
`controlled in response to the signal Vsw0.
`0035) The PWM signal Vsw0 may be coupled to a first
`input of an AND gate 404 and to a RESET input of a flip-flop
`407. A clock signal, CLK, that may be synchronized with the
`ramp Signal, Ramp, may be coupled to a Second input of the
`AND gate 404. An output of the AND gate 404 may be
`coupled to a SET input of the flip-flop 405, through a delay
`line 409. A 6% CLK signal may be an inverted clock signal
`with a 6% duty cycle, meaning that the signal is low 6% of
`the time and high the rest of the time, as shown in FIG. 7C.
`While 6% is a preferred duty cycle, it will be apparent that
`another duty cycle may be selected. The 6% CLK signal may
`also be Synchronized with the ramp Signal, Ramp, and may
`be coupled to a RESET input of the flip-flop 405. The output
`of the flip-flop 405 may be coupled to a first input of the
`NAND gate 406. A clock signal 50% CLK, with a duty cycle
`of 50%, which may be Synchronized to the ramp signal, may
`be coupled to a second input of the NAND gate 406. An
`output of the NAND gate 406 may be coupled to a SET input
`of the flip-flop 407 and a first input of an AND gate 408. An
`output of the flip-flop 407 may be inverted and coupled to a
`second input of an AND gate 408. An output of the AND
`gate 408 may be a Switch control signal PWMout shown in
`FIG. 7D which may be used to control the switch SW2. The
`delay line 409 between the AND gate 404 and the flip-flop
`405 synchronizes the first pulse exiting the NAND gate 406
`with the second pulse exiting the comparator 403.
`0036) The controller 310 implements a pulse-skipping
`mode. When the power requirements of the load 104 are low,
`the PWM stage 103 may enter into pulse-skipping mode.
`The controller 310 may determine when the load is light by
`comparing the PWM signal Vsw0 (FIG.7B) to the reference
`signal with a fixed duty cycle (FIG. 7C). When the duty
`cycle of the intermediate PWM signal is less then the duty
`cycle of the reference signal, a next pulse in the PWM signal
`Vsw0 may be skipped as shown in FIG. 7D. The flip-flop
`
`Samsung, EX1006, p. 10
`
`

`

`US 2004/0174152 A1
`
`Sep. 9, 2004
`
`405 and the AND gate 404 may be used to compare the duty
`of cycle of the PWM signal to that of the reference signal.
`The AND gates 406 and 408 and the flip-flop 407 may be
`used to skip the next pulse. Thus, by comparing FIGS. 7B,
`7C and 7D, it can be seen that the signal PWMout in FIG.
`7D follows that of the signal Vsw0 in FIG. 7B, except that
`when a pulse in the signal VSw0 is bigger (i.e. wider) than
`the corresponding pulse in the reference signal of FIG. 7C,
`the next pulse in the signal PWMout is skipped.
`0037 FIG. 5 illustrates a first embodiment of the low
`power detector 308 of FIG. 3, (which is labeled 308a in
`FIG. 5) in accordance with an aspect of the present inven
`tion (represented by Table 1, above). The low power detector
`308a may include an opto-coupler D3, capacitors C3 and
`C4, two resistors R6 & R8, and a comparator 501 that may
`have hysteresis. A voltage Vcc may be coupled to a first node
`of the resistor R8. The standby signal from the load 104 may
`be coupled to an input of the opto-coupler D3. The opto
`coupler D3 provides isolation between the load 104 and the
`detector 308. The opto-coupler D3 may be coupled to a first
`node of the first capacitor C3, to a first node of the second
`capacitor C4a Second node R8, and to an inverting input of
`the comparator 501. A first node of the resistor R6 may be
`coupled to a Second node of the capacitor C4. A Second node
`of the capacitor C3 and a second node of the resistor R6 may
`be coupled to a ground node. The error signal PFCerror may
`also be coupled into the inverting input of the comparator
`501. A reference voltage Ref A may be coupled to the
`non-inverting input of the comparator 501.
`0038. The low power detector 308a disables the PFC
`Stage 102 in response to receiving the Standby Signal from
`the Smart load 104. This is accomplished by the opto-coupler
`D3 pulling the Voltage at the inverting input of the com
`parator 501 below that of Ref A. However, the PWM stage
`may not be disabled in response to the Standby Signal as
`shown in column Region 3 of Table 1 above. The passive
`elements C3, C4 and R6 act as a low pass filter preventing
`noise in the standby signal from disabling the PFC stage
`102. In addition, when the PFCerror signal falls below the
`Signal Ref A, this indicates that the load has entered Region
`2 (FIG. 2) for the PFC stage 102. Accordingly, the PFC
`Stage enters a pulse skipping mode in which pulses in the
`PFCout signal from the controller 306 (FIG.3) are skipped
`so long as the PFCerror signal remains below the level of
`Ref A. The comparator 501 may optionally exhibit hyster
`esis so as to reduce the frequency that the PFC enters and
`exits pulse-skipping mode in the event the PFCerror Signal
`remains near the level of Ref A.
`0039 FIG. 6 illustrates an alternate embodiment of the
`low power detector 308 of FIG.3 (which is labeled 308b in
`FIG. 6) in accordance with another aspect of the present
`invention (represented by Table 2, above). The low power
`detector 308b may include an opto-coupler D3, two capaci
`tors C3 and C4, two resistors R6 and R8, a comparator 603,
`an OR gate 602, and a comparator 501 that may have
`hysteresis. Elements in common with FIG. 5 are given the
`Same reference numeral. A voltage Vcc may be coupled to
`a first node of the resistor R8. The standby signal from the
`Smart load 104 may be coupled to an input of the opto
`coupler D3. The output of the opto-coupler D3 may be
`coupled to a first node of a capacitor C3, a first node of a
`Second capacitor C4, a Second node of a resistor R8 and an
`inverting input of a comparator 603. A first node of a resistor
`
`R6 may be coupled to the capacitor C4. A second node of
`capacitor C3 and a Second node of a resistor R6 may be
`coupled to a ground node. A reference Voltage Ref B may be
`coupled to a non-inverting input of the comparator 603. An
`output of the comparator 603 may be coupled to a first input
`of the OR gate 602, and may form the signal PWMdisable.
`The error signal PFCerror may be coupled into the inverting
`input of the comparator 501. The reference voltage Ref A
`may be coupled to the non-inverting input of the comparator
`501. The output of the comparator 501 may be coupled to a
`second input of the OR gate 602. The OR gate 602 may form
`a signal PFCdisable.
`0040. The passive elements C3, C4 and R6 act as a low
`pass filter preventing noise in the Standby Signal from
`effecting the behavior of the low power detector 308b. The
`comparator 603 compares the filtered Standby signal to Ref
`B. When Ref B is higher then the Standby signal, then
`PWMdisable is high. When Ref B is lower then the Standby
`signal, then PWMdisable is low. The comparator 501 com
`pares PFCerror to Ref A. When the Ref A is higher then the
`PFCerror, then the output of the comparator 501 is high.
`When Ref B is lower then PFCerror then the output of the
`comparator 501 is low. The logic OR gate 602 causes
`PFCdisable to be high whenever either the output of com
`parator 501 is high or PWMdisable is high. Thus, the low
`power detector 308b disables the PFC stage and the PWM
`stage and enables the linear converter 101, whenever the
`detector 308b receives the standby signal from the Smart
`load 104. In addition, the PFC stage 102 skips pulses in the
`signal PFCout when the signal PFCerror is below Ref A.
`0041
`FIGS. 7A-D illustrate leading edge timing dia
`grams of the Significant Signals in controller 310. The time
`scales for FIGS. 7A-D are equivalent. FIG. 7A illustrates a
`timing diagram showing the ramp signal Ramp and the
`PWMerror signal. The ramp signal Ramp as produced by
`oscillator 402 may be compared to the PWMerror signal
`produced by comparator 403 to form the control signal
`VSWO shown in FIG. 7B.
`0042 FIG. 7C illustrates the inverted 6% CLK that the
`signal represented in FIG. 7B may be compared to. The text
`below each pulse States the results of this comparison. The
`first reference pulse is Smaller than the corresponding pulse
`of VSw0, the second is bigger, the third is bigger, the fourth
`is smaller, the fifth is smaller. FIG. 7D illustrates the signal
`PWMout, of a pulse-skipping controller as may be imple
`mented by the present invention. The text above the wave
`form States the action that the controller takes given the
`results of the comparison between the reference Signal of
`FIG. 7C and the PWM signal of FIG. 7B. When the
`reference signal is smaller then the PWM signal then the
`next pulse is not skipped. When the reference Signal is
`bigger then the PWM signal then the next pulse is skipped.
`The text in FIG. 7D illustrates this. For example, the second
`pulse is not skipped because the first reference pulse is
`smaller then the first PWM pulse. In addition, the third pulse
`is skipped because the Second reference pulse is Smaller then
`the second PWM pulse. In addition, the fourth pulse is
`skipped because the third reference pulse is Smaller then the
`third PWM pulse. In addition, the fifth pulse is not skipped
`because the fourth reference pulse is smaller then the fourth
`PWM pulse. In addition, the sixth pulse (not shown) is not
`skipped because the fifth reference pulse is Smaller then the
`fifth PWM pulse.
`
`Samsung, EX1006, p. 11
`
`

`

`US 2004/0174152 A1
`
`Sep. 9, 2004
`
`0.043 AS FIGS. 7A-D illustrate the leading edge timing
`diagrams of the significant signals in controller 310, FIGS.
`8A-D illustrate trailing edge timing diagrams. The time
`scales along FIGS. 8A-D are equivalent. FIG. 8A illustrates
`a timing diagram showing the ramp Signal and the PWMer
`ror Signal. The ramp signal as produced by the Oscillator 402
`may be compared to the PWMerror signal produced by the
`comparator 403. FIG. 8B illustrates a PWM signal that is
`illustrative of what the comparator 403 would produce given
`the signals shown in FIG. 8A. The dashed lines connecting
`FIG. 8A to FIG. 8B show the logical transitions that the
`comparator 403 may produce, given the signals in FIG. 8A
`as inputs. The comparator 403 would produce these results
`if its input were reversed. For example, if the oscillator 402
`was connected to the inverting input of the comparator 403
`and the amplifier 401 was connected to the non-inverting
`input of amplifier 403.
`0044 FIG. 8C illustrates the inverted 6% CLK that the
`signal represented in FIG. 7B may be compared to. The text
`below each pulse States the results of this comparison. The
`first reference pulse is bigger, the Second is Smaller, the third
`is bigger, the fourth is bigger, the fifth is bigger and the Sixth
`is bigger. FIG. 8D illustrates the signal PWMout, of a
`pulse-skipping controller as may be implemented by the
`present invention. The text above the waveform states the
`action that the controller takes given the results of the
`comparison between, the reference signal of FIG. 8C and
`the PWM signal of FIG. 8B. When the reference signal is
`Smaller then the PWM signal then the next pulse is not
`skipped. When the reference signal is bigger then the PWM
`signal then the next pulse is sk