UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`SAMSUNG ELECTRONICS CO., LTD. AND DELL TECHNOLOGIES INC.,
`and ANKER INNOVATIONS LTD.,1
`Petitioners,
`
`v.
`
`MYPAQ HOLDINGS LTD.,
`Patent Owner.
`____________
`
`Case No. IPR2022-00311
`Patent 8,477,514
`____________
`
`REPLY DECLARATION OF DR. SAYFE KIAEI
`
`1 Anker Innovations Ltd. filed a motion for joinder and a petition in IPR2022-
`
`01134 and has been joined as a petitioner in this proceeding.
`
`Samsung/Dell, Exh. 1026, p. 1
`Samsung/Dell v. MYPAQ, IPR2022-00311
`
`
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`SAMSUNG ELECTRONICS CO., LTD. AND DELL TECHNOLOGIES INC.,
`and ANKER INNOVATIONS LTD.,1
`Petitioners,
`
`v.
`
`MYPAQ HOLDINGS LTD.,
`Patent Owner.
`____________
`
`Case No. IPR2022-00311
`Patent 8,477,514
`____________
`
`REPLY DECLARATION OF DR. SAYFE KIAEI
`
`1 Anker Innovations Ltd. filed a motion for joinder and a petition in IPR2022-
`
`01134 and has been joined as a petitioner in this proceeding.
`
`Samsung/Dell, Exh. 1026, p. 1
`Samsung/Dell v. MYPAQ, IPR2022-00311
`
`
`
`I.
`II.
`
`B.
`
`C.
`
`TABLE OF CONTENTS
`INTRODUCTION ........................................................................................... 3
`“SYSTEM OPERATIONAL STATE OF SAID LOAD” (CLAIM 1) ........... 3
`A.
`Patent Owner and its Expert Reply on an Incorrect
`Interpretation of “System Operational State of Said Load” .................. 4
`Chagny’s “Activity Input 202” Signal is a “Signal Indicating a
`System Operational State of Said Load” ............................................... 7
`Hwang’s “Standby Signal” is a “Signal Indicating a System
`Operational State of Said Load”..........................................................10
`“CHARACTERIZING A POWER REQUIREMENT” (CLAIM 6) ............13
`“ENABLE” / “ENABLING” (CLAIMS 11 AND 16) ..................................15
`A.
`Chagny and Hwang Disclose the “Enable” and “Enabling”
`Elements of Claims 11 and 16.............................................................15
`“IN ACCORDANCE WITH” (CLAIMS 2, 7, 12, & 17) .............................19
`A.
`Chagny Discloses the “In Accordance With” Limitation
`Because Duty Cycle Control Depends on Switching Frequency ........20
`VI. MOTIVATION TO COMBINE HWANG AND CHAGNY ..........................23
`VII. CONCLUSION ..............................................................................................28
`
`III.
`IV.
`
`V.
`
`i
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`Samsung/Dell, Exh. 1026, p. 2
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`Declaration of Dr. Sayfe Kiaei
`
`I.
`
`INTRODUCTION
`
`1.
`
`I have been retained by Samsung Electronics Co., Ltd. (“Samsung”)
`
`and Dell Technologies Inc. (“Dell”) as an independent expert consultant in this
`
`proceeding before the United States Patent and Trademark Office (“PTO”).
`
`2.
`
`My compensation is in no way contingent on the nature of my findings,
`
`the presentation of my findings in testimony, or the outcome of this or any other
`
`proceeding. I have no other interest in this proceeding.
`
`3.
`
`I have been asked to consider whether certain references disclose or
`
`suggest features recited in the claims of U.S. Patent No. EX1001 – US8477514B2
`
`(“the ’514 patent”) (EX1001).2 The opinions below supplement those set forth in
`
`my initial declaration (EX1002) in this matter. My qualifications remain the same
`
`as stated in Paragraphs 4-23 of my initial declaration (EX1002) in this matter.
`
`4.
`
`I make this declaration based upon my own personal knowledge and, if
`
`called upon to testify, would testify competently to the matters contained herein.
`
`II.
`
`“SYSTEM OPERATIONAL STATE OF SAID LOAD” (CLAIM 1)
`
`5.
`
`Claim 1 of the ’514 Patent recites, among other elements, “a power
`
`converter controller configured to receive a signal from said load indicating a system
`
`2 Where appropriate, I refer to exhibits that I understand are, or will be, filed in this
`inter partes review (“IPR”) of the ’514 patent.
`
`3
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`Samsung/Dell, Exh. 1026, p. 3
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`operational state of said load and control an internal operating characteristic of said
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`power converter as a function of said signal.” EX1001, claim 1. I understand that
`
`Patent Owner (“PO”) and its expert, Dr. Ferrese, dispute whether Chagny (EX1004)
`
`and Hwang (EX1006) disclose a “system operational state of said load.” Patent
`
`Owner Response (Paper 17) (“POR”) at 18-23 (Chagny grounds), 41-44 (Hwang
`
`grounds); EX2018 (Ferrese Declaration), ¶¶ 50-58 (Chagny grounds), 100-108
`
`(Hwang grounds). As I explain below, it is my opinion that the arguments of Patent
`
`Owner and its expert, Dr. Ferrese, are based on an incorrect interpretation of the
`
`claims.
`
`A.
`
`6.
`
`Patent Owner and its Expert Reply on an Incorrect Interpretation
`of “System Operational State of Said Load”
`
`I understand that Patent Owner states it “interprets all claim terms in
`
`accordance with their ordinary and customary meaning.” POR, 16. However, as I
`
`explain herein, it is my opinion that Patent Owner applies an incorrect interpretation
`
`of the phrase “system operational stat of said load.”
`
`7.
`
`I understand that Patent Owner contends that a “POSITA would
`
`understand that the term ‘system operational state’ as it pertains to engineering
`
`systems, refers to the way in which the system as a whole is being employed or
`
`utilized.” POR, 18; see also EX2018 (Ferrese Declaration), ¶ 51. I understand that
`
`Patent Owner further cites the ’514 Patent at 9:14-27 for examples of “system
`
`operational states,” and then contends that each of these examples “indicates the
`
`4
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`Samsung/Dell, Exh. 1026, p. 4
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`current or future operational state of the load in a particular context, not simply the
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`current activity level of the processor.” POR, 19-20 (emphasis added); see also
`
`EX2018 (Ferrese Declaration), ¶ 52. PO adds that the system operational state is
`
`“driven by various factors, including external requirements, and is ultimately
`
`dependent on the context in which the system is being utilized.” POR, 21 (emphasis
`
`added); see also EX2018 (Ferrese Declaration), ¶ 54. As I explain below, Patent
`
`Owner’s characterization of examples of “system operational states” is incomplete,
`
`and with respect to certain examples, incorrect. Patent Owner’s resulting
`
`interpretation of “system operational state” is also incorrect.
`
`8.
`
`In my opinion, Patent Owner’s requirement of “particular context”
`
`regarding how the system as a whole is being employed or utilized contradicts the
`
`plain language of the claims and also conflicts with examples of system operational
`
`states in the patent specification. First, Patent Owner’s interpretation conflicts with
`
`the plain language of the claim. Claim 1 recites a “a signal indicating a system
`
`operational state of said load.” EX1001, Claim 1. The plain language dictates that
`
`the “system operational state” is a state “of said load.” Thus, in my opinion, there
`
`is no basis for injecting a “particular context” requirement external to the load as
`
`argued by Patent Owner.
`
`9.
`
`Additionally, Patent Owner’s interpretation excludes embodiments
`
`disclosed in the specification. The ’514 Patent discloses examples of a system
`
`5
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`operational state “such as a processor core state.” EX1001, 26:10-11.3 Indeed, in
`
`the background section, the specification describes “system operational states” such
`
`as ACPI “P-states” and “C-states.” Id., 5:19-26. The P-states “describe[] the
`
`‘performance’ state … of the processor as high, medium, or low” (id., 5:27-29), and
`
`the C-states describe “a processor at its full operation level” or at “various levels of
`
`a processor sleep state” (id., 5:46-49). Notably, the P-states and C-states relate to
`
`the operating state of the processor (i.e., the load), rather than a particular context
`
`(e.g., criticality based on time of day) as purported by PO. Id., 5:27-49. Indeed, the
`
`ACPI specification (EX2022), submitted in this proceeding by Patent Owner,
`
`describes C-states as “processer power states” or “processor power consumption and
`
`thermal management states.” EX2022, 38 (Section 2.5). Thus like the ’514 Patent,
`
`3 I understand that Patent Owner argues that a “core state of a processor such as a
`… C-state, indicating, for example, that the system is operating from emergency
`power” indicates a particular context. POR, 19-20 (citing EX1001, 9:11-27)
`(emphasis added). But, Patent Owner’s cited passage is exemplary, not limiting.
`Other portions of the patent specification describe “system operational states” as
`including core states or C-states with no reference to a particular context external to
`the processor (i.e., the load). EX1001, 26:10-11; see also id., 5:19-27, 5:44-59.
`Thus, a POSITA would understand that a “signal indicating a system operational
`state of said load” does not require indicating a “particular context” external to the
`load.
`
`6
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`the ACPI specification (EX2022) defines C-states in terms of the state of the
`
`processor (i.e., the load), and specifically the power-consumption state of the
`
`processor, not a particular context independent from the operational state or activity
`
`level of the processor.
`
`10. As another example, the ’514 Patent discloses “a signal indicating that
`
`a load current will change” as an “example of a signal indicating a change in a system
`
`operational state.” EX1001, 9:23-27. A “load current” is simply the electrical
`
`current drawn by a load. EX1029, 5. Thus, this example of a signal indicating a
`
`change in a system operational state is focused on a change in the load itself,
`
`specifically a change in the load current itself, not a particular context external to the
`
`load. I note that Patent Owner cites a portion of this load-current example to support
`
`Patent Owner’s interpretation. POR, 19-20; see also EX2018 (Ferrese Declaration),
`
`¶ 52. However, neither Patent Owner nor its expert, Dr. Ferrese, provide any
`
`explanation as to how a load current indicates a particular “context” external to the
`
`load regarding how the system is being employed or utilized. To the opposite, the
`
`load current by definition is simply the electrical current drawn by the load,
`
`irrespective of any particular context external to the load.
`
`B.
`
`Chagny’s “Activity Input 202” Signal is a “Signal Indicating a
`System Operational State of Said Load”
`
`11. As illustrated in annotated Figure 2A below, the “activity input 202”
`
`received by Chagny’s controller module 210 (i.e., the power converter controller)
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`7
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`indicates the activity level of processor 292 (i.e., the load) and thus is a “signal
`
`indicating a system operational state of said load.” EX1004, 4:35-43 (“In one
`
`embodiment, a software program 296, which may be included in the operating
`
`system (not shown) of the device 290, monitors the processor 292 loading. The
`
`software program 296 may utilize predictive techniques to forecast the processor
`
`292 loading by analyzing the processor instruction pipeline stack. Based on the
`
`processor 292 loading and/or the forecasted values, the software program 296
`
`generates the activity input 202 indicative of levels of activity of the processor
`
`292.”), 5:11-12 (describing “activity input 202 indicative of the activity level of the
`
`processor 292”).
`
`software program
`
`processor
`
`activity input 202
`(i.e., signal indicating
`system operational
`state of load)
`
`power
`converter
`controller
`
`power converter
`
`8
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`EX1004, Fig. 2A (annotated).
`12.
`The ’514 Patent describes “system operational states” as including the
`
`“core state” of a processor that affects the processor’s “level of power consumption.”
`
`EX1001, 5:19-27 (describing “system operational state” considerations, for example
`
`the ACPI defined “‘P-states’ and ‘C-states’ of a processor”), 5:44-59 (describing
`
`“processor state indicator” the “core state” or “C-state” that “affects its level of power
`
`consumption” and how “various sleep levels are achieved by halting instruction
`
`execution”). Similar to this example in the ’514 Patent, the activity level of Chagny’s
`
`processor 292 depends “on the number of instructions executed within a predefined
`
`time interval.” EX1004, 4:18-20. The activity level of Chagny’s processor 292 thus
`
`reflects the “demand for power required by the processor 292.” See id., 5:62-64.
`
`13.
`
`I understand that Patent Owner attempts to refute this point by arguing
`
`that the above-cited passages from the ’514 Patent “are intended to make a
`
`distinction between what was known (C-states and P-states) and what is novel about
`
`the ’514 Patent.” POR, 22-23 (citing EX1001, 5:60-64). But in my opinion, Patent
`
`Owner’s argument is misplaced. The ’514 Patent specification does not distinguish
`
`“core states” or “C-states” from “system operational states.” Instead, the ’514 Patent
`
`describes processor “core states” as examples of “system operational states.” See
`
`EX1001, 26:10-11 (referencing “a system operational state such as a processor core
`
`state”). What the ’514 Patent was attempting to distinguish was how conventional
`
`9
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`power converter controllers were purportedly not configured to respond to signals
`
`indicating the system operational state of the load connected to the power converter.
`
`See id., 5:19-22 (“Power conversion systems of the prior art have only partially
`
`responded to such system operational state considerations in the optimization of
`
`operating efficiency, … .”), 5:60-6:2 (describing perceived “opportunities for further
`
`improvement in power converter operational efficiency”), 6:36-44 (describing
`
`perceived need for “controller for a power converter and power system that
`
`adaptively improves power conversion efficiency of a power converter”). However,
`
`both Chagny and Hwang also disclose controlling power converters in response to
`
`signals indicating system operational states of loads connected to those power
`
`converters.
`
`C.
`
`Hwang’s “Standby Signal” is a “Signal Indicating a System
`Operational State of Said Load”
`
`14. Hwang’s controller 105 (i.e., the power converter controller) receives a
`
`“standby signal” from smart load 104 indicating that the microprocessor within
`
`smart load 104 is in a “standby or ‘sleep’ mode during periods of low activity.”
`
`EX1006, [0021] (“The controller 105 may sense a signal from the load 104 that
`
`indicates the level of the power drawn by the load 104. A standby signal from the
`
`load 104 may instruct the controller 105 to enter standby mode. For example, where
`
`the load 104 is a microprocessor or controller, it may enter a standby or ‘sleep’ mode
`
`during periods of low activity for power conservation.”); see also id. [0019], [0031].
`
`10
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`power converter controller
`
`“smart load” including
`power system controller
`
`standby signal
`(indicating system
`operational state)
`
`power converter
`
`EX1006, Fig. 1 (annotated).
`
`15.
`
`In my opinion, Hwang’s standby signal is directly analogous to
`
`examples of signals indicating the system operational state of the load in the
`
`’514 Patent specification. The ’514 Patent describes “system operational states” as
`
`including, for example, the “core states” of a processor, which “describe various
`
`levels of a processor sleep state” and thus affect the processor’s “level of power
`
`consumption.”
`
` EX1001, 5:19-27 (describing “system operational state”
`
`considerations, for example the ACPI defined “‘P-states’ and ‘C-states’ of a
`
`processor”), 5:44-59 (describing “processor state indicator,” the “core state” or
`
`“C-state” that “affects its level of power consumption” and how “various sleep levels
`
`are achieved by halting instruction execution”); see also id., 9:11-13. Likewise,
`
`Hwang’s standby signal is sent from smart load 104 (i.e., the load) to controller 105
`
`11
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`(i.e., the power converter controller) when the microprocessor within smart load 104
`
`enters a “standby or ‘sleep’ mode during periods of low activity.” EX1006, [0021]
`
`(“The controller 105 may sense a signal from the load 104 that indicates the level of
`
`the power drawn by the load 104. A standby signal from the load 104 may instruct
`
`the controller 105 to enter standby mode. For example, where the load 104 is a
`
`microprocessor or controller, it may enter a standby or ‘sleep’ mode during periods
`
`of low activity for power conservation.”); see also id. [0031] (“The load 104 may be
`
`a smart load in that it may instruct the controller 105 to enter a standby mode. For
`
`example, the load 104 may include a microprocessor that may enter a standby mode
`
`during periods of low activity or non-use. The load 104 may send a standby signal
`
`that may be interpreted by a low power detector 308.”). Thus, in my opinion, Hwang
`
`discloses the recited “signal indicating a system operational state of said load” in the
`
`same manner as the ’514 Patent.
`
`16. Moreover, the ’514 Patent specification also describes “a signal
`
`indicating that a load current will change” as an “example of a signal indicating a
`
`change in a system operational state.” EX1001, 9:23-27. Notably, the output
`
`voltage of Hwang’s power converter 100 is constant. EX1006, [0021] (“Using this
`
`sensed signal and by controlling a switch in PWM stage 103, the controller 105
`
`attempts to maintain a constant output voltage or current.”), [0030] (“The PWM
`
`controller 310 may cause the switch SW2 to be switched on and off in an attempt to
`
`12
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`cause the output voltage Vout to remain substantially constant.”). Thus, the voltage
`
`received by Hwang’s smart load 104 from the output of power converter 100 is also
`
`constant. See id. Moreover, power equals voltage times current (P=V*I). EX1030,
`
`12. Thus, in scenarios like Hwang with a constant voltage provided to the load, a
`
`signal indicating a change in the processor power demand (P) would also be a signal
`
`indicating a change in the processor current demand (I) from the power converter.
`
`And as I note in Section II.A above, the ’514 Patent refers to such a signal indicating
`
`a change in the load current as a signal indicating a system operational state of the
`
`load.
`
`III.
`
`“CHARACTERIZING A POWER REQUIREMENT” (CLAIM 6)
`
`17. Claim 6 of the ’514 Patent recites “a power system controller
`
`configured to provide a signal characterizing a power requirement of a processor
`
`system.” EX1001, claim 6. A later portion of claim 6 recites “a power converter
`
`controller configured to receive a signal from said power system controller to control
`
`an internal operating characteristic of said power converter as a function of said
`
`signal.” Id. As I noted in my initial declaration, the signal provided by power system
`
`controller to characterize a power requirement of the processor system may be the
`
`same signal received by the power converter controller later in claim 6. EX1002 at
`
`page 40 n.5.
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`13
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`18.
`
`In my opinion, the plain meaning of “characterizing a power
`
`requirement of a processor system” is merely “describing a power requirement of a
`
`processor system.” See EX1028, 4 (defining “characterize” as “to describe the
`
`character or quality of”).
`
`19.
`
`I understand that during deposition, Patent Owner’s expert Dr. Ferrese
`
`argued that because other portions of claim 6 require the power converter controller
`
`to control an internal operating characteristic as a function of the signal received
`
`from the power system controller, that signal “could not tell anything other than how
`
`much power to provide.” EX1027, 85:10-16; see also id., 83:6-86:8. I disagree with
`
`this statement from Dr. Ferrese.
`
`20. As an initial matter, controlling an internal operating characteristic of a
`
`power converter versus telling the power converter to provide a specific level of
`
`power as a function of the signal from the power system controller are two different
`
`things. The ’514 Patent describes how an internal operating characteristic may be
`
`controlled, for example, to improve power-converter efficiency across different load
`
`conditions. See, e.g., EX1001, 9:28-38 (“[T]he controller for a power converter
`
`according to the principles of the present invention can control, alter, relax, or
`
`differently constrain an internal operating characteristic (such as … a switching
`
`frequency …) … to improve an efficiency thereof in response to … a signal
`
`indicating a system operational state.”), 15:1-12 (describing altering “switching
`
`14
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`frequency” using, for example, “actual load current” or “operating constraints that
`
`may be signaled from an external source”). Meanwhile, a POSITA would have
`
`understood that the conventional feedback loop of a power converter would
`
`determine how much power to provide at its output (and thus to the load) to maintain
`
`the desired output voltage across different levels of power drawn by the load.
`
`EX1031 (Grebene Textbook excerpts), 13 (describing how voltage regulators,
`
`whether linear or switching type, supply constant voltage across “changing load
`
`conditions”); EX1032 (Hirst), Fig. 2, 6:1-14 (describing “conventional” pulse-width
`
`modulation for switching power converter to regulate amount of charge that is
`
`needed to be transferred to the output under given load condition to maintain desired
`
`output voltage). Thus, in my opinion, there is no implied requirement in claim 6
`
`that the signal received by the power converter controller tell the power converter to
`
`provide a certain level of power.
`
`IV.
`
`“ENABLE” / “ENABLING” (CLAIMS 11 AND 16)
`
`A.
`
`Chagny and Hwang Disclose the “Enable” and “Enabling”
`Elements of Claims 11 and 16
`
`21.
`
`I understand that Patent Owner argues that the Chagny (Ground 1A)
`
`and Hwang-based (Grounds 2A-B) grounds fail to disclose “[to enable/enabling]
`
`operation of components of a processor system to establish a state of power drain
`
`thereof” as recited by claims 11 and 16.
`
`22.
`
`In my opinion, a person of ordinary skill in the art (“POSITA”) would
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`have understood that Chagny’s “processor 292” (e.g., EX1004, 4:35-45), and
`
`Hwang’s “microprocessor” (e.g., EX1006, [0021], [0031]), include multiple
`
`components, such as a control unit, a central processing unit, a memory to store the
`
`instructions to be executed, and input/output ports. For example, the Microprocessor
`
`Data Book by S.A. Money describes the basic architecture for well-known
`
`processor-based systems as including a control unit, a central processing unit (CPU),
`
`memory to store the instructions to be executed, and input/output ports. EX1015,
`
`4-6; see also id., 5 (Fig. 1.1). Thus, a POSITA would have understood that Chagny’s
`
`processor 2924 and Hwang’s microprocessor are processor systems with multiple
`
`components.
`
`23.
`
`I understand that Patent Owner first argues that “components of a
`
`processor system” include components, such as memory, hard drives, and
`
`specialized circuit cards, that are “peripheral” to the processor. POR, 26; see also
`
`id., 46. However, the ’514 Patent specification describes how personal computers
`
`or processors systems may “often” be constructed, not how they must be constructed.
`
`EX1001, 13:29-33. Thus, in my opinion, the non-limiting example in the ’514
`
`Patent specification does not warrant interpreting claims 11 and 16 as requiring
`
`4 Chagny’s processor system also includes other associated components such as
`memory and input/output devices. EX1004, 7:17-30, Fig. 4.
`
`16
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`components that are “peripheral” to the processor.
`
`24.
`
`I understand that Patent Owner further argues that the prior art “does
`
`not disclose the capability to selectively power individual components of a
`
`processor.” POR, 46 (emphasis added). But in my opinion, there is no requirement
`
`in the claims that the components of the processor system be “selectively” enabled,
`
`much less selectively powered. Instead, the plain language of the claims requires
`
`that “enabling” components of the processor system be done for the purpose of
`
`establishing “a state of power drain” of those components. See EX1001, claims 11,
`
`16. Nothing requires that the components be “selectively” enabled, much less
`
`“selectively” powered on or off in a binary manner. First, the claims merely recite
`
`“[to enable / enabling] operation of components of the processor system.” EX1001,
`
`claims 11, 16. The plain language covers scenarios where operation of any two or
`
`all components of the processor system are enabled. Moreover, the ’514 Patent
`
`describes power drains at varied “operating” levels. Id., 13:60-63 (describing “when
`
`power drains are at a normal or reduced operating level”). Thus, the ’514 Patent
`
`itself contemplates the enabling of varied operational levels.
`
`25.
`
`In my opinion, both Chagny and Hwang disclose enabling components
`
`of their respective processor systems to establish states of power drain at such varied
`
`operating levels. Chagny’s software program 296 sets two bits in processor 292 to
`
`enable components of its processor to operate at one of “4 activity levels.” EX1004,
`
`17
`
`Samsung/Dell, Exh. 1026, p. 17
`Samsung/Dell v. MYPAQ, IPR2022-00311
`
`
`
`6:3-12 (“The UREG_B1 272 and UREG_B2 274 bits are used to define up to 4
`
`activity levels of the processor 292. For example, the low level of activity may be
`
`defined by setting UREG_B1 272 and UREG_B2 274 bits to 0 and 0 respectively.
`
`Similarly, the medium level of activity may be defined by setting UREG_B1 272
`
`and UREG_B2 274 bits to 1 and 0 respectively and the high level of activity may be
`
`defined by setting UREG_B1 272 and UREG_B2 274 bits to 1 and 1 respectively.
`
`As the activity level of the processor 292 changes, the value of each bit also changes
`
`dynamically.”). By enabling operation of components of Chagny’s processor
`
`system, Chagny’s software program 296 thereby establishes the “demand for power
`
`required by the processor 292” (i.e., the state of power drain). Id., 5:57-64 (“In one
`
`embodiment, in addition to the GPO1 262 and GPO2 264 bits stored in the ICH 280,
`
`the software program 296 defines UREG_B1 272 and UREG_B2 274, which are 2
`
`bits in a register of the processor 292 to control the maximum number of instructions
`
`executed per clock cycle. The demand for power required by the processor 292 is
`
`advantageously controlled by limiting the number of instructions executed for a
`
`predefined time period.”). A POSITA would have understood, for example, that as
`
`the activity level of the processor increases, additional component blocks within the
`
`processor system would be actively employed to process instructions, thus
`
`increasing the demand for power. Conversely, a POSITA would have understood
`
`that as the activity level of the processor decreases, less component blocks within
`
`18
`
`Samsung/Dell, Exh. 1026, p. 18
`Samsung/Dell v. MYPAQ, IPR2022-00311
`
`
`
`the processor system would be actively employed to process instructions, thus
`
`lowering the demand for power.
`
`26.
`
`Similarly, Hwang discloses entry of its smart load 104 (which includes
`
`the microprocessor) into a “standby” or “sleep” mode. EX1006, [0021] (“The
`
`controller 105 may sense a signal from the load 104 that indicates the level of the
`
`power drawn by the load 104. A standby signal from the load 104 may instruct the
`
`controller 105 to enter standby mode. For example, where the load 104 is a
`
`microprocessor or controller, it may enter a standby or ‘sleep’ mode during periods
`
`of low activity for power conservation.”), [0031] (“The load 104 may be a smart
`
`load in that it may instruct the controller 105 to enter a standby mode. For example,
`
`the load 104 may include a microprocessor that may enter a standby mode during
`
`periods of low activity or non-use. The load 104 may send a standby signal that may
`
`be interpreted by a low power detector 308.”). Thus, Hwang enables components of
`
`its microprocessor to operate in a standby condition thereby establishing a standby-
`
`level of power drain. Id., [0021], [0031].
`
`V.
`
`“IN ACCORDANCE WITH” (CLAIMS 2, 7, 12, & 17)
`
`27. Claim 2 recites that the power converter controller is configured to
`
`control the duty cycle of the power switch “as a function of said output characteristic
`
`and in accordance with said signal.” I understand that for Claims 7, 12, and 17,
`
`Patent Owner relies on similarities to claim 2 rather than arguing those claims
`
`19
`
`Samsung/Dell, Exh. 1026, p. 19
`Samsung/Dell v. MYPAQ, IPR2022-00311
`
`
`
`separately. POR 32 (Chagny).
`
`A.
`
`Chagny Discloses the “In Accordance With” Limitation Because
`Duty Cycle Control Depends on Switching Frequency
`
`28. Chagny’s power converter controller is configured to provide signal
`
`212 (i.e., another signal) to control the duty cycle of the power switch (i) as a
`
`function of feedback from the regulated DC voltage output 295 (i.e., as function of
`
`said output characteristic), and (ii) in accordance with Chagny’s “activity input 202”
`
`signal (i.e., said signal) that indicates the system operational state of the load.
`
`EX1004, 4:63-5:8 (“The controller module 210 includes a frequency selector
`
`module 215 and a FET driver module 218. The controller module 210 receives the
`
`regulated DC voltage output 295 as a feedback input for regulating the output of the
`
`VRM 200. The frequency selector module 215 is operable to receive the activity
`
`input 202. e.g., GPO1 262 and GPO2 264, and select a switching frequency 216 from
`
`a plurality of switching frequencies as an output, which dynamically matches the
`
`level of activity of the processor 292. In one embodiment, the plurality of switching
`
`frequencies exactly corresponds to the levels of activity of the processor 292. For
`
`example, in the embodiment having low, medium and high activity levels there are
`
`3 corresponding low 130, medium 140 and high 150 switching frequencies.”), 5:28-
`
`31 (describing generation of control signal 212 at selected switching frequency),
`
`5:34-46 (describing how DC voltage input 204 is “chopped” by the charge switch
`
`20
`
`Samsung/Dell, Exh. 1026, p. 20
`Samsung/Dell v. MYPAQ, IPR2022-00311
`
`
`
`220 to generate square wave at switched DC voltage output 225 having an average
`
`voltage equal to required output voltage).
`
`software program
`
`signal to control
`duty cycle of power switch
`
`power switch
`
`processor
`
`“activity input 202”
`(i.e., signal indicating
`system operational
`state of load)
`
`EX1004, Fig. 2A (annotated).
`
`power
`converter
`controller
`
`feedback
`
`power converter
`
`29. As shown in Figure 2A, signal 212 controls Chagny’s power switch at
`
`a switching frequency determined by frequency selector module 215 within
`
`controller module 210 (i.e., the power converter controller) based on the “activity
`
`input 202” signal. See EX1004, 4:66-5:2 (“The frequency selector module 215 is
`
`operable to receive the activity input 202 … and select a switching frequency 216
`
`… .”), 5:28-31 (describing generation of control signal 212 at selected switching
`
`frequency).
`
`21
`
`Samsung/Dell, Exh. 1026, p. 21
`Samsung/Dell v. MYPAQ, IPR2022-00311
`
`
`
`30.
`
`I understand that Patent Owner contends that “duty cycle” and
`
`“switching frequency” are separate concepts, and that Chagny’s “activity input 202
`
`sets the switching frequency,” but “not the duty cycle.” POR, 33. As an initial
`
`matter, I note that Patent Owner’s position is misplaced. Claim 2 of the ’514 Patent
`
`for example merely requires another signal to control said duty cycle “in accordance
`
`with” said signal indicating the system operational state. EX1001, claim 2. In my
`
`opinion, there is no requirement that said signal indicating system operational state
`
`must “set” the duty cycle as purported by PO. Indeed, such a requirement would
`
`conflict with other portions of the claim, because if the duty cycle were “set” to a
`
`value by “said signal,” the duty cycle could not also be controlled “as a function of
`
`said output characteristic.” See EX1001, claim 2; see also id., 11:15-18 (describing
`
`how “the duty cycle” of power switches may be “adjusted to maintain a regulation
`
`of the output voltage Vout of the power converter.”) (emphasis added).
`
`31. Moreover, Patent Owner’s position ignores the relationship between
`
`duty cycle and switching fr
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