(19) United States
`(12) Patent Application Publication (10) Pub. No.: US 2007/0222463 A1
`Qahouo et al.
`(43) Pub. Date:
`Sep. 27, 2007
`
`US 20070222463A1
`
`(54) POWER CONVERSION EFFICIENCY
`MANAGEMENT
`
`(76) Inventors: Jaber Abu Qahouq, Beaverton, OR
`(US); Lilly Huang, Portland, OR (US)
`Correspondence Address:
`SCHWEGMAN, LUNDBERG, WOESSNER &
`KLUTH, P.A.
`P.O. BOX 2938
`MINNEAPOLIS, MN 55402 (US)
`(21) Appl. No.:
`11/387,395
`
`(22) Filed:
`
`Mar. 23, 2006
`
`Publication Classification
`
`(51) Int. Cl.
`(2006.01)
`GOIR 27/08
`(52) U.S. Cl. .............................................................. 324/712
`
`(57)
`
`ABSTRACT
`
`Some embodiments of the invention may operate tO measure
`a feedback error signal change as an indication of efficiency
`associated with a power stage, and to select a determined
`power stage parameter value to increase the efficiency
`responsive to the feedback error signal change.
`
`-
`
`138
`
`
`
`W
`
`FILTER
`
`11
`8
`
`126
`Ps
`f f
`sw swa
`
`/118 /118
`
`PS2
`
`PSN
`
`83
`
`138
`
`1501O
`
`-
`
`Wo
`INPUT (lo)
`
`WS
`
`PROCESSOR
`
`128
`
`N-
`
`C1, C2, ... Cn
`
`124
`
`42
`| SWITCHING
`* CONTROLLER Y134
`
`CONTROLER
`14
`122
`
`PML
`
`---
`
`We
`
`GAIN
`COMPENSATOR
`s
`f)
`
`refre
`
`130
`
`DAS
`
`100
`
`/
`
`154
`
`158
`
`162
`
`MyPAQ, Exhibit 2025
`IPR2022-00311
`Page 1 of 10
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`

`

`Patent Application Publication Sep. 27, 2007 Sheet 1 of 4
`
`US 2007/0222463 A1
`
`0 || ||
`
`_° C).
`
`81 L/ 81
`
`|-ZSd
`
`|
`
`
`
`
`
`
`
`XJETTO}} | NOO
`
`-
`
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`IPR2022-00311
`Page 2 of 10
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`Patent Application Publication Sep. 27, 2007 Sheet 2 of 4
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`US 2007/0222463 A1
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`FIG. 2
`
`
`
`
`
`
`
`MEASURE
`FEEDBACK
`ERROR SIGNAL
`CHANGE
`
`
`
`
`
`SURVEY
`MULTIPLE
`STAGES
`
`
`
`
`
`FETCH
`ACCEPTABLE
`EFFICIENCY
`
`READ REGISTER
`
`NDef> ACCeff?
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`SELECT
`PARAMETER
`VALUE
`
`- PERIODC
`INCREASE,
`DECREASE
`- MONOTONC
`INCREASE,
`DECREASE
`- MULTIPLE
`STAGES
`
`
`
`
`
`
`
`
`
`/21
`
`DETECT FAILED
`REGULATOR
`
`281
`
`
`
`SELECT
`PARAMETER
`VALUE CHANGE
`DIRECTION
`
`DETERMINE
`CHANGE
`DIRECTION
`
`271
`
`261
`
`MyPAQ, Exhibit 2025
`IPR2022-00311
`Page 3 of 10
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`Patent Application Publication Sep. 27, 2007 Sheet 3 of 4
`
`US 2007/0222463 A1
`
`FG, 3
`
`
`
`
`
`
`
`
`
`
`
`MEASURE We
`
`/31
`
`CALCULATEAV, AF AT
`... Etc.
`
`AVe Ve(current) Ve?previous),
`AF e Fs(current) Fs(previous),
`ATd Td(current) Td(previous)
`
`
`
`
`
`SIGN(AV) = SIGN(AF)
`OR
`SIGN(AV) = SIGNCAT)
`
`NCREMENT
`
`Fs, Td
`
`DECREMENT
`
`
`
`
`
`
`
`F. Td
`
`RESTART
`
`MyPAQ, Exhibit 2025
`IPR2022-00311
`Page 4 of 10
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`Patent Application Publication Sep. 27, 2007 Sheet 4 of 4
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`US 2007/0222463 A1
`
`FIG. 4
`
`
`
`485
`
`INSTRUCTIONS
`
`COMPUTER
`
`MyPAQ, Exhibit 2025
`IPR2022-00311
`Page 5 of 10
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`US 2007/0222463 A1
`
`Sep. 27, 2007
`
`POWER CONVERSION EFFICIENCY
`MANAGEMENT
`
`TECHNICAL FIELD
`0001 Various embodiments described herein relate to the
`provision of power generally, including apparatus, systems,
`and methods used to manage the efficiency of power Sup
`plies and converters.
`
`BACKGROUND INFORMATION
`0002 The output error voltage in a power stage may be
`used to regulate the output voltage, perhaps by determining
`the duty cycle or Switching frequency of the stage in order
`to regulate the output voltage. For example, under steady
`state conditions, such as constant load, input Voltage, and
`ambient temperature, the conventional control loop may
`operate to force the output voltage to match the reference
`Voltage. Such that the output error Voltage tends toward Zero.
`In this case, the output error Voltage is substantially dedi
`cated to regulating the output Voltage.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`0003 FIG. 1 is a block diagram of apparatus and systems
`for power conversion efficiency management according to
`various embodiments of the invention.
`0004 FIG. 2 is a flow diagram illustrating several meth
`ods for power conversion efficiency management according
`to various embodiments of the invention.
`0005 FIG. 3 is a flow diagram illustrating additional
`methods for power conversion efficiency management
`according to various embodiments of the invention.
`0006 FIG. 4 is a block diagram of an article for power
`conversion efficiency management according to various
`embodiments.
`
`DETAILED DESCRIPTION
`0007 Power supply designers are typically concerned
`with two aspects of Supply performance: output regulation,
`and efficiency. While conventional designs make use of an
`error Voltage (Ve) to dynamically improve regulation, effi
`ciency often depends on static design parameters. In the
`embodiments described herein, efficiency may be improved
`in a dynamic fashion by measuring a change in an error
`signal (e.g., AVe, or the change in error Voltage, or AIe, or
`the change in error current), and adjusting selected Supply
`parameters in response thereto.
`0008 Thus, while the error voltage may remain substan
`tially constant, its value depends not only on the difference
`between the input Voltage and the output voltage (via circuit
`gain), but on the power losses in the power conversion path.
`Greater losses mean that less energy is delivered to the
`output, and thus, efficiency may be reduced. Here, the
`change in the error signal is used as indication to determine
`in which direction power stage parameters should be
`changed (e.g., incremented or decremented), so that the error
`signal can be used to indicate power losses and improve
`operating efficiency, reducing the losses.
`0009 FIG. 1 is a block diagram of apparatus 100 and
`systems 110 for power conversion efficiency management
`according to various embodiments of the invention. The
`
`apparatus 100 may include measurement logic 114 to mea
`Sure a feedback error signal change AFSe (e.g., comprising
`an output Voltage error change AVe) as an indication of
`efficiency in one or more power stages 118. The apparatus
`100 may also include performance governor logic 122
`coupled to the power stages 118. Such that the performance
`governor logic 122 is used to select one or more determined
`power stage control parameter values C1, C2, . . . . CN to
`increase efficiency responsive to the feedback error signal
`change AFSe. Examples of determined power stage control
`parameter values C1, C2, .
`.
`. . CN include selecting a
`particular Switching frequency or Switching dead time,
`selecting an input Voltage or an output voltage, or selecting
`a number of active Switches, or active power stages, among
`others. The measurement logic 114 and the performance
`governor logic 122 may form a portion of an adaptive
`controller 124.
`00.10
`Essentially, a control technique is disclosed herein
`that can be used to dynamically reduce power consumption
`by adaptively tracking the change in feedback error signal.
`Here, the change in a feedback error signal is used as an
`indicator of efficiency (i.e., as an increase or decrease in
`power loss when power is provided in various applications).
`By monitoring the feedback error signal change and using it
`as an indication of efficiency, the trend of power consump
`tion and efficiency for the power stages 118 can be predicted.
`It is then possible to use the trend information to dynami
`cally select proper control parameters or modify the existing
`mode of operation in order to reduce power loss, even in the
`face of adverse conditions, such as a non-constant input
`Voltage, variable loading, and component parameter insta
`bility.
`0011 Various embodiments may include a wide variety
`of mechanisms to Supply power, convert power, and invert
`power. For example, the power stages 118 may-include one
`or more converters 126, such as buck converters, boost
`converters, AC-AC converters, AC-DC converters, DC-DC
`converters, and DC-AC converters, among others. That is,
`while a simple DC-DC voltage regulator 128 is shown in
`FIG. 1, any number of circuit topologies may be used.
`0012. In some embodiments, then, the apparatus 100 may
`include one or more gain compensators 130 to couple to the
`measurement logic 114, and to receive a reference Voltage
`Vref. The apparatus 100 may also include one or more
`switching frequency controllers 134 coupled to the perfor
`mance governor logic 122, and/or one or more input filters
`138 coupled to the power stages 118.
`0013 While it should be understood that the feedback
`error signal change AFSe may comprise an error Voltage
`change or an error current change, the example of an error
`voltage change will be used for the balance of this document
`in order to maintain simplicity. Thus, the reader should
`understand that the terms “voltage' and “current can be
`used interchangeably throughout this document, and in the
`figures.
`0014 Consider the situation where the output voltage Vo
`is regulated to assume a value that approximates a reference
`voltage, Vref, while the power stages 118 are supplied by an
`input voltage, Vi. Then the output error voltage Ve may be
`defined as the difference between the output voltage Vo and
`the reference Voltage Vref, after being adjusted according to
`
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`the action of gain or/and compensation transfer networks,
`which may include the power stages 118 and the input filters
`138 as shown in FIG. 1.
`0.015 The determined power stage control parameter
`values C1, C2, .
`.
`. Cn are defined as a set of control
`parameter values which may be adjusted to reduce the power
`losses of a power stage. Thus, the determined power stage
`control parameter values C1, C2, . . . Cn may comprise a
`number of power stage control variables, such as dead time,
`Switching frequency, and input voltage from a previous
`stage. The control signal 142 may be used to directly manage
`the power processing and/or Switching activity of power
`Switching devices 146 in the power stages 118, including
`their switching frequency.
`0016.
`In practice, some-embodiments may operate as
`follows. While an error signal, such as the error voltage Ve,
`may be used to determine the duty cycle or/and Switching
`frequency of power stage Switches 146, including turning
`the Switches 146 ON for a certain amount of time to deliver
`the necessary energy to the load and regulate the output
`Voltage Vo, in many embodiments the feedback error signal
`change AFSe, Such as AVe, may be used to indicate the
`change in the direction of power loss in the power stages 118
`while adaptively varying the determined power stage control
`parameter values C1, C2, ... Cn to reduce power losses, and
`increase efficiency. The determined power stage control
`parameter values C1, C2, ... Cn include power switch dead
`time, Switching frequency, input/output voltage, number of
`turned ON Switches or power stages, among others. Thus,
`monitoring the change in the error signal AFSe, Such as AVe,
`may reveal additional information that indicates the conver
`sion power loss in addition to the required duty cyclef
`conversion ratio (gain). This indication of efficiency, or
`power loss, can therefore be used to adaptively reduce power
`losses and increase efficiency.
`0017. In many power stages, when a substantially steady
`state condition exist (e.g., a constant load, constant input
`Voltage, and/or constant environmental temperature, etc.),
`the control loop operates to force the output voltage to be the
`same as the reference Voltage. However, as mentioned
`previously, the error voltage Ve depends on the difference
`between the input voltage and the output voltage, as well as
`the power losses in the conversion path. Using the mecha
`nism disclosed herein, determined power stage control
`parameter values C1, C2, ... Cn can be adaptively adjusted
`(e.g., incremented and decremented) in response to the
`measured change in Ve to find values that provide reduced
`power losses, increasing efficiency. In some embodiments,
`this may occur by minimizing the steady state error Voltage
`Ve, in a buck converter, for example. Power loss, and
`therefore efficiency, may vary under different conditions due
`to component parasitics.
`0018. In some embodiments, efficiency may be deter
`mined using the following relationship:
`
`Efficiency = Fo P - P - P - Pother,
`P
`P
`
`where Pin=input power; Pswo-f(Vswifsw) switching
`losses as a function of the Voltage across the Switch (VSW),
`
`which sometimes may be equal to Vo; also a function of
`Switch parasitic capacitance, and other parasitics:
`0019), Pcondo f(I, R) conduction losses as a function of
`Switch on-resistance and other component resistance; and
`P=other power losses, such as those from control logic
`and drivers. According to Some embodiments, the efficiency
`may be determined in other ways, that is, by using different
`relationships, as one of ordinary skill in the art would
`appreciate based at least on the teachings provided herein.
`0020 Power loss, including switching and conduction
`losses, is often lowest when Ve is minimum, using less input
`power for the same delivered output power, and thus reduc
`ing power loss. It should be noted, then, that a change in AVe
`may be used to minimize Ve, resulting in reduced losses.
`However, it is often beneficial to maintain a value of Ve
`Sufficient to ensure output regulation. Thus, the direction in
`which Ve changes (the direction of AVe) can be used as an
`indication of the direction to change the determined power
`stage control parameter values C1, C2, ... Cn (e.g., whether
`to increment or decrement them), and Ve may be targeted for
`decreasing (or increasing, depending on modulation direc
`tion), which results in reduced power losses and higher
`conversion efficiency.
`0021. Other embodiments may be realized. For example,
`a system 110, comprising any number of electronic devices,
`Such as a power Supply, or a laptop or desktop computer,
`may include one or more apparatus 100 as described above.
`The system 110 may also include a processor 148 and one
`or more displays 150 to receive power from the power stages
`118.
`0022. In some embodiments, the system 110 may include
`a computer motherboard 154 to receive power from the
`power stage(s) 118 (e.g., in a computer or workstation
`implementation), a television tuner 158 to receive power
`from the power stage(s) 118 (e.g., in a television implemen
`tation), and/or a medical data acquisition system 162 to
`receive power from the power stage(s) 118 (e.g., in a
`medical device implementation, such as an ultrasound imag
`ing unit, or an EKG machine). That is, the motherboard 154,
`the television tuner 158, and the data acquisition system 162
`may be used alone, or in conjunction with each other.
`0023. Any of the components previously described can
`be implemented in a number of ways, including simulation
`via software. Thus, the apparatus 100; systems 110; mea
`Surement logic 114; power stages 118; performance gover
`nor logic 122; adaptive controller 124; converter 126; DC
`DC voltage regulator 128; gain compensator 130; switching
`frequency controller 134; input filters 138; control signal
`142; power switching devices 146; processor 148; display
`150; motherboard 154; television tuner 158; medical data
`acquisition system 162; determined power stage control
`parameter values C1, C2, . . . . CN; feedback error signal
`change AFSe; output error Voltage Ve; input voltage Vi;
`output voltage Vo; and reference voltage Vref may all be
`characterized as "modules' herein.
`0024. Such modules may include hardware circuitry,
`single and/or multi-processor circuits, memory circuits, soft
`ware program modules and objects, and/or firmware, and
`combinations thereof, as desired by the architect of the
`apparatus 100 and systems 110, and as appropriate for
`particular implementations of various embodiments. For
`
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`
`Sep. 27, 2007
`
`example, Such modules may be included in a system opera
`tion simulation package. Such as a software electrical signal
`simulation package, a power usage and distribution simula
`tion package, a capacitance-inductance simulation package,
`a power/heat dissipation simulation package, a signal trans
`mission-reception simulation package, and/or a combination
`of software and hardware used to operate, or simulate the
`operation of various potential embodiments.
`0025. It should also be understood that the apparatus and
`systems of various embodiments can be used in applications
`other than DC-DC converters and power supplies, and thus,
`various embodiments are not to be so limited. The illustra
`tions of apparatus 100 and systems 110 are intended to
`provide a general understanding of the structure of various
`embodiments, and they are not intended to serve as a
`complete description of all the elements and features of
`apparatus and systems that might make use of the structures
`described herein.
`0026 Applications that may include the novel apparatus
`and systems of various embodiments include electronic
`circuitry used in high-speed computers, communication and
`signal processing circuitry, single and/or multi-processor
`modules, single and/or multiple embedded processors, and
`application-specific modules, including multilayer, multi
`chip modules. Such apparatus and systems may further be
`included as Sub-components within a variety of electronic
`systems, such as televisions, cellular telephones, personal
`computers, Switches, hubs, routers, modems, workstations,
`radios, video players, audio players, medical devices,
`vehicles, and others.
`0027 Some embodiments may include a number of
`methods. For example, FIG. 2 is a flow diagram illustrating
`several methods 211 for power conversion efficiency man
`agement according to various embodiments of the invention.
`For example, a method 211 begin with measuring a feedback
`error signal change as an indication of efficiency associated
`with a power stage at block 221. In some embodiments, the
`method 211 may include Surveying a plurality of power
`stages to measure corresponding feedback error signal
`changes as an indication of efficiency associated with each
`of the Surveyed power stages.
`0028. In some embodiments, the method 211 may include
`fetching or otherwise retrieving a value of an acceptable
`efficiency with respect to the power stage at block 231. For
`example, the value may be retrieved by reading a register to
`determine an acceptable efficiency associated with the
`power stage. The method 211 may also include selecting a
`trial determined power stage parameter value if the indica
`tion of efficiency (INDeff) is less than the acceptable effi
`ciency ACCeff at blocks 241 and 251. Otherwise, if the
`indication of efficiency INDeff is greater than or equal to the
`acceptable efficiency ACCeff, the method 211 may continue
`at block 221.
`0029. The selection of a trial determined power stage
`parameter value at block 251 may occur in a number of
`ways. For example, selecting the determined power stage
`parameter value to increase the efficiency of the power stage
`responsive to the feedback error signal change (such as an
`error Voltage change if error Voltage Ve tracking is used to
`optimize Switching frequency or dead time in a digital
`controller to improve the operating efficiency of a buck
`converter, for example), may be effected by periodically
`
`incrementing and/or decrementing the determined power
`stage parameter value to search for a new power stage
`parameter value to increase the efficiency.
`0030. In some embodiments, selecting the determined
`power stage parameter value to increase the efficiency
`responsive to the feedback error signal change may occur by
`selecting a series of monotonically decreasing (or mono
`tonically increasing) power stage parameter values to search
`for a new power stage parameter value to increase the
`efficiency. Multiple power stages may be surveyed to select
`a plurality of associated determined power stage parameter
`values to increase the efficiency associated with one or more
`of the power stages.
`0031. In some embodiments, the method 211 may include
`determining the direction of change in the feedback error
`signal change at block 261, and then selecting a change
`direction of the determined power stage parameter based on
`the change direction of the feedback error signal change at
`block 271. For example, if the feedback error signal changes
`in a positive direction, a positive change in the determined
`power stage parameter value may be made (or a negative
`change, in some embodiments). Similarly, if the feedback
`error signal changes in a negative direction, a negative
`change in the determined power stage parameter value may
`be made (or a positive change, in Some embodiments). In
`Some cases, the method 211 may include detecting a failed
`regulator coupled to the power stage based on the feedback
`error signal change at block 281.
`0032 FIG. 3 is a flow diagram illustrating additional
`methods 311 for power conversion efficiency management
`according to various embodiments of the invention. For
`example, a method 311 may begin with measuring Ve (the
`current error voltage) at block 321. The method 311 may
`continue at block 331 with calculating the change in the
`error voltage Ve as the current error voltage Ve minus the
`previously-measured error Voltage Ve. The change in several
`other parameters may also be calculated, including any of
`the determined power stage control parameter values men
`tioned previously, such as the change in Switching frequency
`AFs, and the change in Switching dead time ATd.
`0033. As mentioned previously, the direction in which
`the error Voltage changes (e.g., the sign(AVe)) can be used
`to determine which direction to change one or more deter
`mined power stage parameter values. For example, a deter
`mination can be made at block 341 as to whether the
`direction of change in the error Voltage is the same as the
`direction of change in the Switching frequency (e.g., did AVe
`increase as Switching frequency Fs increased, or did AVe
`decrease as Switching frequency Fs decreased?). If so, then
`the method 311 may continue with block 351, to decrement
`the Switching frequency Fs. Similarly, a determination can
`be made as to whether the direction of change in the error
`Voltage is the same as the direction of change in the
`Switching dead time (e.g., did AVe increase as Switching
`dead time Td increased, or did AVe decrease as Switching
`dead time Td decreased?). If so, then the method 311 may
`continue with block 351, to decrement the switching dead
`time Td.
`0034. On the other hand, a determination can be made at
`block 341 as to whether the direction of change in the error
`voltage was in a different direction than that of the switching
`frequency (e.g., did AVe increase as Switching frequency Fs
`
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`Sep. 27, 2007
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`decreased, or did AVe decrease as Switching frequency Fs
`increased?). If so, then the method 311 may continue with
`block 361, to increment the switching frequency Fs. Simi
`larly, a determination can be made as to whether the direc
`tion of change in the error voltage is different than the
`direction of change in the Switching dead time (e.g., did AVe
`increase as Switching dead time Td decreased, or did AVe
`decrease as Switching dead time Td increased?). If so, then
`the method 311 may continue with block 361, to increment
`the Switching dead time Td. In either case, after increment
`ing or decrementing the Switching frequency FS or Switching
`dead time Td, the method 311 may go on to restart at block
`371, and (perhaps after a time delay at block 371) the
`method 311 may continue with a new measurement
`sequence at block 321.
`0035) It should be noted that the methods described
`herein do not have to be executed in the order described, or
`in any particular order. Moreover, various activities
`described with respect to the methods identified herein can
`be executed in repetitive, simultaneous, serial, or parallel
`fashion. Information, including parameters, commands,
`operands, and other data, can be sent and received in the
`form of one or more carrier waves.
`0.036 Upon viewing the content of this disclosure, one of
`ordinary skill in the art will understand the manner in which
`a Software program can be launched from a computer
`readable medium in a computer-based system to execute the
`functions defined in the software program. One of ordinary
`skill in the art will further understand the various program
`ming languages that may be employed to create one or more
`Software programs designed to implement and perform the
`methods disclosed herein. The programs may be structured
`in an object-orientated format using an object-oriented lan
`guage such as Java, Smalltalk, or C++. Alternatively, the
`programs can be structured in a procedure-orientated format
`using a procedural language. Such as assembly or C. The
`Software components may communicate using any of a
`number of mechanisms well known to those skilled in the
`art, such as application program interfaces or interprocess
`communication techniques, including remote procedure
`calls. The teachings of various embodiments are not limited
`to any particular programming language or environment,
`including Hypertext Markup Language (HTML) and Exten
`sible Markup Language (XML). Thus, other embodiments
`may be realized.
`0037 FIG. 4 is a block diagram of an article 485 for
`power conversion efficiency management according to vari
`ous embodiments, such as a computer, a memory system, a
`magnetic or optical disk, Some other storage device, and/or
`any type of electronic device or system. The article 485 may
`include a computer 487 (having one or more processors)
`coupled to a computer-readable medium 489, such as a
`memory (e.g., fixed and removable storage media, including
`tangible memory having electrical, optical, or electromag
`netic conductors) or a carrier wave, having associated infor
`mation 491 (e.g., computer program instructions and/or
`data), which when executed by the computer 487, causes the
`computer 487 to perform a method including Such actions as
`measuring an feedback error signal change as an indication
`of efficiency associated with a power stage, and selecting a
`determined power stage parameter value to increase the
`efficiency responsive to the feedback error signal change.
`0038 Further activities may include detecting a failed
`regulator coupled to the power stage based on the feedback
`error signal change, and Surveying multiple power stages,
`
`including the power stage, to select a plurality of associated
`determined power stage parameter values to increase effi
`ciency associated with the multiple power stages. Other
`activities may include any of those forming a portion of the
`methods illustrated in FIGS. 2 and 3, and described above.
`0039) Implementing the apparatus, systems, and methods
`disclosed herein may operate to reduce power losses of
`power converters and regulators used in computing and
`communications platforms, among others, in both stationary
`and mobile devices. Battery life may also be extended over
`more conventional Solutions due to higher efficiency under
`varying load conditions.
`0040. The accompanying drawings that form a part
`hereof show by way of illustration, and not of limitation,
`specific embodiments in which the subject matter may be
`practiced. The embodiments illustrated are described in
`sufficient detail to enable those skilled in the art to practice
`the teachings disclosed herein. Other embodiments may be
`utilized and derived therefrom, such that structural and
`logical Substitutions and changes may be made without
`departing from the scope of this disclosure. This Detailed
`Description, therefore, is not to be taken in a limiting sense,
`and the scope of various embodiments is defined only by the
`appended claims, along with the full range of equivalents to
`which such claims are entitled.
`0041. Such embodiments of the inventive subject matter
`may be referred to herein, individually and/or collectively,
`by the term “invention' merely for convenience and without
`intending to voluntarily limit the scope of this application to
`any single invention or inventive concept if more than one
`is in fact disclosed. Thus, although specific embodiments
`have been illustrated and described herein, it should be
`appreciated that any arrangement calculated to achieve the
`same purpose may be substituted for the specific embodi
`ments shown. This disclosure is intended to cover any and
`all adaptations or variations of various embodiments. Com
`binations of the above embodiments, and other embodi
`ments not specifically described herein, will be apparent to
`those of skill in the art upon reviewing the above descrip
`tion.
`0042. The Abstract of the Disclosure is provided to
`comply with 37 C.F.R. S1.72(b), requiring an abstract that
`will allow the reader to quickly ascertain the nature of the
`technical disclosure. It is submitted with the understanding
`that it will not be used to interpret or limit the scope or
`meaning of the claims. In addition, in the foregoing Detailed
`Description, it can be seen that various features are grouped
`together in a single embodiment for the purpose of stream
`lining the disclosure. This method of disclosure is not to be
`interpreted as reflecting an intention that the claimed
`embodiments require more features than are expressly
`recited in each claim. Rather, as the following claims reflect,
`inventive subject matter lies in less than all features of a
`single disclosed embodiment. Thus the following claims are
`hereby incorporated into the Detailed Description, with each
`claim standing on its own as a separate embodiment.
`
`1. An apparatus, including:
`measurement logic to measure a feedback error signal
`change as an indication of efficiency in a power stage;
`and
`performance governor logic to select a determined power
`stage control parameter to increase the efficiency
`responsive to the feedback error signal change.
`
`MyPAQ, Exhibit 2025
`IPR2022-00311
`Page 9 of 10
`
`

`

`US 2007/0222463 A1
`
`Sep. 27, 2007
`
`2. The apparatus of claim 1, wherein the power stage
`includes:
`
`a DC-DC converter.
`3. The apparatus of claim 1, wherein the determined
`power stage control parameter includes at least one of a
`Switching dead time, a Switching frequency, an input volt
`age, an output voltage, a number of active Switches, and a
`number of active power stages.
`4. The apparatus of claim 1, further including:
`a gain compensator coupled to the measurement logic.
`5. The apparatus of claim 1, further including:
`a plurality of power stages coupled to the performance
`governor logic.
`6. The apparatus of claim 5, wherein the feedback error
`signal change comprises an output voltage error change.
`7. A system, including:
`measurement logic to measure a feedback error signal
`change as an indication of efficiency in a power stage;
`performance governor logic to select a determined power
`stage control parameter to increase the efficiency
`responsive to the feedback error signal change; and
`a display to receive power from the power stage.
`8. The system of claim 7, further including:
`a computer motherboard to receive power from the power
`Stage.
`9. The system of claim 7, further including:
`a television tuner to receive power from the power stage.
`10. The system of claim 7, further including:
`a medical data acquisition system to receive power from
`the power stage.
`11. The system of claim 7, wherein the power stage
`includes at least one of a buck converter and a boost
`converter.
`12. A method, comprising:
`measuring a feedback error signal change as an indication
`of efficiency associated with a power stage; and
`Selecting a determined power stage parameter value to
`increase the efficiency responsive to the feedback error
`signal change.
`
`13. The method of claim 12, further including:
`selecting a change direction of the determined power
`stage parameter based on a change direction of the
`feedback error signal change.
`14. The method of claim 12, further including:
`reading a register to determine an acceptable efficiency
`associated with the power stage.
`15. The method of claim 12, further including:
`selecting a trial determined power stage parameter value
`if the efficiency is less than an acceptable efficiency.
`16. The method of claim 12, further including:
`periodically incrementing the determined power stage
`parameter value to search for a new power stage
`parameter value to increase the efficiency.
`17. The method of claim 12,