R. JACOB (JAKE) BAKER, PH.D., P.E.
`Professor of Electrical and Computer Engineering
`
`6775 Agave Azul Court
`Las Vegas, NV 89120
`
`(725) 777-3755 (Home Office)
`(208) 850-0517 (Cell)
`
`Email: rjacobbaker@gmail.com
`Website: http://CMOSedu.com/jbaker/jbaker.htm
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`PROFESSIONAL SUMMARY
`Russel Jacob (Jake) Baker, Ph.D., P.E. (IEEE Student Member 1983, Member 1988, Senior Member 1997, and Fellow
`2013) was born in Ogden, Utah, on October 5, 1964. He received the B.S. and M.S. degrees in electrical engineering
`from the University of Nevada, Las Vegas, in 1986 and 1988. He received the Ph.D. degree in electrical engineering
`from the University of Nevada, Reno in 1993. His Google Scholar profile is here and his ResearchGate profile is
`here.
`From 1981 to 1987 he served in the United States Marine Corps Reserves (Fox Company, 2nd Battalion, 23rd Marines,
`4th Marine Division). From 1985 to 1993 he worked for E. G. & G. Energy Measurements and the Lawrence
`Livermore National Laboratory designing nuclear diagnostic instrumentation for underground nuclear weapons
`tests at the Nevada Test Site. During this time, he designed, and oversaw the fabrication and manufacture of, over
`30 electronic and electro-optic instruments including high-speed cable and fiber-optic receiver/transmitters, PLLs,
`frame- and bit-syncs, data converters, streak-camera sweep circuits, Pockels cell drivers, micro-channel plate
`gating circuits, and analog oscilloscope electronics. From 1991-1992 he was an adjunct faculty member in the
`department of electrical engineering at the University of Nevada, Las Vegas (UNLV). From 1993 to 2000 he served
`on the faculty in the department of electrical engineering at the University of Idaho (UI), first as an untenured
`Assistant Professor and then from 1998 as a tenured Associate Professor. In 2000 he joined a new electrical and
`computer engineering (ECE) program at Boise State University (BSU) where he was promoted to Full Professor in
`2002. He then served as the ECE department chair at BSU from 2004 to 2007. At BSU he helped establish graduate
`programs in ECE including, in 2006, the university’s second PhD degree. In 2012 he re-joined the faculty at UNLV
`as a tenured Full Professor of ECE. During his service at the UI, BSU, and UNLV he has been the major professor to
`more than 100 graduate students. In addition to this industry and academic experience, he has done consulting,
`both technical and expert witness, for over 125 companies and laboratories.
`Over the last 35+ years his research/development interests and publications have been, or currently are, focused on:
`analog-to-digital/digital-to-analog data conversion and transmission, optoelectronics (imagers, displays, LIDARs,
`APDs, SiPMs, and associated electronics), analog and digital integrated circuit design and fabrication, design of
`diagnostic electrical and electro-optic instrumentation for scientific research, integrated electrical/biological
`circuits and systems, array (memory, imagers, and displays) fabrication and design, CAD tool development and
`online tutorials,
`low-power
`interconnect and packaging (electrical and optical) techniques, design of
`wired/wireless communication and interface circuits, circuit design for the use and storage of renewable energy,
`power electronics and power supply design, and the delivery of online engineering education.
`Dr. Baker is the named inventor on over 150 US patents. He is a member of the honor societies Eta Kappa Nu and Tau
`Beta Pi, a licensed Professional Engineer, a popular lecturer that has delivered over 50 invited talks around the
`world, an IEEE Fellow, and the author of the books CMOS Circuit Design, Layout, and Simulation, CMOS Mixed-
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`Signal Circuit Design, and a coauthor of DRAM Circuit Design: Fundamental and High-Speed Topics. He received
`the 2000 Best Paper Award from the IEEE Power Electronics Society, the 2007 Frederick Emmons Terman Award,
`the 2011 IEEE Circuits and Systems Education Award and the 2021 Wiley-IEEE Press Textbook Award for the 4th
`Edition of his book CMOS Circuit Design, Layout, and Simulation.
`His service activities include the IEEE Press Editorial Board (1999-2004), editor for the Wiley-IEEE Press Book Series on
`Microelectronic Systems (2010-2018), the Technical Program Chair of the 2015 IEEE 58th International Midwest
`Symposium on Circuits and Systems (MWSCAS 2015), the IEEE Solid-State Circuits Society (SSCS) Administrative
`Committee (2011-2016), Distinguished Lecturer for the SSCS (2012-2015), Technology Editor (2012-2014) and
`Editor-in-Chief (2015-2020) for the IEEE Solid-State Circuits Magazine, IEEE Kirchhoff Award Committee (2020-
`present), and advisor for the student branch of the IEEE at UNLV (2013-present).
`INDUSTRY EXPERIENCE
`2013 - present: Working with Freedom Photonics, Santa Barbara, CA, on the integration, fabrication and design, of
`optoelectronics with CMOS integrated circuits. Work includes the design of compact optical transceivers for range
`finding applications, high-efficiency integrated silicon avalanche photodetectors for quantum key receivers,
`Geiger mode SiGe receivers for long-range communications, cryptography, and the fabrication of near-infrared
`focal plane arrays. Packaging and testing of numerous chips fabricated in both CMOS and SiGe technologies using
`LEDs, ILDs, PIN, APDs, and ROICs.
`2009 - present: Expert witness in intellectual property disputes in electrical, electro-optic, and computer engineering
`matters for: 1) district court and ITC patent disputes, 2) inter partes reviews at the PTAB, and 3) arbitrations and
`mediations.
`2017 - 2019: Worked with Vorpal Research Systems, Las Vegas, NV on the design of integrated circuit electronics and
`optoelectronics for optical transceivers used in LIDARs/LADARs.
`2016 - 2019: Worked with Attollo Engineering on the design of transient digitizers for the capture of high-speed signals
`for range finders using LEDs and lasers in compact optical transceivers.
`2013 - 2018: Working with Mission Support and Test Services, LLC (MSTS, formerly National Security Technologies,
`LLC, [NSTec]) on the Design and Fabrication of Integrated electrical/photonic application specific integrated circuit
`(ASIC) design for use in the implementation of diagnostic instrumentation.
`2013 - 2015: Consultant for OmniVision. Working on integrating CMOS image sensors (CIS) with memory for very high-
`speed consumer imager products. Design specialty DRAM, high-speed interfaces between CIS and DRAM,
`packaging techniques to pair the CIS with DRAM.
`2010 - 2013: Worked with Arete’ Associates on the design of high-speed compressive transimpedance amplifiers for
`LADAR projects and the design of ROIC unit cells. Work funded by the U. S. Air Force.
`2013: Cirque, Inc. Consulting on the design of analog-to-digital interfaces for capacitive touch displays and pads.
`2012: Consultant at Lockheed-Martin Santa Barbara Focal Plane Array. CMOS circuit design and fabrication for the
`development and manufacture of infrared components and imaging systems with an emphasis on highest
`sensitivity Indium Antimonide (InSb) focal plane arrays (FPAs) in linear through large staring formats. Product
`groups include FPAs, integrated dewar assemblies (IDCAs), camera heads, high-speed interfaces between image
`processors and imaging systems, and infrared imaging systems.
`2010 - 2012: Working with Aerius Photonics (and then FLIR Inc. when Aerius was purchase by FLIR) on the design of
`Focal Plane Arrays funded (SBIRs and STTRs) by the U.S. Air Force, Navy, and Army. Experience with readout
`integrated circuits (ROICs) and the design/layout of photodetectors in standard CMOS.
`2009 - 2010: Sun Microsystems, Inc. (and then Oracle) VLSI research group. Provided consulting on memory circuit
`design/fabrication and proximity connection (PxC) interfaces to DRAMs and SRAMs for lower power, 3D
`packaging, for memory modules and controllers implemented with FPGAs and custom ASICs.
`2009 - 2010: Contour Semiconductor, Inc. Design of NMOS voltage and current references as well as the design of a
`charge pump for an NMOS memory chip.
`1994 - 2008: Affiliate faculty (Senior Designer), Micron Technology. Designed CMOS circuits for DRAMs including DLLs,
`PLLs for embedded graphics chips, voltage references and regulators, data converters, field-emitting display
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`drivers, sensing for MRAM (using delta-sigma data conversion topologies), SRAMs, RFIDs, CMOS active pixel
`imagers and sensors, power supply design (linear and switching), input buffers, etc. Worked on a joint research
`project between Micron and HP labs in magnetic memory fabrication and design using the MTJ memory cell.
`Worked on numerous technologies ranging from LED lighting to medical imaging using CMOS image sensors (too
`many to list) resulting in numerous US patents (see following list). Considerable experience working with product
`engineering to ensure high-yield from the production line from fabrication to test. Co-authored a book on DRAM
`circuit design through the support of Micron. Gained knowledge in the entire memory design process from
`fabrication to packaging. Developed, designed, and tested circuit design techniques for multi-level cell (MLC) Flash
`memory using signal processing.
`January 2008: Consultant for Nascentric located in Austin, TX. Provide directions on circuit operation (DRAM, memory,
`and mixed-signal) for fast SPICE circuit simulations.
`May 1997 - May 1999: Consultant for Tower Semiconductor, Haifa, Israel. Designed CMOS integrated circuit cells for
`various modem chips, interfaces, and serial buses including USB circuits, charging circuits based upon power
`up/down circuits using an MOS or bandgap reference, pre-amplifiers, comparators, etc.
`Summer 1998: Consultant for Amkor Wafer Fabrication Services, Micron Technology, and Rendition, Inc., Design PLLs
`and DLLs for custom ASICs and a graphics controller chip.
`Summers 1994 - 1995: Micron Display Inc. Designing phase locked loop for generating a pixel clock for field emitting
`displays and a NTSC to RGB circuit on chip in NMOS. These displays are miniature color displays for camcorder and
`wrist watch size color television. Worked on the fabrication and design of video peripheral circuits for these
`displays.
`September - October 1993: Lawrence Berkeley Laboratory. Designed and constructed a 40 A, 2 kV power MOSFET
`pulse generator with a 3 ns rise-time and 8 ns fall-time for driving Helmholtz coils.
`Summer 1993: Lawrence Livermore National Laboratory, Nova Laser Program. Researched picosecond
`instrumentation, including time-domain design for impulse radar and imaging.
`December 1985 - June 1993: (from July 1992 to June 1993 employed as a consultant while finishing up my Ph.D.),
`E.G.&G. Energy Measurements Inc., Nevada, Senior Electronics Design Engineer. Responsible for the design and
`manufacturing of instrumentation used in support of Lawrence Livermore National Laboratory's Nuclear Test
`Program. Responsible for designing and fabricating over 30 electronic and electro-optic instruments including:
`CCD camera design, communication networks, fiber optic transmitters employing high speed laser drive
`electronics, receivers employing envelop tracking for DC voltage restoration and regeneration of received
`information, receiver low noise amplifier design, frame synchronizers for re-assembling transmitted images, high-
`speed SRAM memory system design with battery back-up, calibration equipment design such as a tunnel diode
`pulse generator for testing compensation of oscilloscopes and DAC design for calibrating CCD readout electronics,
`power supply and battery charger designs, sweep circuits for streak cameras, Pockel’s cell drive electronics,
`vertical amplifier design using HBTs for analog oscilloscopes used at the Nevada Test Site, and 10 kV ramp designs
`using a planar triode to name some of the designs.
`This position provided considerable fundamental grounding in EE with a broad exposure ranging from the design
`of PC boards to, for example, the design of cable equalizers. Summarizing, gained experience in circuit design
`technologies including: bipolar, vacuum tubes (planar triodes for high voltages), hybrid integrated circuit
`fabrication and design, GaAs (high speed logic and HBTs), Mach-Zehnder interferometers, Pockels cells, krytrons,
`power MOSFETs, microwave techniques, power supplies, fiber optic transmitters/receivers, etc.
`Summer 1985: Reynolds Electrical Engineering Company, Las Vegas, Nevada. Gained hands on experience in primary
`and secondary power system design, installation and trouble-shooting electric motors on mining equipment.
`ACADEMIC EXPERIENCE
`January 1991 - Present: Professor of Electrical and Computer Engineering at the University of Nevada, Las Vegas from
`August 2012 to present. From January 2000 to July 2012 held various positions at Boise State University including:
`Professor (2003 – 2012), Department Chair (2004 - 2007), and tenured Associate Professor (2000 - 2003). From
`August 1993 to January 2000 was a tenured/tenure track faculty member at the University of Idaho: Assistant
`Professor (1993 - 1998) and then tenured Associate Professor (1998 - 2000). Lastly, from January 1991 to May
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`R. JACOB BAKER, PH.D., P.E.
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`1993 held adjunct faculty positions in the departments of Electrical Engineering at the University of Nevada, Las
`Vegas and Reno. Additional details:
`• Research is focused on analog and mixed-signal integrated circuit fabrication and design. Worked with multi-
`disciplinary teams (civil engineering, biology, materials science, etc.) on projects that have been funded by
`EPA, DARPA, NASA, Army, DMEA, Navy, and the AFRL.
`• Current and past research and development interests are:
`o Design and packaging of electrical/optical systems (e.g., LiDARs/LADARs) using LEDs, semiconductor
`lasers, lens for focusing and directing light, integrated circuits, and associated control and communication
`systems/circuits.
`o Capacitive sensing techniques using delta-sigma modulation and interfacing to sensors
`o Design of high-voltage and energy switching circuits
`o Circuit design and fabrication for the control, use, and storage of renewable energy using thermoelectric
`generators
`o Design of electrical/biological/optical circuits and systems using electrowetting on dielectric for
`automating and controlling biological experiments
`o Design of readout integrated circuits (ROICs) for use with focal plane arrays (FPAs)
`o Heterogeneous integration of III-V photonic devices (e.g., FPAs and VCSELs) with CMOS
`in
`o Methods (e.g., 3D packaging and capacitive
`interconnects) to reduce power consumption
`semiconductor memories, memory modules, and digital systems using custom and non-custom (e.g.,
`FPGAs) implementations
`o Analog and mixed-signal circuit fabrication and design for communication systems, synchronization,
`energy storage, data conversion, and interfaces
`o The design of writing and sensing circuitry for emerging nonvolatile memory technologies, focal planes,
`and displays (arrays) in nascent nanotechnologies (e.g., magnetic, chalcogenide)
`o Reconfigurable electronics design and fabrication using nascent memory technologies such as the
`memristor to implement FPGAs
`o Finding an electronic, that is, no mechanical component, replacement for the hard disk drive using nascent
`fabrication technologies
`o Power electronics circuit design for consumers and consumer electronics including power management
`and adaptive control to reduce power consumption
`o Design of bandpass delta-sigma modulators for IQ demodulation in wireless communication systems in
`OFDM, WiFi, 802.11, Bluetooth, 3G, 4G, etc.
`o University prototyping, fabricating, and packaging of integrated circuits
`Led, as chair, the department in graduate curriculum (MS and PhD), program development, and ABET
`accreditation visits.
`• Worked with established and start-up companies to provide technical expertise and identify employment
`opportunities for students.
`• Held various leadership and service positions including: ECE chair, graduate coordinator, college curriculum
`committee (chair), promotion and tenure committee, scholarly activities committee, faculty search
`committee, university level search committees, etc. Collaborate with College of Engineering faculty on joint
`research projects.
`• Taught courses in circuits, analog IC design, digital VLSI design and fabrication, fiber optics, and mixed-signal
`integrated circuit design to both on- and, via the Internet, off-campus students. Research emphasis in
`integrated circuit design using nascent technologies.
`EDUCATION
`
`•
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`• Ph.D. in Electrical Engineering; December 1993; University of Nevada, Reno, GPA 4.0/4.0. Dissertation Title:
`Applying power MOSFETs to the design of electronic and electro-optic instrumentation.
`• M.S. and B.S. in Electrical Engineering: May 1986 and May 1988; University of Nevada, Las Vegas. Thesis Title:
`Three-dimensional simulation of a MOSFET including the effects of gate oxide charge.
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`R. JACOB BAKER, PH.D., P.E.
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`MEMBERSHIPS IN PROFESSIONAL AND SCHOLARLY ORGANIZATIONS
`IEEE (student, 1983; member, 1988; senior member, 1997; Fellow, 2013)
`Member of the honor societies Eta Kappa Nu and Tau Beta Pi
`Licensed Professional Engineer
`
`•
`
`HONORS AND AWARDS
`Consolidated Students of the University of Nevada, Las Vegas (CSUN) Faculty Award, 2017
`Tau Beta Pi UNLV Outstanding Professor of the Year in 2013, 2014, 2015 and 2016
`•
`• UNLV ECE Department Distinguished Professor of the Year in 2015
`IEEE Fellow for contributions to the design of memory circuits - 2013
`•
`• Distinguished Lecturer for the IEEE Solid-State Circuits Society, 2012 - 2015
`IEEE Circuits and Systems (CAS) Education Award - 2011
`•
`Twice elected to the Administrative Committee of the Solid-State Circuits Society, 2011 - 2016
`Frederick Emmons Terman Award from the American Society of Engineering Education - 2007
`President’s Research and Scholarship Award, Boise State University - 2005
`•
`• Honored Faculty Member - Boise State University Top Ten Scholar/Alumni Association 2003
`• Outstanding Department of Electrical Engineering faculty, Boise State 2001
`Recipient of the IEEE Power Electronics Society’s Best Paper Award in 2000
`•
`• University of Idaho, Department of Electrical Engineering outstanding researcher award, 1998-99
`• University of Idaho, College of Engineering Outstanding Young Faculty award, 1996-97
`
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`•
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`•
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`SERVICE
`Reviewer for IEEE transactions on solid-state circuits, circuits and devices magazine, education, instrumentation,
`nanotechnology, VLSI, etc. Reviewer for several American Institute of Physics journals as well (Review of Scientific
`Instruments, Applied Physics letters, etc.) Board member of the IEEE press (reviewed dozens of books and book
`proposals). Reviewer for the National Institutes of Health. Technology editor and then Editor-in-Chief for the Solid-
`State Circuits Magazine.
`
`Led the Department on ABET visits, curriculum and policy development, and new program development including the
`PhD in electrical and computer engineering. Provided significant University and College service in infrastructure
`development, Dean searches, VP searches, and growth of academic programs. Provided university/industry
`interactions including starting the ECE department’s advisory board. Held positions as the ECE department
`Master’s graduate coordinator and coordinator for the Sophomore Outcomes Assessment Test (SOAT).
`
`Also currently serves, or has served, on the IEEE Press Editorial Board (1999-2004), as a member of the first Academic
`Committee of the State Key Laboratory of Analog and Mixed-Signal VLSI at the University of Macau, as editor for
`the Wiley-IEEE Press Book Series on Microelectronic Systems (2010-2018), on the IEEE Solid-State Circuits Society
`(SSCS) Administrative Committee (2011-2016), as an Advisory Professor to the School of Electronic and
`Information Engineering at Beijing Jiaotong University, as a Distinguished Lecturer for the SSCS (2012-2015), as
`the Technical Program Chair for the IEEE 58th 2015 International Midwest Symposium on Circuits and Systems,
`MWSCAS 2015, as advisor for the student branch of the IEEE at UNLV (2013-present), and as the Technology Editor
`(2012-2014) and Editor-in-Chief (2015-2020) for the IEEE Solid-State Circuits Magazine, and IEEE Kirchhoff Award
`Committee (2020-present).
`
`ARMED FORCES
`6 years United States Marine Corps reserves (Fox Company, 2nd Battalion, 23rd Marines, 4th Marine Division),
`Honorable Discharge, October 23, 1987. Military Occupational Specialty was Machine Gunner (MOS 0331)
`
`TEXTBOOKS AUTHORED
`Baker, R. J., "CMOS Circuit Design, Layout and Simulation, Fourth Edition" Wiley-IEEE Press, 1234 pages. ISBN
`9781119481515 (2019) Over 50,000 copies of this book in print. (Third Edition published in 2010, Revised Second
`Edition published in 2008, and Second Edition Published in 2005)
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`R. JACOB BAKER, PH.D., P.E.
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`Baker, R. J., “CMOS Mixed-Signal Circuit Design,” Wiley-IEEE, 329 pages. ISBN 978-0470290262 (second edition, 2009)
`and ISBN 9780471227540 (First Edition published in 2002)
`Keeth, B., Baker, R. J., Johnson, B., and Lin, F., “DRAM Circuit Design: Fundamental and High-Speed Topics”, Wiley-
`IEEE, 2008, 201 pages. ISBN: 9780470184752
`Keeth, B. and Baker, R. J., “DRAM Circuit Design: A Tutorial”, Wiley-IEEE, 2001, 201 pages. ISBN 0780360141
`Baker, R. J., Li, H.W., and Boyce, D.E. "CMOS Circuit Design, Layout and Simulation," Wiley-IEEE, 1998, 904 pages. ISBN
`9780780334168
`
`BOOKS, OTHER (edited, chapters, etc.)
`Saxena, V. and Baker, R. J., “Analog and Digital VLSI,” chapter in the CRC Handbook on Industrial Electronics, edited by
`J. D. Irwin and B. D. Wilamowski, CRC Press, 2009 second edition.
`Baker, R. J., “CMOS Analog Circuit Design,” (A self-study course with study guide, videos, and tests.) IEEE Education
`Activity Department, 2000. ISBN 0-7803-4822-2 (with textbook) and ISBN 0-7803-4823-0 (without textbook)
`Baker, R. J., “CMOS Digital Circuit Design,” (A self-study course with study guide, videos, and tests.) IEEE Education
`Activity Department, 2000. ISBN 0-7803-4812-5 (with textbook) and ISBN 0-7803-4813-3 (without textbook)
`
`Li, H.W., Baker, R. J., and Thelen, D., “CMOS Amplifier Design,” chapter 19 in the CRC VLSI Handbook, edited by Wai-
`kai Chen, CRC Press, 1999 (ISBN 0-8493-8593-8) and the second edition in 2007 (ISBN 978-0-8493-4199-1)
`
`INVITED TALKS AND SEMINARS
`Have given over 50 invited talks and seminars at the following locations: AMD (Fort Collins), AMI semiconductor,
`Arizona State University, Beijing Jiaotong University, Boise State University, Carleton University, Carnegie Mellon,
`Columbia University, Dublin City University (Ireland), E.G.&G. Energy Measurements, Foveon, the Franklin
`Institute, Georgia Tech, Gonzaga University, Hong Kong University of Science and Technology, ICSEng Keynote,
`ICySSS keynote, IEEE Computing and Communication Workshop (CCWC), IEEE Electron Devices Conference
`(NVMTS), IEEE Workshop on Microelectronics and Electron Devices (WMED), Indian Institute of Science
`(Bangalore, India), Instituto de Informatica (Brazil), Instituto Tecnológico y de Estudios Superiores de Monterrey
`(ITESM, Mexico), Iowa State University, Lawrence Livermore National Laboratory, Lehigh University, Lockheed-
`Martin, Micron Technology, Nascentric, National Semiconductor, Princeton University, Rendition, Saintgits
`College
`(Kerala,
`India), Southern Methodist University, Sun Microsystems, Stanford University, ST
`Microelectronics (Delhi, India), Temple University, Texas A&M University, Tower Semiconductor (Israel),
`University of Alabama (Tuscaloosa), University of Arkansas, University of Buenos Aires (Argentina), University of
`Houston, University of Idaho, University of Illinois (Urbana-Champaign), Université Laval (Québec City, Québec),
`University of Macau, University of Maryland, Université de Montréal (École Polytechnique de Montréal), Xilinx
`(Ireland), University of Nevada (Las Vegas), University of Nevada (Reno), University of Toronto, University of Utah,
`Utah State University, and Yonsei University (Seoul, South Korea).
`
`RESEARCH FUNDING (LAST 5 YEARS AS A PROFESSOR)
`Recent funding listed below. In-kind, equipment, and other non-contract/grant funding [e.g., MOSIS support, money
`for travel for invited talks, etc.] not listed.
`• Baker, R. Jacob, (2017-2023) "Tiled Silicon Photomultiplier Array Read-Out Integrated Circuit," NASA, $29,999
`(Phase I), $225,238 (Phase II), and $79,697 (Phase IIE)
`• Goldman, J., Menezes, J., and Baker, R. J., (2021-2022) "Monitored Compression Therapy: Using Smart Technology
`to Optimize the Treatment of Lower Extremity Swelling," UNLV Sports Research & Innovation Initiative. Proof of
`Concept Grant Program, $50,000
`• Baker, R. Jacob, (2019-2021) "Dual-Mode, Extended Near-Infrared, Focal Plane Arrays Fabricated with CMOS
`Compatible GeSiSn Alloy Materials," DARPA, $149,998
`• Baker, R. Jacob, (2018-2020) “Geiger Mode SiGe Receiver for Long-Range Optical Communications,” NASA,
`$99,996
`• Baker, R. Jacob, (2019) "Improved Quantum Efficiency Photo-Detector," Navy, $29,999
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`R. JACOB BAKER, PH.D., P.E.
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`7.
`6.
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`• Baker, R. Jacob, (2018-2019) "Tiled Silicon Photomultiplier Array Read-Out Integrated Circuit – Phase I," NASA,
`$29,999
`• Baker, R. Jacob, (2017-2019) "Quantum Cryptography Detector Chip," Defense MicroElectronics Activity (DMEA),
`$266,029
`• Baker, R. Jacob, (2017-2019) “Advanced Printed Circuit Board Design Methods for Compact Optical Transceiver,”
`U.S. Army/DOD, $299,605
`• Baker, R. Jacob, (2016-2018) "High-Sensitivity Monolithic Silicon APD and ROIC," U.S. Air Force/DOD, $299,665
`• Baker, R. Jacob, (2017-2018) "Transimpedance Amplifier Integrated Circuit Collaboration," Department of Energy,
`National Security Technologies, LLC, $100,436
`• Baker, R. Jacob, (2017) “Geiger Mode SiGe Receiver for Long-Range Optical Communications,” NASA, $30,000
`• Baker, R. Jacob, (2016-2017) "Testing and development of BiCMOS photodetectors and diagnostic
`instrumentation," Department of Energy, National Security Technologies, LLC, $181,605
`• Baker, R. Jacob, (2016-2017) "Dual-Mode, Extended Near Infrared, Focal Plane Arrays fabricated with a
`Commercial SiGe BiCMOS Process," DARPA, $41,892
`DOCTORAL STUDENT SUPERVSION
`11. Mario Valles Montenegro (underway)
`10. Sachin Namboodiri – A Multi-channel MCP-PMT based Readout Integrated Circuit for LiDAR Applications (2020)
`9. Wenlan Wu – High-Speed Radhard Mega-Pixel CIS Camera for High-Energy Physics (2019)
`8.
`Kostas Moutafis – A Highly-Sensitive Global-Shutter CMOS Image Sensor with On-Chip Memory for Hundreds of
`kilo-frames per second Scientific Experiments (2019)
`Yiyan Li – Portable High Throughput Digital Microfluidics and On-Chip Bacteria Cultures (2016)
`Yacouba Moumouni – Designing, Building, and Testing a Solar Thermoelectric Generation, STEG, for Energy
`Delivery to Remote Residential Areas in Developing Regions (2015)
`5. Qawi IbnZayd Harvard – Low-Power, High-Bandwidth, and Ultra-Small Memory Module Design (2011)
`4.
`Vishal Saxena – K-Delta-1-Sigma Modulators for Wideband Analog-to-Digital Conversion (2010)
`3.
`Robert Russell Hay – Digitally-Tunable Surface Acoustic Wave Resonator (2009)
`2.
`Xiangli Li (the first Boise State University College of Engineering PhD graduate) – MOSFET Modulated Dual
`Conversion Gain CMOS Image Sensors (2008)
`1.
`Feng Lin, Research and Design of Low Jitter, Wide Locking-Range Phase-Locked and Delay-Locked Loops (2000)
`MASTERS STUDENT SUPERVISION
`92. Armani Alvarez (underway)
`91. Khulan Tsogt (underway)
`90.
`Jazmin Boloor (underway)
`89. Minsung Cho (underway)
`88. Chris Barr (underway)
`87. David Santiago (underway)
`86. Francisco Mata-carlos (underway)
`85. Daniel Senda – Designs and Outcomes of Transcranial Magnetic Stimulation (TMS) and Repetitive Transcranial
`Magnetic Stimulation (rTMS) Circuits
`James Skelly – Monitored Compression Therapy: Using Smart Technology to Optimize the Treatment of Lower
`Extremity Swelling
`83. Gonzalo Arteaga – Current-mode photon-counting circuit with SiGe BiCMOS input stage (2020)
`82. Jason Silic – Design and Fabrication of a 6-bit Current-Mode ADC for Lidar and High-Speed Applications (2020)
`81. Brandon Wade (2020)
`80. Mario Valles Montenegro – Front-End CMOS Transimpedance Amplifiers on a Silicon Photomultiplier Resistant
`to Fast Neutron Fluence (2020)
`Jonathan DeBoy (2018)
`79.
`78. Dane Gentry – Design, Layout, and Testing of SiGe APDs Fabricated in a BiCMOS Process (2018)
`77.
`James Mellot – Variable Transition Time Inverters in a Digital Delay Line with Analog Storage for Processing Fast
`Signals and Pulses (2018)
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`84.
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`R. JACOB BAKER, PH.D., P.E.
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`76. Eric Monahan – High Speed Fast Transient Digitizer Design and Simulation (2018)
`75. Shada Sharif – Design and Analysis of First and Second Order K-Delta-1-Sigma Modulators in Multiple Fabrication
`Processes (2018)
`74. Vikas Vinayaka – Analysis and Design of Analog Front-End Circuitry for Avalanche Photodiodes (APD) and Silicon
`Photo-Multipliers (SiPM) in Time-of-Flight Applications (2018)
`73. Claire Tsagkari – Design, Fabrication and Testing of a Capacitive Sensor Using Delta-Sigma Modulation (2017)
`72. Kevin Buck – Fast Transient Digitizer and PCB Interface (2015)
`71. Marzieh Sharbat Maleki (2015)
`70. Angsuman Roy – Design, Fabrication and Testing of Monolithic Low-Power Passive Sigma-Delta Analog-to-Digital
`Converters (2015)
`69. Daniel Anderson – Design and Implementation of an Instruction Set Architecture and Instruction Execution Unit
`for the RZ9 Coprocessor System (2014)
`Jared Gordon – Design and Fabrication of an Infrared Optical Pyrometer ASIC (2013)
`68.
`Justin Butterfield (2012)
`67.
`66. Adam Johnson – Methods and Considerations for Testing Resistive Memories (2012)
`65. Ben Millemon – CMOS Characterization, Modeling, and Circuit Design in the Presence of Random Local Variation
`(2012)
`Justin Wood (2012)
`64.
`63. Chamunda Ndinawe Chamunda (2011)
`62. Gary VanAckern – Design Guide for CMOS Process On-Chip 3D Inductors using Thru-Wafer Vias (2011)
`61. Lucien Jan Bissey – High-Voltage Programmable Delta-Sigma Modulation Voltage-Control Circuit (2010)
`60. Kaijun Li (2010)
`59. Yingting Li (co-supervised with Maria Mitkova) (2010)
`58. Lael Matthews (co-supervised with Said Ahmed-Zaid) (2010)
`57. Priyanka Mukeshbhai Parikh (2010)
`56. Todd Plum (co-supervised with Jeff Jessing) – Design and Fabrication of a Chemicapacitive Sensor for the
`Detection of Volatile Organic Compounds (2010)
`55. Rahul Srikonda (2010)
`54. Avani Falgun Trivedi (2010)
`53. Kuang Ming Yap – Gain and Offset Error Correction for CMOS Image Sensors using Delta-Sigma Modulation
`(2010)
`52. Mahesh Balasubramanian – Phase Change Memory - Array Development and Sensing Circuits using Delta-Sigma
`Modulation (2009)
`51. Lincoln Bollschweiler (2009)
`50. Shantanu Gupta (2009)
`49. Qawi Harvard – Wide I_O DRAM Architecture Utilizing Proximity Communication (2009)
`48. Avinash Rajagiri (2009)
`47. Ramya Ramarapu (2009)
`46. Harikrishna Rapole (2009)
`45. Aruna Vadla (2009)
`44. Hemanth Ande (2008)
`43. Curtis Cahoon – Low-Voltage CMOS Temperature Sensor Design using Schottky Diode-Based References (2008)
`42. Prashanth Busa (2008)
`41.
`John McCoy III (2008)
`40. Dennis Montierth – Using Delta-Sigma-Modulation for Sensing in a CMOS Imager (2008)
`39. Rudi Rashwand (2008)
`38. Barsha Shrestha (co-supervised with Zhu Han) – Wireless Access in Vehicular Environments using Bit Torrent and
`Bargaining (2008)
`37. Eric Becker – Design of an Integrated Half-Cycle Delay Line Duty Cycle Corrector Delay Locked Loop (2007)
`36. Matthew Leslie – Noise-Shaping Sense Amplifier for Cross-Point Arrays (2007)
`35.
`Jose Monje (2007)
`
`R. JACOB BAKER, PH.D., P.E.
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`Page 8
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`Unified Patents Exhibit 1004
`Page 8 of 37
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`34. Sanghyun Park (2007)
`33. Vishal Saxena – Indirect Feedback Compensation Techniques for Multi-Stage Operational Amplifiers (2007)
`32. Meshack Appikatla