UNITED STATES PATENT AND TRADEMARK OFFICE
`
`———————
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`———————
`
`UNIFIED PATENTS, LLC
`
`Petitioner
`
`- v. –
`
`ARIGNA TECHNOLOGY LIMITED
`
`Patent Owner
`
`———————
`
`IPR2022-00285
`
`U.S. Patent 7,049,850
`
`DECLARATION OF R. JACOB BAKER, PH.D., P.E., UNDER 37 C.F.R. § 1.68
`
`IN SUPPORT OF PETITION FOR INTER PARTES REVIEW OF
`
`U.S. PATENT NO. 7,049,850
`
`1
`
`Unified Patents EX1003
`
`Unified Patents Exhibit 1003
`Page 1 of 99
`
`

`

`Declaration of R. Jacob Baker, Ph.D, P.E., Under 37 C.F.R. § 1.68 in Support of
`Petition for Inter Partes Review of U.S. Patent No. 7,049,850
`
`
`TABLE OF CONTENTS
`Introduction ...................................................................................................... 4
`
`I.
`
`II.
`
`Background and Qualifications ....................................................................... 7
`
`Industry Experience ............................................................................... 8
`A.
`Academic Experience .......................................................................... 12
`B.
`Other Relevant Experience .................................................................. 14
`C.
`III. Understanding of Patent Law ........................................................................ 15
`
`IV. The ’850 Patent and Relevant Background ................................................... 20
`
`Summary of the ’850 Patent ................................................................ 20
`A.
`Claim 7 and the Second Embodiment ................................................. 23
`B.
`Prosecution History ............................................................................. 27
`C.
`Level of Ordinary Skill in the Pertinent Art .................................................. 30
`
`V.
`
`VI. Claim Construction ........................................................................................ 32
`
`VII. Detailed Invalidity Analysis .......................................................................... 34
`
`A. Ground 1: Claim 7 would have been obvious in view of
`Majumdar and Cowles ........................................................................ 35
`1.
`The Prior Art References ......................................................... 36
`a)
`Overview of Majumdar ................................................. 36
`b)
`Overview of Cowles ....................................................... 55
`Unpatentability Analysis of Claim 7 ....................................... 57
`2.
`VIII. Availability for cross-examination ................................................................ 98
`
`
`
`2
`
`Unified Patents EX1003
`
`Unified Patents Exhibit 1003
`Page 2 of 99
`
`

`

`Declaration of R. Jacob Baker, Ph.D, P.E., Under 37 C.F.R. § 1.68 in Support of
`Petition for Inter Partes Review of U.S. Patent No. 7,049,850
`
`IX. Conclusion ..................................................................................................... 99
`
`
`
`
`
`
`
`
`3
`
`Unified Patents EX1003
`
`Unified Patents Exhibit 1003
`Page 3 of 99
`
`

`

`Declaration of R. Jacob Baker, Ph.D, P.E., Under 37 C.F.R. § 1.68 in Support of
`Petition for Inter Partes Review of U.S. Patent No. 7,049,850
`
`I, R. Jacob Baker, do hereby declare as follows:
`
`I.
`
`INTRODUCTION
`
`1.
`
`I have been retained by counsel for Unified Patents, LLC (“Unified”)
`
`as an independent expert witness for the above-captioned Petition for Inter Partes
`
`Review (“IPR”) of U.S. Patent No. 7.049,850 (“the ’850 patent”). I am being
`
`compensated at my usual and customary rate for the time I spend in connection with
`
`this IPR. My compensation is not affected by the outcome of this IPR.
`
`2.
`
`I have been asked to provide my opinions regarding whether claim 7
`
`(the “Challenged Claim”) of the ’850 patent is invalid as they would have been
`
`anticipated by the prior art or obvious to a person of ordinary skill in the art
`
`(“POSITA”) as of the earliest claimed priority date. It is my opinion that the
`
`Challenged Claim would have been obvious to a POSITA, after reviewing the prior
`
`art discussed below.
`
`3.
`
`In preparing this Declaration, I have reviewed:
`
`a)
`
`b)
`
`c)
`
`EX1001, the ’850 patent;
`
`EX1002, the file history of the ’850 patent;
`
`the prior art references discussed below:
`
`• U.S. Patent 6,452,365
`
`to Gourab Majumdar et al.
`
`(“Majumdar” (EX1005));
`
`
`
`4
`
`Unified Patents EX1003
`
`Unified Patents Exhibit 1003
`Page 4 of 99
`
`

`

`Declaration of R. Jacob Baker, Ph.D, P.E., Under 37 C.F.R. § 1.68 in Support of
`Petition for Inter Partes Review of U.S. Patent No. 7,049,850
`
`
`• U.S. Patent 6,545,510 to Timothy B. Cowles (“Cowles”
`
`(EX1006));
`
`• U.S. Patent Application Publication 2003/0012040 to Shoichi
`
`Orita et al. (“Orita” (EX1007));
`
`• U.S. Patent 6,774,674 by Kazuaki Okamoto et al.
`
`(“Okamoto” (EX1010));
`
`• U.S. Patent 5,608,237 by Yoshiaki Aizawa et al. (“Aizawa”
`
`(EX1014)); and
`
`• U.S. Patent 5,838,027 by Ho-Hym Kim et al. (“Kim”
`
`(EX1015));
`
`d)
`
`the following reference materials:
`
`• Victor P. Nelson et al., “Digital Logic Circuit Analysis &
`
`Design,” Prentice Hall, 1995 (EX008); and
`
`• Ejup N. Ganic, “The McGraw-Hill Handbook of Essential
`
`Engineering Information and Data,” R. R. Donnelly & Sons
`
`Co., 1991 (EX1013).
`
`e)
`
`any other document cited below.
`
`4.
`
`Unless indicated otherwise, in my analysis below, I refer to column and
`
`line numbers for issued U.S. patents, paragraph numbers for published U.S. patent
`
`
`
`5
`
`Unified Patents EX1003
`
`Unified Patents Exhibit 1003
`Page 5 of 99
`
`

`

`Declaration of R. Jacob Baker, Ph.D, P.E., Under 37 C.F.R. § 1.68 in Support of
`Petition for Inter Partes Review of U.S. Patent No. 7,049,850
`
`applications, and the original page numbering in non-patent documents.
`
`5.
`
`I understand that the ’850 patent issued from U.S. Patent Application
`
`Number 10/780,735 (“the ’735 application”), which was filed February 19, 2004. I
`
`understand that the ’850 patent claims priority to Japanese Patent Application No.
`
`2003-119641, which was filed on April 24, 2003. The face of the ’850 patent lists
`
`Kazuhiro Shimizu as the inventor. I have been informed that Arigna Technology
`
`Limited is the current assignee of the ’850 patent.
`
`6.
`
`In forming the opinions expressed in this Declaration, I relied upon my
`
`education and experience in the relevant field of art, and have considered the
`
`viewpoint of a Person of Ordinary Skill in the Art (POSITA), as of April 24, 2003,
`
`the priority date of the ’850 patent. I have also considered:
`
`a)
`
`b)
`
`the documents listed above,
`
`any additional documents and references cited in the analysis
`
`below,
`
`c)
`
`the relevant
`
`legal standards,
`
`including
`
`the standard for
`
`obviousness, and
`
`d) my knowledge and experience based upon my work in this area
`
`as described below.
`
`7.
`
`I understand that claims in an IPR are construed using the same claim
`
`
`
`6
`
`Unified Patents EX1003
`
`Unified Patents Exhibit 1003
`Page 6 of 99
`
`

`

`Declaration of R. Jacob Baker, Ph.D, P.E., Under 37 C.F.R. § 1.68 in Support of
`Petition for Inter Partes Review of U.S. Patent No. 7,049,850
`
`construction standard as one would use in a District Court proceeding.
`
`II. BACKGROUND AND QUALIFICATIONS
`8. My qualifications are set forth in my curriculum vitae, a copy of which
`
`is submitted as Exhibit 1004 in this proceeding. As set forth in my curriculum vitae:
`
`9.
`
`I am a Professor of Electrical and Computer Engineering at the
`
`University of Nevada, Las Vegas (“UNLV”). I have been working as an Engineer
`
`since 1985, and I have been teaching Electrical and Computer Engineering courses
`
`since 1991. I am also currently an industry consultant for Freedom Photonics. I am
`
`the named inventor on over 150 U.S. patents resulting from my industry work. I
`
`have over 35 years of experience in a wide variety of technologies and industries
`
`relating to semiconductor devices and the operation of semiconductor devices, as
`
`discussed below.
`
`10.
`
`I received B.S. and M.S. degrees in Electrical Engineering from UNLV
`
`in 1986 and 1988, respectively. I received my Ph.D. in Electrical Engineering from
`
`the University of Nevada, Reno, in 1993.
`
`11. My doctoral research, culminating in the award of a Ph.D., investigated
`
`the use of power MOSFETs in the design of very high peak power, and high-speed,
`
`instrumentation. A MOSFET is an abbreviation for a metal-oxide-semiconductor
`
`field-effect transistor. I developed techniques to reliably stack power MOSFETs to
`
`
`
`7
`
`Unified Patents EX1003
`
`Unified Patents Exhibit 1003
`Page 7 of 99
`
`

`

`Declaration of R. Jacob Baker, Ph.D, P.E., Under 37 C.F.R. § 1.68 in Support of
`Petition for Inter Partes Review of U.S. Patent No. 7,049,850
`
`switch higher voltages, that is, greater than 1,000 V and 100 Amps of current with
`
`nanosecond switching times. This work was reported in the paper entitled
`
`“Transformerless Capacitive Coupling of Gate Signals for Series Operation of
`
`Power MOSFET Devices,” published in the IEEE Transactions on Power
`
`Electronics. The paper received the Best Paper Award in 2000.
`
`A.
`12.
`
`Industry Experience
`
` I have done technical and expert witness consulting for over 125
`
`companies since I started working as an engineer in 1985. From 1985 to 1993, I
`
`worked for EG&G Energy Measurements and the Lawrence Livermore National
`
`Laboratory designing nuclear diagnostic instrumentation for underground nuclear
`
`weapon tests at the Nevada test site. During this time, I designed, and oversaw the
`
`fabrication of, over 30 electronic and electro-optic instruments including high-speed
`
`cable and fiber-optic receiver/transmitters, PLLs, frame and bit-syncs, data
`
`converters, streak-camera sweep circuits, Pockel’s cell drivers, micro-channel plate
`
`gating circuits, charging circuits for battery backup of equipment for recording test
`
`data, and analog oscilloscope electronics. My efforts in these devices included the
`
`mechanical and electrical design of the enclosures housing these instruments. Many
`
`of the enclosures I designed were ultimately mounted in equipment racks; however,
`
`some were hand-held for portable testing and measurements.
`
`13. My work during this time, as one example, had a direct impact on my
`
`
`
`8
`
`Unified Patents EX1003
`
`Unified Patents Exhibit 1003
`Page 8 of 99
`
`

`

`Declaration of R. Jacob Baker, Ph.D, P.E., Under 37 C.F.R. § 1.68 in Support of
`Petition for Inter Partes Review of U.S. Patent No. 7,049,850
`
`doctoral research work using power MOSFETs, subsequent publishing efforts, and
`
`industry designs. In addition to the 2000 Best Paper Award from the IEEE Power
`
`Electronics Society, I published several other papers in related areas while working
`
`in industry. I hold a patent, Patent No. 5,874,830, in the area of power supply design,
`
`titled, “Adaptively biased voltage regulator and operating method,” which was
`
`issued on February 23, 1999. I have designed dozens of linear and switching power
`
`supplies for commercial products and scientific instrumentation.
`
`14. From 1994 to 1996, I worked on the design of displays at Micron
`
`Display and Micron Technology, Inc. (“Micron”) in Boise, Idaho. This work was at
`
`a time when cathode ray tubes (CRTs) were still the dominant type of display. Flat
`
`panel displays were being developed with the hopes of replacing CRTs in the
`
`consumer market. I worked on field emitting displays which resulted in 5 patents:
`
`5,598,156, 5,638,085, 5,818,365, 5,894,293, and 5,909,201. I worked on the design
`
`of the pixels, both active and passive, as well as the supporting electronics for
`
`processing video signals. I was also involved with the evaluation of other display
`
`technologies including liquid crystal displays (LCDs), plasma displays, and organic
`
`light emitting diode (OLED) displays; the display technologies that were looking to
`
`displace CRTs in the consumer market. I was also involved with the packaging of
`
`the displays including the vacuum sealing and deposition of the phosphors for light
`
`wavelength conversion.
`
`
`
`9
`
`Unified Patents EX1003
`
`Unified Patents Exhibit 1003
`Page 9 of 99
`
`

`

`Declaration of R. Jacob Baker, Ph.D, P.E., Under 37 C.F.R. § 1.68 in Support of
`Petition for Inter Partes Review of U.S. Patent No. 7,049,850
`
`
`15.
`
`I am a licensed Professional Engineer and have extensive industry
`
`experience in circuit design, fabrication, and manufacture of Dynamic Random
`
`Access Memory (DRAM) semiconductor integrated circuit chips, Phase-Change
`
`Random Access Memory (PCRAM) chips, and CMOS Image Sensors (CISs) at
`
`Micron Technology, Inc. (“Micron”) in Boise, Idaho. I spent considerable time
`
`working on the development of Flash memory chips while at Micron. My efforts
`
`resulted in more than a dozen patents relating to Flash memory. One of my projects
`
`at Micron included the development, design, and testing of circuit design techniques
`
`for a multi-level cell (MLC) Flash memory using signal processing. Another project
`
`focused on the design of buffers for high-speed double-data rate DRAM which
`
`resulted in around 10 US patents in buffer design. Among many other experiences,
`
`I led the development of the delay locked loop (DLL) in the late 1990s so that Micron
`
`DRAM products could transition to the DDR memory protocol, used in mobile and
`
`non-mobile (server, desktop, cell phones, tablets, etc.) computing systems as main
`
`computer memory, for addressing and controlling accesses to memory via
`
`interprocess communications (IPC) with the memory controller (MC). I provided
`
`technical assistance with Micron’s acquisition of Photobit during 2001 and 2002,
`
`including transitioning the manufacture of CIS products into Micron’s process
`
`technology. Further, I did consulting work at Sun Microsystems and then Oracle on
`
`the design of memory modules during 2009 and 2010. This work entailed the design
`
`
`
`10
`
`Unified Patents EX1003
`
`Unified Patents Exhibit 1003
`Page 10 of 99
`
`

`

`Declaration of R. Jacob Baker, Ph.D, P.E., Under 37 C.F.R. § 1.68 in Support of
`Petition for Inter Partes Review of U.S. Patent No. 7,049,850
`
`of low-power, high-speed, and wide interconnection methods with the goal of
`
`transmitting data to/from the memory module and the MC at higher speeds.
`
`16.
`
`I have extensive experience in the development of instrumentation and
`
`commercial products
`
`in
`
`a multitude of
`
`areas
`
`including:
`
`integrated
`
`electrical/biological circuits and systems, array (memory, imagers, and displays)
`
`circuit design, CMOS analog and digital circuit design, diagnostic electrical and
`
`electro-optic instrumentation for scientific research, CAD tool development and
`
`online tutorials, low-power interconnect and packaging techniques, design of
`
`communication/interface circuits (to meet commercial standards such as USB,
`
`firewire, DDR, PCIe, SPI, etc.), circuit design for the use and storage of renewable
`
`energy, and power electronics. For example, a part of my research at Boise State,
`
`for many years, focused on the use of Thru-Silicon-Vias (TSVs), aka Thru-Wafer
`
`Vias (TWVs), for high-density packaging. These packaging techniques were
`
`utilized in the memory module development work I did with Sun Microsystems and
`
`Oracle. As another example, I’ve designed circuitry for use in implementing
`
`Universal Serial Bus (USB) interface circuits while I did consulting at Tower
`
`Semiconductor. I designed PCI communication circuits for IPC between a Graphics
`
`Processor Unit (GPU) and memory while consulting for Rendition, Inc.
`
`17. My current research work is focused in part on the design of integrated
`
`
`
`11
`
`Unified Patents EX1003
`
`Unified Patents Exhibit 1003
`Page 11 of 99
`
`

`

`Declaration of R. Jacob Baker, Ph.D, P.E., Under 37 C.F.R. § 1.68 in Support of
`Petition for Inter Partes Review of U.S. Patent No. 7,049,850
`
`circuits for wireless sensing using LIDAR (LIght Detection And Ranging). The
`
`designs are packaged and enclosures are designed, and fabricated (most often using
`
`3D printing) to house the units. I have worked with several companies in the
`
`development of these circuits and systems including Freedom Photonics, Aerius
`
`Photonics and FLIR. In the early 1990s I worked on wireless systems for wideband
`
`impulse radar while at Lawrence Livermore Laboratory. Further, part of my
`
`research for several years focused on the digitization of IQ channels using delta-
`
`sigma modulation. The knowledge and experience gained from this effort are
`
`reflected in my textbook CMOS Mixed-Signal Circuit Design and a presentation,
`
`which
`
`I
`
`have
`
`presented
`
`at
`
`several
`
`universities
`
`and
`
`companies,
`
`http://cmosedu.com/jbaker/papers/talks/BP_DSM_talk.pdf.
`
`B. Academic Experience
`18.
`
`I was an adjunct faculty member in the Electrical Engineering
`
`department of the University of Nevada, Las Vegas in 1991 and 1992. From 1993
`
`to 2000, I served on the faculty at the University of Idaho as an Assistant Professor
`
`and then as a tenured Associate Professor of Electrical Engineering. In 2000, I
`
`joined a new Electrical and Computer Engineering program at Boise State
`
`University (“BSU”) where I served as department chair from 2004 to 2007. At BSU,
`
`I helped establish graduate programs in Electrical and Computer Engineering
`
`including, in 2006, the university’s second Ph.D. degree. In 2012, I re-joined the
`
`
`
`12
`
`Unified Patents EX1003
`
`Unified Patents Exhibit 1003
`Page 12 of 99
`
`

`

`Declaration of R. Jacob Baker, Ph.D, P.E., Under 37 C.F.R. § 1.68 in Support of
`Petition for Inter Partes Review of U.S. Patent No. 7,049,850
`
`faculty at UNLV. Over the course of my career as a professor, I have advised over
`
`100 masters and doctoral students.
`
`19.
`
`I have been recognized for my contributions as an educator in the field.
`
`While at Boise State University, I received the President’s Research and Scholarship
`
`Award (2005), Honored Faculty Member recognition (2003), and Outstanding
`
`Department of Electrical Engineering Faculty recognition (2001). In 2007, I
`
`received the Frederick Emmons Terman Award (the “Father of Silicon Valley”).
`
`The Terman Award
`
`is bestowed annually upon an outstanding young
`
`electrical/computer engineering educator
`
`in recognition of
`
`the educator’s
`
`contributions to the profession. In 2011 I received the IEEE Circuits and Systems
`
`Education Award. I received the Tau Beta Pi Outstanding Electrical and Computer
`
`Engineering Professor Award every year it was awarded while I have been back at
`
`UNLV.
`
`20.
`
`I have authored several books and papers in the electrical and computer
`
`engineering area. My published books include CMOS Circuit Design, Layout, and
`
`Simulation (Baker, R.J., Wiley-IEEE, ISBN: 9781119481515 (4th ed., 2019)) and
`
`CMOS Mixed-Signal Circuit Design
`
`(Baker, R.J., Wiley-IEEE,
`
`ISBN:
`
`9780470290262 (2nded., 2009) and ISBN: 978-0471227540 (1st ed., 2002)). I co-
`
`authored DRAM Circuit Design: Fundamental and High-Speed Topics (Keeth, B.,
`
`
`
`13
`
`Unified Patents EX1003
`
`Unified Patents Exhibit 1003
`Page 13 of 99
`
`

`

`Declaration of R. Jacob Baker, Ph.D, P.E., Under 37 C.F.R. § 1.68 in Support of
`Petition for Inter Partes Review of U.S. Patent No. 7,049,850
`
`Baker, R.J., Johnson, B., and Lin, F., Wiley-IEEE, ISBN: 9780470184752 (2008)),
`
`DRAM Circuit Design: A Tutorial (Keeth, B. and Baker, R.J., Wiley-IEEE, ISBN:
`
`0780360141 (2001)), and CMOS Circuit Design, Layout and Simulation (Baker,
`
`R.J., Li, H.W., and Boyce, D.E., Wiley-IEEE, ISBN: 9780780334168 (1998)). I
`
`contributed as an editor and co-author on several other electrical and computer
`
`engineering books.
`
`C. Other Relevant Experience
`21.
`
`I have performed technical and expert witness consulting for over 125
`
`companies and laboratories and given more than 50 invited talks at conferences,
`
`companies, and universities. Further, I am the author or co-author of more than 100
`
`papers and presentations in the areas of electrical and computer engineering design,
`
`fabrication and packaging.
`
`22.
`
`I currently serve, or have served, as a volunteer on: the IEEE Press
`
`Editorial Board (1999-2004); as editor for the Wiley-IEEE Press Book Series on
`
`Microelectronic Systems (2010-2018); as the Technical Program Chair of the 2015
`
`IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS
`
`2015); on the IEEE Solid-State Circuits Society (SSCS) Administrative Committee
`
`(2011-2016); as a Distinguished Lecturer for the SSCS (2012-2015); as the
`
`Technology Editor (2012-2014) and Editor-in-Chief (2015-2020) for the IEEE
`
`Solid-State Circuits Magazine; IEEE Kirchhoff Award Committee (2020-present);
`
`
`
`14
`
`Unified Patents EX1003
`
`Unified Patents Exhibit 1003
`Page 14 of 99
`
`

`

`Declaration of R. Jacob Baker, Ph.D, P.E., Under 37 C.F.R. § 1.68 in Support of
`Petition for Inter Partes Review of U.S. Patent No. 7,049,850
`
`and advisor for the student branch of the IEEE at UNLV (2013-present). These
`
`meetings, groups, and publications are intended to allow researchers to share and
`
`coordinate research. My active participation in these meetings, groups, and
`
`publications allowed me to see what other researchers in the field have been doing.
`
`23.
`
`In addition to the above, I am an IEEE Fellow for contributions to
`
`memory design and a member of the honor societies Eta Kappa Nu and Tau Beta Pi.
`
`24. My current research work is focused in part on the design of integrated
`
`circuits for wireless sensing using LIDAR (LIght Detection And Ranging). I have
`
`worked with several companies in the development of these circuits and systems
`
`including Aerius Photonics and FLIR.
`
`25.
`
`I have considered information from various sources in forming my
`
`opinions. A list of materials considered is included in the list of exhibits that I
`
`understand Petitioner is filing. I may review additional documents filed in
`
`connection with this proceeding as they become available.
`
`III. UNDERSTANDING OF PATENT LAW
`26.
`
`I am not an attorney. For the purposes of this declaration, I have been
`
`informed about certain aspects of the law that are relevant to my opinions. My
`
`understanding of the law was provided to me by Petitioner’s attorneys.
`
`27.
`
`I have applied the following legal principles provided to me by counsel
`
`
`
`15
`
`Unified Patents EX1003
`
`Unified Patents Exhibit 1003
`Page 15 of 99
`
`

`

`Declaration of R. Jacob Baker, Ph.D, P.E., Under 37 C.F.R. § 1.68 in Support of
`Petition for Inter Partes Review of U.S. Patent No. 7,049,850
`
`in arriving at the opinions set forth in this declaration.
`
`28.
`
`I understand that prior art to the ’850 patent includes patents and printed
`
`publications in the relevant art that predate the priority date of the ’850 patent. For
`
`purposes of this Declaration, I have applied the date of April 24, 2003, the filing date
`
`of Japanese Patent Application No. 2003-119641, as the priority date of the ’850
`
`patent.
`
`29.
`
`I have been asked to provide my opinions regarding whether claim 7
`
`(the “Challenged Claim”) of the ’850 patent would have been anticipated by the prior
`
`art or would have been obvious to a POSITA at the time of the alleged invention
`
`(April 24, 2003) in light of the prior art.
`
`30.
`
`It is my understanding that, to anticipate a claim under 35 U.S.C. § 102,
`
`a reference must disclose each and every element of the claim.
`
`31.
`
`I understand that a claim is also unpatentable if it would have been
`
`obvious. Obviousness of a claim requires that the claim would have been obvious
`
`from the perspective of a POSITA at the time the alleged invention was made. I
`
`understand that a claim could have been obvious from a single prior art reference or
`
`from a combination of two or more prior art references.
`
`32.
`
`I understand that an obviousness analysis requires an understanding of
`
`the scope and content of the prior art, any differences between the alleged invention
`
`
`
`16
`
`Unified Patents EX1003
`
`Unified Patents Exhibit 1003
`Page 16 of 99
`
`

`

`Declaration of R. Jacob Baker, Ph.D, P.E., Under 37 C.F.R. § 1.68 in Support of
`Petition for Inter Partes Review of U.S. Patent No. 7,049,850
`
`and the prior art, and the level of ordinary skill in evaluating the pertinent art.
`
`33.
`
`I further understand that a claim would have been obvious if it unites
`
`old elements with no change to their respective functions, or alters prior art by mere
`
`substitution of one element for another known in the field and that combination
`
`yields predictable results. Also, I understand that obviousness does not require
`
`physical combination/bodily incorporation, but rather consideration of what the
`
`combined teachings would have suggested to persons of ordinary skill in the art at
`
`the time of the alleged invention. I understand that the combination of familiar
`
`elements according to known methods is likely to be obvious when it does no more
`
`than yield predictable results.
`
`34. As indicated above, I understand that a claim would have been obvious
`
`if it unites old elements with no change to their respective functions, or alters prior
`
`art by mere substitution of one element for another known in the field and that
`
`combination yields predictable results. While it may be helpful to identify a reason
`
`for this combination, I understand that there is no rigid requirement of finding an
`
`express teaching, suggestion, or motivation to combine within the references. When
`
`a product is available, design incentives and other market forces can prompt
`
`variations of it, either in the same field or different one. If a POSITA can implement
`
`a predictable variation, obviousness likely bars its patentability. For the same
`
`
`
`17
`
`Unified Patents EX1003
`
`Unified Patents Exhibit 1003
`Page 17 of 99
`
`

`

`Declaration of R. Jacob Baker, Ph.D, P.E., Under 37 C.F.R. § 1.68 in Support of
`Petition for Inter Partes Review of U.S. Patent No. 7,049,850
`
`reason, if a technique has been used to improve one device and a POSITA would
`
`recognize that it would improve similar devices in the same way, using the technique
`
`would have been obvious. I understand that a claim would have been obvious if
`
`common sense directs one to combine multiple prior art references or add missing
`
`features to reproduce the alleged invention recited in the claims.
`
`35.
`
`I further understand that certain factors may support or rebut the
`
`obviousness of a claim. I understand that such secondary considerations include,
`
`among other things, commercial success of the patented invention, skepticism of
`
`those having ordinary skill in the art at the time of invention, unexpected results of
`
`the invention, any long-felt but unsolved need in the art that was satisfied by the
`
`alleged invention, the failure of others to make the alleged invention, praise of the
`
`alleged invention by those having ordinary skill in the art, and copying of the alleged
`
`invention by others in the field. I understand that there must be a nexus—a
`
`connection—between any such secondary considerations and the alleged invention.
`
`I also understand that contemporaneous and independent invention by others is a
`
`secondary consideration tending to show obviousness.
`
`36.
`
`I am not aware of any allegations by the named inventors of the ’850
`
`patent or any assignee of the ’850 patent that any secondary considerations tend to
`
`rebut the obviousness of the Challenged Claim of the ’850 patent.
`
`
`
`18
`
`Unified Patents EX1003
`
`Unified Patents Exhibit 1003
`Page 18 of 99
`
`

`

`Declaration of R. Jacob Baker, Ph.D, P.E., Under 37 C.F.R. § 1.68 in Support of
`Petition for Inter Partes Review of U.S. Patent No. 7,049,850
`
`
`37.
`
`I understand that in considering obviousness, it is important not to
`
`determine obviousness using the benefit of hindsight derived from the patent being
`
`considered.
`
`38.
`
`I understand that other challenges to the validity of a patent, including
`
`patent ineligibility, enablement, written description, and definiteness, cannot be
`
`raised in inter partes review proceedings before the Board to challenge the validity
`
`of the ’850 patent. Accordingly, I did not consider those other challenges.
`
`39.
`
`I understand that Petitioner has the burden of proving unpatentability
`
`by a preponderance of evidence, which means that the claims are more likely than
`
`not unpatentable.
`
`40.
`
`I have been informed that the references I rely on in support of the
`
`unpatentability challenge (Majumdar (EX1005) and Cowles (EX1006)) were not of
`
`record during prosecution of the ’850 patent.
`
`41. The analysis in this declaration is in accordance with the above-stated
`
`legal principles.
`
`42. Unless indicated otherwise, all emphasis and annotations of the ’850
`
`patent and the prior art references cited in this Declaration are my own.
`
`
`
`19
`
`Unified Patents EX1003
`
`Unified Patents Exhibit 1003
`Page 19 of 99
`
`

`

`Declaration of R. Jacob Baker, Ph.D, P.E., Under 37 C.F.R. § 1.68 in Support of
`Petition for Inter Partes Review of U.S. Patent No. 7,049,850
`
`IV. THE ’850 PATENT AND RELEVANT BACKGROUND
`Summary of the ’850 Patent
`A.
`43. The ’850 Patent is titled “Semiconductor Device with a Voltage
`
`Detecting Device to Prevent Shoot-Through Phenomenon in First and Second
`
`Complementary Switching Devices,” and was issued on May 23, 2006.
`
`44. The ’850 patent relates to a high voltage integrated circuit (HVIC) for
`
`driving power devices such as integrated gate bipolar transistors (IGBTs). EX1001,
`
`1:10-24, 5:26-34. Figure 1 of the ’850 patent below illustrates an HVIC 100 in which
`
`a first power device 12 (e.g., IGBT) and a second power device 13 (e.g., IGBT)
`
`are connected in series between a high side (HV) power line and a low side (ground
`
`potential (GND)) power line, to form a half-bridge power device. EX1001, 5:26-
`
`32. A load U (e.g., a motor) is connected to a node N1 between the series-connected
`
`power devices 12, 13. EX1001, 5:32-34.
`
`
`
`20
`
`Unified Patents EX1003
`
`Unified Patents Exhibit 1003
`Page 20 of 99
`
`

`

`Declaration of R. Jacob Baker, Ph.D, P.E., Under 37 C.F.R. § 1.68 in Support of
`Petition for Inter Partes Review of U.S. Patent No. 7,049,850
`
`
`
`
`
`— ceeon
`
`CIRCUIT
`
`°850 patent (EX1001), Fig. 1 (annotated)
`
`45.
`
`The 850 patent explains that “the power device 12 switches between
`
`a potential at the node N1 used as a reference potential and the potential (HV)at a
`
`high side powerline, and is called a high side power device.” EX1001, 5:35-38.
`
`Further, “[t]he power device 13 switches between the ground potential used as a
`
`reference potential and the potential at the node N1, andis called a low side power
`
`device.” EX1001, 5:39-41. Thus, as shown in Figure 1, the HVIC 100 includesa
`
`first switching device 12 and a second switching device 13 connectedin series and
`
`interposed between a high main power potential (HV) and a low main power
`
`21
`
`IJnified Patents EX1003
`
`Unified Patents Exhibit 1003
`Page 21 of 99
`
`

`

`Declaration of R. Jacob Baker, Ph.D, P.E., Under 37 C.F.R. § 1.68 in Support of
`Petition for Inter Partes Review of U.S. Patent No. 7,049,850
`
`potential (GND).
`
`46.
`
`In Figure 1, the first switching device 12 is a high side switching
`
`device, and the second switching device 13 is a low side switching device. The
`
`’850 patent is related to addressing the “shoot-through” phenomenon in which the
`
`high side switching device and the low side switching device are turned on at the
`
`same time, resulting in a short circuit. EX1001, 1:20-24. To prevent this, the ’850
`
`patent explains that the potential VS (at node N1) between the high side switching
`
`device and the low side switching device may be monitored. EX1001, 1:39-40.
`
`However, the ’850 patent explains that “the potential VS usually reaches several
`
`hundred volts. Thus, it is impossible to monitor the potential VS within the HVIC.”
`
`EX1001, 1:40-42.
`
`
`
`22
`
`Unified Patents EX1003
`
`Unified Patents Exhibit 1003
`Page 22 of 99
`
`

`

`Declaration of R. Jacob Baker, Ph.D, P.E., Under 37 C.F.R. § 1.68 in Support of
`Petition for Inter Partes Review of U.S. Patent No. 7,049,850
`
`
`
`"besV11
`
`fy
`
`CIRCUIT
`temuseai— GENERATOR
`
`°850 patent (EX1001), Fig. 1 (annotated)
`
`47.
`
`Dueto it being allegedly “impossible to monitor the potential VS
`
`within the HVIC,” the ’850 patent proposes to monitor another voltage thatis
`
`considered to be “substantially equal to the potential VS,” as described in Section
`
`IV.B below. EX1001, 1:40-42, 19:44-49.
`
`B.
`
`Claim 7 and the Second Embodiment
`
`
`
`48. Claim7corresponds to the second embodimentillustrate