IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-14, NO. 6, DECEMBER 1979
`
`961
`
`A Two Chip PCM Voice CODEC with Filters
`
`YUSUF A. HAQUE, ROUBr.K GREGORIAN, MEMBER, JEEE, RICHARD W. BLASCO,
`ROGER A. MAO, MEMBER, IEEE, AND WILLIAM E. NICHOLSON, Jr., MEMBER, IEEE
`
`Abstract-Architecture and design of a monolithic voice CODEC is
`described.
`The CODEC consists of 2 chips-the transmit chip includes the com•
`panding coder (nonlinear A/D) along with filtering functions, and the
`receive chip consists of the expanding decoder (nonlinear D/ A) chip
`with its smoothing filter.
`Experimental results show the circuit to meet accepted requirements.
`
`J. INTRODUCTION
`
`F OR MORE THAN a decade analog-to-digital (A/D) and
`
`digital-to-analog (D/ A) conversion, i.e., the coder-decoder
`(CODEC) function has been required in the telephone system
`for transmission of voiceband signals. This involved the use of
`a high-speed CODEC multiplexed over 24, 32, or 96 channels
`using pulse amplitude modulation techniques. Technological
`advances have allowed the use of time division multiplexed
`digital switching networks to replace older space division analog
`switching networks. This has created yet another market for
`CODEC's (in addition to the channel bank application) for use
`in PBX's and local switching networks. The large volumes in(cid:173)
`volved, coupled with the economics of LSI circuits, make the
`development of monolithic per channel CODEC's viable.
`The CODEC to be described uses pulse-code modulation
`(PCM) for voice digitization. PCM is widely used in commer(cid:173)
`cial telephony switching and is deeply entrenched in world
`networks for short haul transmission. In order to achieve the
`required greater than 70 dB dynamic range with an 8 bit digi•
`tal word, compression/expansion technique is performed by
`using coding laws, the two internationally recognized laws for
`8 bit PCM being the segmented µ255 law and the A Law fl].
`The µ255 version has been implemented here and the A Law
`version is a metal mask option.
`The standard sampling rate for PCM codjng is 8 kHz. This
`requires that the signals applied to the coder be band-limited
`to below 4 kHz (Nyquist frequency) to prevent aliasing. In
`the decoder direction, after the digital word is decoded and is
`applied to the sample-and-hold, a smoothing filter is required
`to remove the high-frequency components from the sample•
`and-hold signal. These filtering functions have also been inte(cid:173)
`grated on the same chip with the associated data converters.
`
`11. SELECTION OF PROCESS TECHNOLOGY
`Silicon gate CMOS technology was chosen to fabricate the
`CODEC. This choice was motivated by the availability of low(cid:173)
`power digital circuitry and by the superior analog capability
`
`Manuscript received July 2, 1979;rcvised August 13, 1979.
`Y. A. Haque, R. Gregorian, R. W. Blasco, and W. E. Nicholson, Jr.,
`are with American Microsystems, Inc., Santa ClaJ'a, CA 9505 J.
`R. A. Mao was with American Microsystems, Inc., Santa Clara, CA
`95051. He is now with Synertek, Inc., Santa Clara, CA.
`
`of CMOS compared to single channel MOS. The CODEC with
`filters has a large mix of analog and digital circuitry on the
`same chlp. Thus digital feedthrough and noise can be coupled
`onto analog signal paths (for instance, through operational am(cid:173)
`plifier power supplies). Single channel operational amplifiers
`do not have a comparable power supply rejection from both
`supplies compared to CMOS operational amplifiers. This allows
`for a smaller decoupling requirement on CMOS analog cir·
`cuitry power supply lines and also allows a wider operating
`voltage range. In addition, CMOS has vertical n-p-n bipolar
`transistors which provides low output impedance devices with
`high current drive capability.
`Thin oxide voltage invariant capacitors were used for the
`CODEC. The polysilicon-to-aluminum capacitors are thermally
`grown using a double contact process. The first contact mask
`is used to define normal diffusion or polysilicon-to-metal con·
`tact openings and capacitor areas. A second contact mask is
`used after the wafer goes through a reflow process to remove
`oxide from normal contact areas. This mask is identical to the
`first contact mask if no capacitors are present. Thus, capac(cid:173)
`itors are fabricated without the need for additional masking
`steps.
`
`Ill. CHIP ARCHITECTURE
`The encoder and decoder with their corresponding filtering
`functions were integrated on two separate chips. This con·
`figuration guarantees good isolation between the transmit and
`receive functions. Integrating both functions on the same chip
`makes such isolation difficult to achieve, especially under an
`asynchronous mode of operation.
`[n addition, each chip of
`such a pair is smaller than a single chip version and, as such,
`yields are higher and costs are lower. Further, many applica(cid:173)
`tions exist where either the transmit or receive functions are
`separately required.
`Fig. I(a), and (b) show the block diagram of the transmit
`and receive chlp, respectively. In the transmit chip the voice
`signal is applied to a switched capacitor active low-pass filter
`through an uncommitted operational amplifier. The uncom(cid:173)
`mitted operational amplifier is required for constructing an
`antialiasing filter with external passive components_ These
`components can also be used for gain trimming. The low-pass
`filter is followed by a high-pass filter which also acts as a
`sample-and-hold for the encoder. The encoder performs the
`A/D conversion using a binary area ratioed capacitor array and
`a linear resistor string. An auto zero loop is also included to
`cancel any de offset in the encoder/filter combination.
`The phase-locked loop (PLL) synchronizes to an externally
`supplied strobe, typically 8 kHz, and provides all internal tirn·
`ing. In addition, the PLL powers down the chlp during the ab-
`
`0018-9200/79/1200-0961$00.75 © 1979 IEEE
`
`Authorized licensed use limited to: Kilpatrick Townsend & Stockton LLP. Downloaded on May 11,2021 at 20:56:28 UTC from IEEE Xplore. Restrictions apply.
`
`LG Ex. 1008
`LG Electronics Inc. v. ParkerVision, Inc.
`IPR2022-00245
`Page 00001
`
`

`

`962
`
`IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-14, NO. 6, DECEMBER 1979
`
`C ARRAY
`
`R STRING
`
`A/D LOGIC
`
`AUTO ZERO
`
`t----J AZ FILTER
`
`TEST
`
`MOOE
`
`OUTPUT
`BUFFER
`REGISTER
`
`-
`
`- -
`
`-
`
`-
`
`-
`
`-
`
`-
`
`-
`
`-
`
`-
`
`-
`
`-
`
`BKHz OUT (PROBE PAO)
`
`WER OOWN
`
`- ------+--+---V OUT CONTROL
`
`____ _.
`
`SIGNALING
`LOGIC
`
`.---e----< > B SIG IN
`
`A/B SELECT
`' - - - - - - - : J (A/BOUT) l
`
`VINF
`
`VIN+
`
`VIN-
`
`STROBE
`IBKHzl
`
`LOOP
`FILTER
`
`VooO
`
`VssO
`ANALOG Q
`GND
`DIGITAL
`GND
`
`0
`
`,.
`,.
`,.
`,.
`
`1: CCIS A/B SIGNALING OPTION
`
`$3501 ENCODER WITH FILTER BLOCK DIAGRAM (18 PIN PKG)
`(a)
`
`LOOP
`FILTER
`
`STROBE
`
`IN-
`
`LOW PASS FILTER
`W SINX/X
`CORRECTION
`
`128 KHz
`
`POWER
`DOWN
`BK Hz
`(PROBE PAO)
`
`Voo 0
`
`Vss 0
`
`~~G~TAL Q
`
`ANALOG
`GND
`
`0
`
`,.
`,.
`,.
`..
`
`*cc1s A/B SIGNALING OPTION
`
`I
`
`1 SIGNALING LOGIC --1-------------------i
`:~
`t
`
`r------------------------,
`·~---<
`I
`I
`--+---,1-VREF
`
`- - - - -~
`
`CARRAY
`
`...,
`
`I - - -
`I
`
`S&H
`
`R STRING
`
`~------+----{ J SHIFT CLOCK
`
`0/A LOGIC
`
`PCM IN
`
`ENABLE
`
`I
`I
`I
`I
`I
`r------------------~
`
`+
`
`AouT
`
`Bour
`
`A/8 SELECT (A/BIN)*
`
`POLARITY
`(GND OR Vssl
`
`$3502 DECODER WITH FILTER BLOCK DIAGRAM (16 PIN PKG)
`
`(b)
`
`Fig. 1. (a) Block diagram for the transmit chip. (b) Block diagram for the receive chip.
`
`sence of the 8 kHz strobe by driving a power-on reset (POR)
`circuit. The converted 8 bit PCM word is shifted out by a shift
`clock using a tristate output driver. This facilitates tying the
`PCM outputs of multiplexed CODEC's on a time shared bus.
`The receive chip accepts the PCM word and performs the D/A
`
`conversion. The output of the decoder is sampled and held
`and introduced into a switched-capacitor active low-pass re(cid:173)
`construction filter. A separate uncommitted-low output(cid:173)
`impedance operational amplifier is provided in this chip capable
`of driving a 600 D. hybrid. For users not requiring this func-
`
`Authorized licensed use limited to: Kilpatrick Townsend & Stockton LLP. Downloaded on May 11,2021 at 20:56:28 UTC from IEEE Xplore. Restrictions apply.
`
`IPR2022-00245 Page 00002
`
`

`

`HAQUE et al.: TWO CHIP PCM VOICE CODEC WITH FILTERS
`
`963
`
`FRt'JM OTHE/f
`IIV
`POINT.S
`HIGH PAS.5 FILiE.Jt
`
`I.OW.if! PL.ATE:
`SWITCH CONTROL.
`
`VREF
`
`VREF
`
`AUTO ZERO LOOP
`
`Fig. 2. Block diagram representation of the key section of A/D.
`
`tion the operational amplifier can be effectively turned off to
`save power.
`Both chips include functions required for supervision and
`signaling in telephone systems. Both in band signaling (where
`the LSB of the processed word is replaced every sixth frame
`by A signal and B signal inputs) and common channel interof(cid:173)
`fice signaling (CCIS) schemes (where a separate signaling high(cid:173)
`way exists) are implemented. In addition, noninverted and in(cid:173)
`verted (for relay drive applications) signaling options are
`available.
`The use of the PLL makes the system very flexible, since the
`8 kHz strobe (an internationally accepted standard) fixes all
`internal timing independent of the shift clock rate which is used
`to shift out the converted PCM data. The shift clock rate of
`the chip can be arbitrary to 3.1 MHz. The architecture of
`these chips was aimed at minimizing overall cost of the sys(cid:173)
`tem where the CODEC will be used. This was achieved by in(cid:173)
`tegrating the described. features and by making the chip re(cid:173)
`quirements flexible. Hence, the operating power supplies are
`allowed to vary from ±4.75 to ±7.5 V. In addition, only one
`common reference is required which can be shared among
`several CODEC's (i.e., 24 or 32 in a channel bank). This is
`achieved by buffering the reference on-chip. Also power sup(cid:173)
`ply and reference voltage decoupling were kept minimal (i.e.,
`0.1 µF capacitor). The use of the PLL (which eliminates the
`need for extra clock inputs) and the use of multiplexing on
`certain pins enabled the chips to be packaged in an 18 pin
`(I 6 pins for the receive chip) 300 mil wide package. The narrow
`packages have lower cost, are machine insertable, and result in
`a compact printed circuit board layout. To fit the package,
`the chip dimensions were tailored to be narrow on one side.
`
`IV. CIRCUIT DESIGN
`A. A/D and D/A Convenion Schemes
`The CODEC design is based on charge redistribution in a
`binary weighted array of capacitors [2] . In the present work,
`a capacitor array is used to define the decision levels corre(cid:173)
`sponding to the end points of the companding segments. To
`
`generate the linearly spaced decision levels within the segments,
`however, a resistor array is used instead of another capacitor
`array and buffer amplifier. Use of a resistor array for this ap(cid:173)
`plication has been reported in previous work [3] . However,
`the configuration of the array used here is different.
`The design approach to. be described here differs from other
`designs based on the charge tedistribution principle in that it
`uses state sequencing of switches to achieve data conversion of
`bipolar signals with a single polarity reference. This is achieved
`by switching the capacitors in the capacitor array from analog
`ground to v;.ef (reference voltage) for a + v;.ef increment, and
`from v;.ef to analog ground for a -Vref increment. Apart from
`the fact that only one reference is needed, this scheme has the
`advantage that the two reference swings achieved at the ca(cid:173)
`pacitor array are identical in magnitude, i.e., no mismatch
`occurs.
`Fig. 2. shows a simplified schematic of the analog portion of
`the transmit circuit.
`Initially, the input analog voltage from
`the band-limiting filter is sampled on the top plate of the ca(cid:173)
`pacitor array with the bottom plate being connected to v;.ef
`(normally - 3 V). This corresponds to position I for the lower
`plate switches. The sign of the signal is then determined and if
`the signal is positive the lower plates are connected to position
`3 (i.e., ground) with switch SA stiil being on. If the signal is
`negative, the lower plates are left connected in position I and
`switch SA is turned off. The segment bits (i.e., chords) are
`found by a sequential technique where, starting with the smali(cid:173)
`est capacitor, the voltage on the lower plate of the array is
`changed by -v;.ef (for a negative signal) by switching the lower
`plate connection from position 1 to 3, or by +v;.ef (for a posi(cid:173)
`tive signal) by changing the lower plate switch from position 3
`to I until the comparator changes sign. This determines the
`chord. The linear resistor string with 32 taps is then used to
`present (Yrefl32) k V (k = 0 to 32) to the lower plate of one
`capacitor (selected by the sequential search for the chords) in
`the capacitor array. A successive approximation technique is
`then used to determine the 4 bits corresponding to the linear
`division of the chords (this technique was not used for the
`
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`
`IPR2022-00245 Page 00003
`
`

`

`964
`
`IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-14, NO. 6, DECEMBER 1979
`
`chords because for coding of the smallest signal more than one
`capacitor needs to be switched simultaneously, as opposed to
`only one in the sequential scheme, thus increasing the risk of
`disturbing the sensing node during a critical phase of the con(cid:173)
`version). The decoder uses similar principles to achieve the
`data conversion. The linear resistor string has 32 equal taps on
`the transmit chip to implement the half-step shift adjacent to
`the origin. In .the decoder, 32 equal taps are used to implement
`half-step shifts corresponding to the signaling frames (where
`the LSB of the processed word is replaced by signaling bits)
`and information frames (where the unaltered 8 bit PCM word
`is available).
`
`B. Offset Compensation
`In order to meet stringent system requirements, it is necessary
`to cancel any offset voltage in the encoder. The offset is
`caused by comparator and filter offset voltages and by clock
`feedthrough on the top plates of the capacitor array through
`the parasitic capacitance of the switch driving it. Offset can(cid:173)
`cellation i~ achieved by integrating the PCM sign bit (using an
`on-chip resistor and an external capacitor) and feeding back the
`result into the last stage of the high-pass filter, as shown in
`Fig. 2. The time constant of the auto zero loop is several sec(cid:173)
`onds. For faster acquisition of offsets immediately after
`power-up, a dual bandwidth \oop "'.as implemented. The auto
`zero loop is powered up immediately on application of the
`strobe signal. The loop starts with a large bandwidth by se(cid:173)
`iecting a smaller on-chip integrating resistance. The PLL in the
`meantime acquires lock and drives a POR circuit to enable the
`chip. As soon as the chip is enabled, the auto zero loop
`switches to a lower bandwidth. This feature not only im(cid:173)
`proves circuit performance immediately after power-up but
`also eases automated testing of these chips_
`
`C. Operational Amplifiers
`The transmit and receive chips required 20 operational am(cid:173)
`plifiers, out of which three had to have low-impedance out(cid:173)
`puts capable of driving 600 Q loads. Due to the large number
`of a,mplifiers, the power dissipation of each amplifier had to be
`minimized. In addition, due to the large mix of digital and
`analog circuitry,, the power supply rejection had to be accept(cid:173)
`able to limit noise from power supply lines getting coupled onto
`analog signal paths.
`Figs. 3 and 4 show the schematic of a high and low output
`impedance operational amplifier. A key feature of the circuits
`is the class A-B operation of the output stage which results in
`significantly reduced power dissipation and higher open loop
`gain. Further reduction in power dissipation is obtained by
`using a frequency compensation scheme which does not use a
`buffer amplifier (normally used to prevent the feedforward of
`the signal through the compensation capacitor which creates a
`low~frequency zero in the transfer function [4] ). Instead, the
`compensation capacitor is introduced through a resistor (using
`QI 0, QI 1 ). This creates a zero in the position of the second
`dominant pole and helps stabilize the amplifier, In principle,
`the operational amplifier can be stabilized using C 1 only. Use
`of C2 along with C 1 , however, improves the power supply re(cid:173)
`jection ratio (PSRR) as follows: node 1 (in Fig. 3) is a high-
`
`QIC
`
`QII
`
`Fig. 3. Schematic of high-output impedance operational amplifier.
`
`Fig. 4. Schematic of the low-output impedance operational amplifier.
`
`impedance point and any noise on VDD appears essentially un(cid:173)
`attenuated on it at low frequencies. Thus, at low frequencies
`transistor Q 1 does not amplify any noise.on v;D (due to es(cid:173)
`sentially zero gate source noise voltage). At higher frequencies,
`however, node I starts rolling off due to the pole created by
`C1 , thus creating an increasing gate source noise voltage and
`thus noise amplification into the amplifier through Q 1 • This
`effect can be alleviated by making C1 smaller_ Use of C2
`makes this possible. T11ble I shows the performance data for
`the high output impedance operational amplifier. The low
`output impedance operational amplifier has similar perfor(cid:173)
`mance, except that the minimum open loop gain is 60 dB and
`the power dissipation is higher (approximately 20 mW).
`
`D. Comparator
`The comparator used in the transmit chip is capable of re(cid:173)
`solving 300 µV in less than 2 µs. It consists of (Fig. 5) a diode
`clamped preamplifier (Q 13, Q14 , Q 15 , Q 16 , Q17 ) driving an(cid:173)
`other differential amplifier stage (Q 3 , Q4 , Q5 , Q6 , Q7 ) which
`drives the output gain stage (Q 10 , Q11 , Q12 ). The output of a
`nondiode clamped differential stage undergoes large voltage
`excursions and under sufficient input voltage it drives the out(cid:173)
`put devices out of the saturation region of operntion. There~
`fore, in switching from one state to another, the comparator
`initially starts with a low gain resulting in a slow response time.
`Diode clamps on the output .nodes (node 2) limits the voltage
`excursion of the output nodes and thus improves the transient
`response. The stage was broad-banded by using source follower
`b4ffers (Q18, Q19 , Q20 , Q2 i) to drive the second stage (the in(cid:173)
`put capacitance of this stage is large due to the Miller multi(cid:173)
`plication of the gate drain overlap capacitance).
`
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`
`IPR2022-00245 Page 00004
`
`

`

`HAQUE et al.: TWO CHIP PCM VOICE CODEC WITH FILTERS
`
`965
`
`TABLE I
`HIGH-OUTPUT IMPEDANCE OPERATIONAL AMPLIFIER
`Low Frequency Gain
`
`= 90dB
`
`Unity Gain Bandwidth
`
`2.5MHz
`
`Offset Voltage
`
`lOmv (standard deviation)
`+0.4mv (mean)
`
`CMRR
`
`PSRR
`
`Slew Rate
`
`73dB
`
`70dB (DC) to VSS
`
`68dB (DC) to VDD
`(meas ~red)
`2 V/µsec
`
`/
`
`/
`
`76dB (DC), 74dB (3.16KHz) to VSS
`
`74dB (DC), 67dB (3.16KHz) to VDD
`(computer simulation)
`
`Power Dissipation
`
`1.6mW
`
`Noise
`
`Area
`
`26µV rms fntegrated over a band lOHz-lMHz .)
`
`270mil2
`
`i
`Q/8 ~ l---'-o--<Ho+-1---,
`
`L,t;NJ
`i
`'
`
`/(>II
`
`STR085
`
`/
`
`CONTROLLE t> BY f'HA!Je
`0/FFERENCI!' 8STW£EN
`EXTERNAL ST/foae AND
`tNTl!RNAJ..L Y PLL
`GENEAATEO STff06E.
`
`Fig. 5. Schematic of comparator used in the transmit chip.
`
`Fig. 6. Offset canceled reference buffer.
`
`The second differenti;.d amplifier has a cascaded gain stage
`for its load. This reduces Miller multiplication of the gate ca(cid:173)
`pacitance of Q 10 , as seen on node 3. A push-pull drive has
`been implemented for the output stage to reduce power dis(cid:173)
`sipation and increase gain. The comparator has an open loop
`gain greater than 120 dB with a bandwidth of 2 5 MHz.
`
`E. Reference Buffer
`An on-chip reference buffer is required for both chips to re(cid:173)
`duce decoupling and current supply requirements of the ex(cid:173)
`ternal reference (which can be common to many CODEC's).
`The offset voltage of this reference buffer is canceled to elim(cid:173)
`inate gain variation in the channel. This is accomplished by
`using the circuit shown on Fig. 6. Initially, switches SA and
`SB are turned on and the reference voltage is sampled onto
`one plate of the capacitor C, with the offset of the amplifier
`being stored on the other plate. Next, SA and SB are turned
`off and Sc is turned on. This forces the output to be equal to
`the reference voltage. Clock feedthrough does not have any
`effect since the feedthrough is not signal dependent (the refer(cid:173)
`ence has a constant value).
`
`Cz
`
`l
`
`Fig. 7. Schematic of power-on reset circuit.
`
`F. PLL and POR Circuitry
`The PLL consists of an edge sensitive phase detector, a loop
`filter (lead-lag), a voltage-controlled oscillator (VCO), and a
`divider chain. The loop filter uses on-chip resistors and an ex(cid:173)
`ternal capacitor. The loop filter has dual bandwidth. During
`the power-up period the loop filter starts with a small time(cid:173)
`constant, thus enabling the PLL to achieve lock in less than
`20 ms. In normal operation, however, the loop switches to a
`narrow bandwidth filter to reduce phase jitter.
`A POR circuit controls the power-up/down function on both
`chips, and is shown in Fig. 7. In the absence of the strobe sig(cid:173)
`nal, the lock detector in the PLL turns on a current source and
`charges the capacitor C2 to V DD, . and forces the Schmitt
`trigger to VDn. In the presence of the strobe this capacitor is
`discharged to ground through SA and S8 which eventually
`powers up the circuit by forcing the Schmitt trigger output to
`ground. Capacitors C1 , C2 act as an RC filter with the time
`constant given by (C1 /C2 ) T, where Tis the clocking period.
`The time constant of the POR is selected to allow sufficient
`time for the PLL to acquire lock before the circuit is powered
`up.
`
`G. Signaling
`Two different types of signaling functions have been in(cid:173)
`corporated.
`In the .common channel interoffice signaling
`(CCIS) scheme, a separate signaling highway is created. Two
`bits (Asig, Bsig) are multiplexed on this line and transmitted
`every frame. In the inband signaling scheme implemented, the
`LSB of the processed word is replaced every sixth frame by
`
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`
`IPR2022-00245 Page 00005
`
`

`

`966
`
`IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-14, NO. 6, DECEMBER 1979
`
`VOICE. SIGNAL J LCM' fJIS6 FU:rERI
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`(a) Transmit filter block diagram. (b) Doubly-terminated reactance ladder filter. (c) Low-pass transmit ladder
`Fig. 8.
`simulated switched-capacitor filter. (d) Transmit high-pass state-variable filter. (e) Circuit for third-order state-variable
`filter.
`
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`
`IPR2022-00245 Page 00006
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`

`

`HAQUE et al.: TWO CHIP PCM VOICE CODEC WITH FILTERS
`
`967
`
`(a)
`
`(b)
`Fig. 9. (a) Photomicrograph of the transmit chip. (b) Photomicrograph of the receive chip.
`
`Asig and twelfth frame by Bsig• To compensate for loss of the
`LSB during signaling, the decoder adjusts for it by making
`½ LSB shifts in its coding algorithm [I] .
`H Filters
`In a PCM telephone system, two major filtering functions are
`In the encode direction,
`performed on the incoming signal.
`the transmit filter limits the frequency content of the analog
`voice signal to the 0-3400 Hz band. This then allows sampling
`at an 8 kHz rate without aliasing. In addition, a notch or high(cid:173)
`pass filtering is also performed to prevent power line fundamen(cid:173)
`tal frequencies from being transmitted. The IC implementation
`of the transmit and receive filters for the two-chip PCM voice
`CODEC will be described next. The design of the filters were
`based on the recently developed concept of switched-capacitor
`filters (6], (7], which makes it possible to obtain high-quality
`filters in fully integrated form. Shown in Fig. 8(a) is a block
`diagram of the transmit filter. The filter contains a low-pass
`and a high-pass connected in cascade. The low-pass, operating
`at 128 kHz, performs the band-limiting to 3.4 kHz. This then
`allows the high-pass to operate at the lowest possible rate,
`8 kHz, which avoids the need for a wide element value spread.
`
`The design approach chosen for the transmit low-pass was
`based on the simulation of a double-terminated reactance lad(cid:173)
`der filter (8], (9] . The fifth-order elliptic filter shown in
`Fig. 8(b) served as the model circuit, and the switched(cid:173)
`capacitor filter shown in Fig. 8( c) was developed using the de(cid:173)
`sign techniques of (8] and (9] . As the model circuit of Fig.
`8(b) illustrates, for R 1 = R 2 , there is flat loss of 6 dB gain in
`the high-pass filter.
`The circuit configuration of the third-order Chebyshev high(cid:173)
`pass filter is shown in Fig. 8( d). A detailed analysis and design
`technique of this state-variable filter is described in (10] . In(cid:173)
`spection of Fig. 8( d) reveals that the clocking of the first- and
`second-order sections must alternate to prevent analog signal
`leakthrough which affects the frequency response _of the filter.
`In the decoder direction, the receive filter performs two
`It removes frequencies above 4 kHz from the
`functions.
`sampled-and-held signal coming from the decoder. It also per(cid:173)
`forms the loss equalization to compensate for the sinx/x dis(cid:173)
`tortion due to the 8 kHz sample-and-hold operation. The basic
`third-order section is shown in Fig. 8( e) [ 11] . Using the charge
`conservation concept and z-domain techniques the transfer
`function will be derived as
`
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`
`IPR2022-00245 Page 00007
`
`

`

`968
`
`IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-14, NO. 6, DECEMBER 1979
`
`GAIN TRACKING RESPO'iSE
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`BEL.L SYSTEM D3 sPEC
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`--- APPROXIMATE. THEORETICAL. RATIO
`NIEASU~ED
`
`/
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`o
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`INPlJT AMPLrfUDE IN dB
`REL. TO OVERLOAD POINT
`(b)
`(a) Tracking error as a function of input level relative to
`Fig. 1 L
`-10 dBmO with an input frequency of 1004 Hz. (b) Signal to dis(cid:173)
`tortion ratio as a function of input level.
`
`Fig. 12. 1'he top trace is the frequency response of the transmit filter.
`The output of the filter was impulse sampled by external circuitry
`at 8 kHz. This causes the extra component at 4 kHz seen on the top
`trace. The lower trace (displaced by l O dB) is the frequency response
`of the receive filter.
`
`of the two chips is 125 mW during normal operation and
`35 mW during power-down.
`
`VI. CONCLUSIONS
`A complete PCM voice CODEC with the necessary filtering
`functions has been successfully integrated on a two-chip set.
`
`ACKNOWLEDGMENT
`The authors wish to thank V. God bole for his assistance in
`product definition, C. Lee for circuit emulation, and S. Carter
`and R. Arnst for circuit layout.
`
`(a)
`
`(b)
`Fig. 10. (a) The response of the coder driving the decoder for a linear
`ramp at its input. (b) The response of the decoder when driven by all
`possible PCM words in amplitude sequence.
`
`where H(z) describes a third-order characteristic with three
`poles (one real and two normally complex) and two complex
`conjugate transmission zeros. The sixth-order receive filter is
`obtained by cascading two such sections.
`The design of the receive filter was carried out directly in the
`z-domain and the critical frequencies were found by computer(cid:173)
`aided optimization. For ±5 V supply voltages the maximum
`output swing was 7 V peak-to-peak. The filter operated
`at a 128 kHz clock rate. Both transmit and receive filters
`were designed to meet the CCITT attenuation/frequency
`recommendations.
`
`V. EXPERIMENTAL RESULTS
`The chips were planned so that they are optically shrinkable
`up to 20 percent. The full-size drawn dimension of the trans(cid:173)
`mit chip is equivalent in area to 202 mil 2
`, but was shrunk by
`15 percent, yielding a chip 172 mil2
`• The receive chip full(cid:173)
`size drawn dimension is equivalent in area to 192 mi12
`• This
`chip was initially not shrunk. Fig. 9(a) and (b) show photo(cid:173)
`micrographs of the transmit and receive chips, respectively.
`Fig. lO(a) shows the response of the coder driving the de(cid:173)
`coder (with the respective filters on each chip bypassed) to a
`linear ramp at the input of the coder. The nonlinear step size
`resulting from the compression/expansion is clearly evident.
`The last code for negative signals on the transfer curve does
`not follow the ramp due to zero code suppression implemented
`on-chip. Fig. lO(b) shows the output of the decoder when
`driven by all the possible PCM codes in amplitude sequence.
`Fig. 1 l(a) shows the gain tracking characteristics and Fig.
`11 (b) the signal to total quantization distortion ratio for the
`two devices looped together (including filters). Fig. 12 shows
`the frequency response of the filters. Both filters meet D3/
`Idle channel noise for the full channel
`CCITT requirements.
`was measured at 17 dBrnCD. The combined power dissipation
`
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`
`IPR2022-00245 Page 00008
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`

`

`HAQUE et at.: TWO CHIP PCM VOICE CODEC WITH FILTERS
`
`969
`
`REFERENCES
`
`[1] CCITT Orangebook Geneva, Recommendation G.711, p. 407-
`423, 1977.
`[2] Y. P. Tsividis, P. R. Gray, D. A. Hodges, and J. Chacko, Jr., "A
`segmented µ255 Law PCM voice encoder utilizing NMOS tech(cid:173)
`nology," IEEE J. Solid-State Circuits, vol. SC-11, pp. 740-747,
`Dec. 1976.
`[3] J. T. Caves, C.H. Chan, S. D. Rosenbaum, L. P. Sellars, and J.B.
`Terry, "A PCM voice CODEC with on chip filters," IEEE J.
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`[6] B. J. Hosticka, R. W. Brodersen, and P.R. Gray, "MOS sampled
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`[7] J. T. Caves, M.A. Copeland, C. F. Rahim, and S. D. Rosenbaum,
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`equivalents," IEEE J. Solid-State Circuits, vol. SC-12, pp. 592-
`589, Dec. 1977.
`[8] D. J. Allstott, R. W. Brodersen, and P.R. Gray, "Fully-integrated
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`[9] G. M. Jacobs, D. J. Allstot, R. W. Brodersen, and P. R. Gray,
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`Trans. Circuits Syst., vol. CAS-25, pp. 1014-1021, Dec. 1978.
`(10] R. Gregorian and W. E. Nicholson, Jr., "A high-pass switched ca(cid:173)
`pacitor filter," in Conf Rec., 12th Asilomar Conf Circuits, Sys(cid:173)
`tems and Computers, Nov. 1978, pp. 669-673.
`(11] R. Gregorian, Y. Haque, R. Mao, R. W. Blasco, and W. E. Nichol(cid:173)
`son, Jr., "CMOS switched capacito