| HAI LALA AT MATA AT MATA MO AT NA HATI
`
`US009824035B2
`
`( 12 ) United States Patent
`Lee et al .
`
`( 54 ) MEMORY MODULE WITH
`TIMING - CONTROLLED DATA PATHS IN
`DISTRIBUTED DATA BUFFERS
`Applicant : Netlist , Inc . , Irvine , CA ( US )
`( 71 )
`( 72 ) Inventors : Hyun Lee , Ledera Ranch , CA ( US ) ;
`Jayesh R . Bhakta , Cerritos , CA ( US )
`( 73 ) Assignee : NETLIST , INC . , Irvine , CA ( US )
`Subject to any disclaimer , the term of this
`( * ) Notice :
`patent is extended or adjusted under 35
`U . S . C . 154 ( b ) by 0 days .
`This patent is subject to a terminal dis
`claimer .
`( 21 ) Appl . No . : 15 / 426 , 064
`( 22 ) Filed :
`Feb . 7 , 2017
`Prior Publication Data
`( 65 )
`US 2017 / 0147514 A1 May 25 , 2017
`Related U . S . Application Data
`( 63 ) Continuation of application No . 14 / 846 , 993 , filed on
`Sep . 7 , 2015 , now Pat . No . 9 , 563 , 587 , which is a
`( Continued )
`
`( 51 )
`
`( 52 )
`
`Int . Cl .
`GO6F 3 / 00
`G06F 12 / 00
`G06F 13 / 00
`G06F 13 / 16
`G06F 3 / 06
`G11C 8 / 18
`U . S . CI .
`CPC . . . . . . . . GO6F 13 / 1673 ( 2013 . 01 ) ; G06F 3 / 0613
`( 2013 . 01 ) ; G06F 370656 ( 2013 . 01 ) ; G06F
`
`( 2006 . 01 )
`( 2006 . 01 )
`( 2006 . 01 )
`( 2006 . 01 )
`( 2006 . 01 )
`( 2006 . 01 )
`
`( 10 ) Patent No . :
`( 45 ) Date of Patent :
`
`U
`
`4 , 035 B2
`* Nov . 21 , 2017
`
`( 56 )
`
`370659 ( 2013 . 01 ) ; G06F 370683 ( 2013 . 01 ) ;
`G06F 13 / 1642 ( 2013 . 01 ) ; GIIC 8 / 18
`( 2013 . 01 )
`( 58 ) Field of Classification Search
`None
`See application file for complete search history .
`References Cited
`U . S . PATENT DOCUMENTS
`7 , 884 , 619 B1 *
`2 / 2011 Chong . . . . . . . . . . . . . . . GO1R 31 / 3016
`324 / 601
`8 , 214 , 616 B2 *
`7 / 2012 Ware .
`2012 Ware . . . . . . . . . . . . . . . . . . . G06F 13 / 1684
`711 / 104
`( Continued )
`Primary Examiner - Michael Sun
`( 74 ) Attorney , Agent , or Firm — Maschoff Brennan
`ABSTRACT
`( 57 )
`A memory module is operatable in a memory system with a
`memory controller . The memory module comprises a mod
`ule control device mounted on the module board to receive
`command signals from the memory controller and to output
`module command signals and module control signals , and
`memory devices mounted on the module board to perform a
`first memory operation in response to the module command
`signals . The memory module further comprises a plurality of
`buffer circuits distributed across a surface of the module
`board . Each respective buffer circuit is associated with a
`respective set of the memory devices and includes logic that
`is configured to obtain timing information based on signals
`received by the each respective buffer circuit during a
`second memory operation prior to the first memory opera
`tion and to control timing of the data and strobe signals
`through the each respective buffer circuit in accordance with
`the timing information .
`22 Claims , 26 Drawing Sheets
`
`101 ~
`
`105
`
`118
`
`MCH 11
`
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`
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`T3
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`
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`
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`
`O O OOO
`NIINNSY
`
`III + IIIIIII
`
`116
`
`Module Control
`
`0 - 0 FILLIFILE .
`IT
`
`Micron et al. - Exhibit 1008
`Micron et al. v. Netlist - IPR2022-00237
`Page 1 of 39
`
`

`

`US 9 , 824 , 035 B2
`Page 2
`
`Related U . S . Application Data
`continuation of application No . 13 / 952 , 599 , filed on
`Jul . 27 , 2013 , now Pat . No . 9 , 128 , 632 .
`( 60 ) Provisional application No . 61 / 676 , 883 , filed on Jul .
`27 , 2012 .
`
`( 56 )
`
`References Cited
`U . S . PATENT DOCUMENTS
`8 , 565 , 033 B1 * 10 / 2013 Manohararajah . . . . G11C 29 / 028
`365 / 129
`8 , 949 , 519 B2 *
`2 / 2015 Rajan . . . . . . . . . . . . . .
`G110 5 / 02
`365 / 189 . 2
`2002 / 0039323 A1 *
`4 / 2002 Tokutome . . . . . . . . . . . . G11C 7 / 1066
`365 / 233 . 12
`2006 / 0077731 A1 *
`4 / 2006 Ware
`G11C 5 / 04
`365 / 194
`2007 / 0217559 A1 *
`9 / 2007 Stott . . . . . . . . . . . . . . . . . . GIIC 7 / 1051
`375 / 355
`2008 / 0037412 A1 * 2 / 2008 Geile
`. . . . . . . . . .
`. . . G06F 17 / 14
`370 / 208
`2010 / 0271092 A1 * 10 / 2010 Zerbe . . . . . . . . . . . . . . . . . GO6F 13 / 4243
`327 / 161
`2012 / 0256639 A1 *
`10 / 2012 Pausini . . . . . . . . . . . . GOIR 31 / 31709
`324 / 613
`2014 / 0029370 A1 *
`1 / 2014 Koshizuka . . . . . . . . . . . G11C 7 / 1051
`365 / 233 . 13
`
`* cited by examiner
`
`Micron et al. - Exhibit 1008
`Micron et al. v. Netlist - IPR2022-00237
`Page 2 of 39
`
`

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`atent
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`Nov . 21 , 2017
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`Sheet 1 of 26
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`US 9 , 824 , 035 B2
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`FIG . 1
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`
`Micron et al. - Exhibit 1008
`Micron et al. v. Netlist - IPR2022-00237
`Page 3 of 39
`
`

`

`atent
`
`Nov . 21 , 2017
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`Sheet 2 of 26
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`US 9 , 824 , 035 B2
`
`FIG . 2A
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`Micron et al. - Exhibit 1008
`Micron et al. v. Netlist - IPR2022-00237
`Page 4 of 39
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`

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`atent
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`Nov . 21 , 2017
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`Sheet 3 of 26
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`US 9 , 824 , 035 B2
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`Micron et al. - Exhibit 1008
`Micron et al. v. Netlist - IPR2022-00237
`Page 5 of 39
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`atent
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`Nov . 21 , 2017
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`Sheet 4 of 26
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`US 9 , 824 , 035 B2
`
`wwwwwwwwwwwwwwwwwwwwwwwwwwwwwww DIMM
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`Micron et al. - Exhibit 1008
`Micron et al. v. Netlist - IPR2022-00237
`Page 6 of 39
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`

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`atent
`
`Nov . 21 , 2017
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`Sheet 5 of 26
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`US 9 , 824 , 035 B2
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`Micron et al. - Exhibit 1008
`Micron et al. v. Netlist - IPR2022-00237
`Page 7 of 39
`
`

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`atent
`
`Nov . 21 , 2017
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`Sheet 6 of 26
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`US 9 , 824 , 035 B2
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`Micron et al. - Exhibit 1008
`Micron et al. v. Netlist - IPR2022-00237
`Page 8 of 39
`
`

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`atent
`
`Nov . 21 , 2017
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`Sheet 7 of 26
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`US 9 , 824 , 035 B2
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`Micron et al. - Exhibit 1008
`Micron et al. v. Netlist - IPR2022-00237
`Page 9 of 39
`
`

`

`atent
`
`Nov . 21 , 2017
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`Sheet 8 of 26
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`US 9 , 824 , 035 B2
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`Micron et al. - Exhibit 1008
`Micron et al. v. Netlist - IPR2022-00237
`Page 10 of 39
`
`

`

`atent
`
`Nov . 21 , 2017
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`Sheet of 26
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`US 9 , 824 . 035 B2
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`M11 - 1
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`Micron et al. - Exhibit 1008
`Micron et al. v. Netlist - IPR2022-00237
`Page 11 of 39
`
`

`

`atent
`
`Nov . 21 , 2017
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`Sheet 10 of 26
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`US 9 , 824 , 035 B2
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`Micron et al. - Exhibit 1008
`Micron et al. v. Netlist - IPR2022-00237
`Page 12 of 39
`
`

`

`atent
`
`Nov . 21 , 2017
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`Sheet ll of 26
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`US 9 , 824 , 035 B2
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`Micron et al. - Exhibit 1008
`Micron et al. v. Netlist - IPR2022-00237
`Page 13 of 39
`
`

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`atent
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`Nov . 21 , 2017
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`Sheet 12 of 26
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`Micron et al. - Exhibit 1008
`Micron et al. v. Netlist - IPR2022-00237
`Page 14 of 39
`
`

`

`atent
`
`Nov . 21 , 2017
`
`Sheet 13 of 26
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`US 9 , 824 , 035 B2
`
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`Micron et al. - Exhibit 1008
`Micron et al. v. Netlist - IPR2022-00237
`Page 15 of 39
`
`

`

`atent
`
`Nov . 21 , 2017
`
`Sheet 14 of 26
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`US 9 , 824 , 035 B2
`
`XX FIG . 10B
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`Micron et al. - Exhibit 1008
`Micron et al. v. Netlist - IPR2022-00237
`Page 16 of 39
`
`

`

`atent
`
`Nov . 21 , 2017
`
`Sheet 15 of 26
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`US 9 , 824 , 035 B2
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`Micron et al. - Exhibit 1008
`Micron et al. v. Netlist - IPR2022-00237
`Page 17 of 39
`
`

`

`atent
`
`Nov . 21 , 2017
`
`Sheet 16 of 26
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`US 9 , 824 , 035 B2
`
`912
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`Micron et al. - Exhibit 1008
`Micron et al. v. Netlist - IPR2022-00237
`Page 18 of 39
`
`

`

`atent
`
`Nov . 21 , 2017
`
`Sheet 17 of 26
`
`US 9 , 824 , 035 B2
`
`
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`Micron et al. - Exhibit 1008
`Micron et al. v. Netlist - IPR2022-00237
`Page 19 of 39
`
`

`

`U . S . Patent
`
`Nov . 21 , 2017
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`Sheet 18 of 26
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`US 9 , 824 , 035 B2
`
`DOS1 IIIIII
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`Micron et al. - Exhibit 1008
`Micron et al. v. Netlist - IPR2022-00237
`Page 20 of 39
`
`

`

`U . S . Patent
`
`Nov . 21 , 2017
`
`Sheet 19 of 26
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`Micron et al. - Exhibit 1008
`Micron et al. v. Netlist - IPR2022-00237
`Page 21 of 39
`
`

`

`atent
`
`Nov . 21 , 2017
`
`Sheet 20 of 26
`
`US 9 , 824 , 035 B2
`
`650
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`FIG . 13
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`Micron et al. - Exhibit 1008
`Micron et al. v. Netlist - IPR2022-00237
`Page 22 of 39
`
`

`

`atent
`
`Nov . 21 , 2017
`
`Sheet 21 of 26
`
`US 9 , 824 , 035 B2
`
`1402
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`Micron et al. - Exhibit 1008
`Micron et al. v. Netlist - IPR2022-00237
`Page 23 of 39
`
`

`

`atent
`
`Nov . 21 , 2017
`
`Sheet 22 of 26
`
`US 9 , 824 , 035 B2
`
`Y Boas
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`Micron et al. - Exhibit 1008
`Micron et al. v. Netlist - IPR2022-00237
`Page 24 of 39
`
`

`

`atent
`
`Nov . 21 , 2017
`
`Sheet 23 of 26
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`US 9 , 824 , 035 B2
`
`YA
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`Micron et al. - Exhibit 1008
`Micron et al. v. Netlist - IPR2022-00237
`Page 25 of 39
`
`

`

`atent
`
`Nov . 21 , 2017
`
`Sheet 24 of 26
`
`US 9 , 824 , 035 B2
`
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`From 1550 / 1650
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`FIG . 17
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`DS
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`Micron et al. - Exhibit 1008
`Micron et al. v. Netlist - IPR2022-00237
`Page 26 of 39
`
`

`

`U . S . Patent
`
`Nov . 21 , 2017
`
`Sheet 25 of 26
`
`US 9 , 824 , 035 B2
`
`1810
`
`1820
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`1830
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`centes
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`Delaying the read strobe signal and the one or more read data
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`Micron et al. - Exhibit 1008
`Micron et al. v. Netlist - IPR2022-00237
`Page 27 of 39
`
`

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`atent
`
`Nov . 21 , 2017
`
`Sheet 26 of 26
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`US 9 , 824 , 035 B2
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`- 310
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`330
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`Micron et al. - Exhibit 1008
`Micron et al. v. Netlist - IPR2022-00237
`Page 28 of 39
`
`

`

`US 9 , 824 , 035 B2
`
`memory module can be increased by increasing the number
`MEMORY MODULE WITH
`of memory devices per rank or by increasing the number of
`TIMING - CONTROLLED DATA PATHS IN
`DISTRIBUTED DATA BUFFERS
`ranks .
`In certain conventional memory modules , the ranks are
`CLAIM OF PRIORITY
`5 selected or activated by control signals from a processor or
`memory controller during operation . Examples of such
`control signals include , but are not limited to , rank - select
`The present application is a continuation of U . S . patent
`signals , also called chip - select signals . Most computer and
`application Ser . No . 14 / 846 , 993 , to be issued as U . S . Pat .
`server systems support a limited number of ranks per
`No . 9 , 563 , 587 , which is a continuation of U . S . patent
`application Ser . No . 13 / 952 , 599 , filed Jul . 27 , 2013 , issued 10 memory module , which limits the memory density of the
`as U . S . Pat . No . 9 , 128 , 632 , which claims priority to U . S .
`memory modules that can be used in these computer and
`Provisional Pat . Appl . No . 61 / 676 , 883 , filed on Jul . 27 ,
`server systems .
`2012 . Each of the above applications is incorporated by
`For memory devices in such as a memory module to be
`reference herein in its entirety .
`15 properly accessed , distribution of control signals and a
`control clock signal in the memory module is subject to strict
`CROSS REFERENCE TO RELATED
`constraints . In some conventional memory modules , control
`APPLICATIONS
`wires are routed so there is an equal length to each memory
`component , in order to eliminate variation of the timing of
`The present application is related to commonly - owned
`U . S . patent application Ser . No . 14 / 715 . 486 . filed on May 20 the control signals and the control clock signal between
`18 , 2015 ; U . S . patent application Ser . No . 13 / 970 , 606 , filed
`different memory devices in the memory modules . The
`on Aug . 20 , 2013 ; U . S . patent application Ser . No . 12 / 504 ,
`balancing of the length of the wires to each memory devices
`131 , filed on Jul . 16 , 2009 , now U . S . Pat . No . 8 , 417 , 870 ;
`compromises system performance , limits the number of
`U . S . patent application Ser . No . 12 / 761 , 179 , filed on Apr . 15 ,
`memory devices , and complicates their connections .
`2010 , now U . S . Pat . No . 8 , 516 , 185 ; U . S . patent application 25
`In some conventional memory systems , the memory
`Ser . No . 13 / 287 , 042 , filed on Nov . 1 , 2011 , now U . S . Pat .
`controllers include leveling mechanisms for write and / or
`No . 8 , 756 , 364 ; and U . S . patent application Ser . No . 13 / 287 ,
`read operations to compensate for unbalanced wire lengths
`081 , filed on Nov . 1 , 2011 , now U . S . Pat . No . 8 , 516 , 188 ;
`and memory device loading on the memory module . As
`each of which is incorporated herein by reference in its
`memory operating speed and memory density continue to
`entirety .
`30
`30 increase , however , such leveling mechanisms are also insuf
`ficient to insure proper timing of the control and / or data
`FIELD
`signals received and / or transmitted by the memory modules .
`The disclosure herein is related generally to memory
`BRIEF DESCRIPTION OF THE DRAWINGS
`modules , and more particularly to multi - rank memory mod - 35
`ules and methods of operation .
`FIG . 1 is a diagram illustrating a memory system includ
`ing at least one memory module according to one embodi
`BACKGROUND
`ment .
`FIGS . 2A - 2D are each a diagrams illustrating interactions
`With recent advancement of information technology and 40
`among components in a a memory module according to
`widespread use of the Internet to store and process infor -
`certain embodiments .
`mation , more and more demands are placed on the acqui -
`FIG . 3 is a diagram illustrating one of a plurality of data
`sition , processing , storage and dissemination of vocal , pic -
`buffers in a memory module according to one embodiment .
`torial ,
`textual
`and
`numerical
`information
`by
`FIGS . 4A - 4B are each a diagram illustrating data and data
`microelectronics - based combination of computing and com - 45
`strobe signal lines coupled to memory devices in a memory
`munication means . In a typical computer or server system ,
`module according to certain embodiments .
`memory modules are used to store data or information . A
`FIGS . 5A - 5B are diagrams illustrating different numbers
`memory module usually includes multiple memory devices ,
`of memory devices that can be coupled to each data buffer
`such as dynamic random access memory devices ( DRAM )
`a memory module according to certain embodiments .
`in
`or synchronous dynamic random access memory devices 50
`FIG . 6 is a diagram illustrating a control circuit in a data
`( SDRAM ) , packaged individually or in groups , and / or
`buffer according to certain embodiments .
`mounted on a printed circuit board ( PCB ) . A processor or a
`FIG . 7 is a diagram illustrating control signals from a
`memory controller accesses the memory module via a
`module control device to a plurality of data buffers in
`a
`memory bus , which , for a single - in - line memory module
`( SIMM ) , can have a 32 - bit wide data path , or for a dual - in - 55 memory module according to certain embodiments .
`line memory module ( DIMM ) , can have a 64 - bit wide data
`FIG . 8
`is a timing diagram illustrating alignment of
`path .
`module control signals with respect to module clock signals .
`The memory devices of a memory module are generally
`FIG . 9 is a diagram illustrating a metastability detection
`organized in ranks , with each rank of memory devices
`circuit and signal adjustment circuit in a data buffer accord
`generally having a bit width . For example , a memory 60 ing to certain embodiments .
`module in which each rank of the memory module is 64 bits
`FIGS . 10A - 10C are diagrams illustrating a metastability
`wide is described as having an “ x64 ” or “ by 64 " organiza -
`detection circuit according to certain embodiments .
`tion . Similarly , a memory module having 72 - bit - wide ranks
`FIG . 10D is a diagram illustrating a signal adjustment
`is described as having an “ x72 ” or “ by 72 ” organization .
`circuit according to certain embodiments .
`The memory capacity or memory density of a memory 65
`FIGS . 11A - 11B are diagrams illustrating a metastability
`module increases with the number of memory devices on the
`detection circuit and signal adjustment circuit , respectively ,
`memory module . The number of memory devices of a
`according to certain embodiments .
`
`Micron et al. - Exhibit 1008
`Micron et al. v. Netlist - IPR2022-00237
`Page 29 of 39
`
`

`

`5
`
`US 9 , 824 , 035 B2
`FIGS . 12A - 12B are a timing diagrams illustrating a write
`In one embodiment , each buffer circuit includes metasta
`operation and a read operation , respectively , performed by a
`bility detection circuits to detect metastability condition in
`the module control signals and signal adjustment circuits to
`memory module according to one embodiment .
`FIG . 13 is a diagram illustrating a delay control circuit in
`adjust the module control signals and / or a module clock
`signal to mitigate any metastability condition in the module
`a data buffer according to certain embodiments .
`FIG . 14 is a diagram illustrating a DQ or DQS routing
`control signals .
`Further , in one embodiment , each buffer circuit includes
`circuit in a data buffer according to an embodiment .
`signal alignment circuits that determine , during a write
`FIG . 15 a diagram illustrating a DQS routing circuit
`operation , a time interval between a time when one or more
`having a delay circuit in a data buffer according to an
`module control signals are received from the module control
`embodiment .
`circuit and a time when a strobe or data signal is received
`FIG . 16 a diagram illustrating a DQ routing circuit having
`from the memory controller . This time interval is used
`a delay circuit in a data buffer according to an embodiment .
`during a subsequent read operation to time transmission of
`FIG . 17 is a diagram illustrating a delay circuit in a DO
`read data to the memory controller , such that the read data
`or DOS routing circuit according to an embodiment .
`15 arrives at the memory controller within a time limit in
`FIG . 18 is a flowchart illustrating a method for data edge
`accordance with a read latency parameter associated with
`alignment according to embodiments .
`the memory system .
`FIG . 1 shows a system 100 including a memory controller
`FIG . 19 is a diagram illustrating a control circuit in a data
`buffer according to certain embodiments .
`( MCH ) 101 and one or more memory modules 110 coupled
`20 to the MCH by a memory bus 105 , according to one
`DESCRIPTION OF EMBODIMENTS
`embodiment . As shown , the memory bus includes C / A
`signal lines 120 and groups of system data / strobe signal
`A memory module according to one embodiment includes
`lines 130 . Also as shown , each memory module 110 has a
`plurality of memory devices 112 organized in a plurality of
`memory devices organized in groups , a module control
`device , and data buffers ( DB ) . The data buffers are some - 25 ranks 114 . Each memory module 110 further includes a
`times referred to herein as buffer circuits , isolation devices
`module control circuit ( module controller or module control
`( I . D . ) or load reduction devices . The memory module is
`device ) 116 coupled to the MCH 101 via the C / A signal lines
`operable to perform memory operations in response to
`120 , and a plurality of buffer circuits or isolation devices 118
`memory commands ( e . g . , read , write , refresh , precharge ,
`coupled to the MCH 101 via respective groups of system
`etc . ) , each of which is represented by a set of control / address 30 data / strobe signal lines 130 . In one embodiment , the
`( CIA ) signals transmitted by the memory controller to the
`memory devices 112 , the module control circuit 116 and the
`memory module . The C / A signals may include , for example ,
`isolation devices 118 can be mounted on a same side or
`a row address strobe signal ( / RAS ) , a column address strobe
`different sides of a printed circuit board ( module board ) 119 .
`signal ( ICAS ) , a write enable signal ( / WE ) , an output enable
`In the context of the present description , a rank refers to
`signal ( OE ) , one or more chip select signals , row / column 35 a set of memory devices that are selectable by a same chip
`address signals , and bank address signals . The memory
`select signal from the memory controller . The number of
`controller may also transmit a