IN THE UNITED STATES DISTRICT COURT
`FOR THE DISTRICT OF DELAWARE
`
`INTEL CORPORATION,
`
`Plaintiff,
`
`v.
`
`FUTURE LINK SYSTEMS , LLC,
`
`Defendant.
`
`C.A. No. 14-377-LPS
`
`Jack B. Blumenfeld, Maryellen Noreika, Paul Saindon, MORRIS, NICHOLS, ARSHT &
`TUNNELL LLP, Wilmington, DE
`
`Gregory S. Arovas, Jon R. Carter, KIRKLAND & ELLIS LLP, New York, NY
`
`Adam Alper, Sarah E. Piepmeier, KIRKLAND & ELLIS LLP, San Francisco, CA
`
`Michael W. De Vries, KIRKLAND & ELLIS LLP, Los Angeles, CA
`
`Attorneys for Plaintiff Intel Corporation.
`
`Brian E. Farnan, Michael J. Farnan, FARNAN LLP, Wilmington, DE
`
`Benjamin Hattenbach, Ellisen S. Turner, Richard W. Krebs, Amy E. Proctor, Dominik
`Slusarczyk, IRELL & MANELLA LLP, Los Angeles, CA
`
`Attorneys for Defendant Future Link Systems, LLC.
`
`MEMORANDUM OPINION
`
`August 2, 2016
`Wilmington, Delaware
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`On March 24, 2014, Plaintiff Intel Corporation ("Plaintiff' or "Intel") filed suit for
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`declaratory judgment that patents owned by Defendant Future Link Systems, LLC ("Defendant"
`
`or "Future Link") are "not infringed, invalid, licensed, and/or exhausted." (D .I. 1 at 1-2) Intel' s
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`initial and first-amended complaints challenged nine patents: U.S. Patent Nos. 5,608,357 ("'357
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`patent"); 5,870,570 ("' 570 patent"); 6,008,823 ('" 823 patent"); 6,108,738 ("' 738 patent");
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`6,606,576 ("' 6576 patent"); 6,622,108 ('" 108 patent"); 6,636,166 ('" 166 patent"); 6,920,576
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`('" 0576 patent"); and 7,478,302 ("' 302 patent"). (D.I. 1at2; D.I. 95 at 1-2) On September 2,
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`2015, Future Link filed a Partial Answer and Counterclaims asserting eight additional patents
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`against Intel: U.S . Patent Nos. 5,754,867 ('" 867 patent"); 6,052,754 ("' 754 patent"); 6,317,804
`
`('" 804 patent"); 7,685,439 ('" 439 patent"); 7,743,257 ('"257 patent"); 7,917,680 ('" 680 patent");
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`7,983 ,888 ('" 888 patent"); and 8,099,614 ('" 614 patent") (collectively with the nine patents
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`originally challenged by Intel, "Patents-in-Suit"). (See D.I. 135 at 40) The Patents-in-Suit relate
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`to a broad range of computer technology. 1
`
`Pending before the Court are claim construction disputes for thirteen claim terms across
`
`the following ten patents: the ' 357, '867, ' 570, ' 754, ' 804, ' 6576, ' 108, '302, ' 257, and ' 680
`
`patents.2 (D.I. 324 at 1) The parties submitted technology tutorials on April 28 (see D.I. 302,
`
`304) and completed briefing on claim construction on May 12 (D.I. 288, 290, 315, 318). The
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`1The Patents-in-Suit are attached as exhibits to Intel' s First Amended Complaint (D.I. 95)
`and Future Link's Partial Answer and Counterclaims (D.I. 135).
`
`20n May 27, the parties submitted a chart of all claims from the Patents-in-Suit that are
`either challenged by Intel (as not-infringed or invalid) and/or asserted by Future Link. (D.I. 341 )
`The Court will only construe terms that are in claims identified by the parties in this chart.
`
`1
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`Court held a claim construction hearing on June 6. (See Transcript, D.I. 351 ("Tr."))
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`I.
`
`LEGAL STANDARDS
`
`The ultimate question of the proper construction of a patent is a question of law. See
`
`Teva Phann. USA, Inc. v. Sandoz, Inc., 135 S. Ct. 831 , 837 (2015) (citing Markman v. Westview
`
`Instruments, Inc., 517 U. S. 370, 388-91 (1996)). "It is a bedrock principle of patent law that the
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`claims of a patent define the invention to which the patentee is entitled the right to exclude."
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`Phillips v. A WH Corp., 415 F.3d 1303, 1312 (Fed. Cir. 2005) (internal quotation marks omitted).
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`" [T]here is no magic formula or catechism for conducting claim construction." Id. at 1324.
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`Instead, the court is free to attach the appropriate weight to appropriate sources "in light of the
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`statutes and policies that inform patent law." Id.
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`" [T]he words of a claim are generally given their ordinary and customary meaning .. .
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`[which is] the meaning that the term would have to a person of ordinary skill in the art in
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`question at the time of the invention, i.e., as of the effective filing date of the patent application."
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`Id. at 1312-13 (internal citations and quotation marks omitted). " [T]he ordinary meaning of a
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`claim term is its meaning to the ordinary artisan after reading the entire patent." Id. at 1321
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`(internal quotation marks omitted). The patent specification "is always highly relevant to the
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`claim construction analysis. Usually, it is dispositive; it is the single best guide to the meaning of
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`a disputed term." Vitronics Corp. v. Conceptronic, Inc., 90 F.3d 1576, 1582 (Fed. Cir. 1996).
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`While "the claims themselves provide substantial guidance as to the meaning of particular
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`claim terms," the context of the surrounding words of the claim also must be considered.
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`Phillips, 415 F.3d at 1314. Furthermore, " [o]ther claims of the patent in question, both asserted
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`and unasserted, can also be valuable sources of enlightenment . .. [b ]ecause claim terms are
`
`2
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`normally used consistently throughout the patent ... . " Id. (internal citation omitted).
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`It is likewise true that " [ d]ifferences among claims can also be a useful guide .... For
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`example, the presence of a dependent claim that adds a particular limitation gives rise to a
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`presumption that the limitation in question is not present in the independent claim." Id. at 1314-
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`15 (internal citation omitted). This "presumption is especially strong when the limitation in
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`dispute is the only meaningful difference between an independent and dependent claim, and one
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`party is urging that the limitation in the dependent claim should be read into the independent
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`claim." SunRace Roots Enter. Co., Ltd. v. SRAM Corp., 336 F.3d 1298, 1303 (Fed. Cir. 2003).
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`It is also possible that "the specification may reveal a special definition given to a claim
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`term by the patentee that differs from the meaning it would otherwise possess. In such cases, the
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`inventor' s lexicography governs." Phillips, 415 F.3d at 1316. It bears emphasis that " [e]ven
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`when the specification describes only a single embodiment, the claims of the patent will not be
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`read restrictively unless the patentee has demonstrated a clear intention to limit the claim scope
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`using words or expressions of manifest exclusion or restriction." Hill-Rom Servs., Inc. v. Stryker
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`Corp ., 755 F.3d 1367, 1372 (Fed. Cir. 2014) (quoting Liebel-Flarsheim Co. v. Medrad, Inc., 358
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`F.3d 898, 906 (Fed. Cir. 2004)) (internal quotation marks omitted).
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`In addition to the specification, a court "should also consider the patent's prosecution
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`history, if it is in evidence." Markman v. Westview Instruments, Inc., 52 F.3d 967, 980 (Fed. Cir.
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`1995), aff'd, 517 U. S. 370 (1996). The prosecution history, which is "intrinsic evidence,"
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`"consists of the complete record of the proceedings before the PTO [Patent and Trademark
`
`Office] and includes the prior art cited during the examination of the patent." Phillips, 415 F.3d
`
`at 1317. " [T]he prosecution history can often inform the meaning of the claim language by
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`3
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`demonstrating how the inventor understood the invention and whether the inventor limited the
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`invention in the course of prosecution, making the claim scope narrower than it would otherwise
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`be." Id.
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`In some cases, ''the district court will need to look beyond the patent's intrinsic evidence
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`and to consult extrinsic evidence in order to understand, for example, the background science or
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`the meaning of a term in the relevant art during the relevant time period." Teva , 135 S. Ct. at
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`841 . Extrinsic evidence "consists of all evidence external to the patent and prosecution history,
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`including expert and inventor testimony, dictionaries, and learned treatises." Markman , 52 F.3d
`
`at 980. For instance, technical dictionaries can assist the court in determining the meaning of a
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`term to those of skill in the relevant art because such dictionaries "endeavor to collect the
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`accepted meanings of terms used in various fields of science and technology." Phillips, 415 F.3d
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`at 1318. In addition, expert testimony can be useful "to ensure that the court' s understanding of
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`the technical aspects of the patent is consistent with that of a person of skill in the art, or to
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`establish that a particular term in the patent or the prior art has a particular meaning in the
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`pertinent field ." Id. Nonetheless, courts must not lose sight of the fact that "expert reports and
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`testimony [are] generated at the time of and for the purpose of litigation and thus can suffer from
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`bias that is not present in intrinsic evidence." Id. Overall, while extrinsic evidence "may be
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`useful" to the court, it is "less reliable" than intrinsic evidence, and its consideration "is unlikely
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`to result in a reliable interpretation of patent claim scope unless considered in the context of the
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`intrinsic evidence." Id. at 1318-19. Where the intrinsic record unambiguously describes the
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`scope of the patented invention, reliance on any extrinsic evidence is improper. See Pitney
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`Bowes, Inc. v. Hewlett-Packard Co. , 182 F.3d 1298, 1308 (Fed. Cir. 1999) (citing Vitronics, 90
`
`4
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`F.3d at 1583).
`
`Finally, "[t]he construction that stays true to the claim language and most naturally aligns
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`with the patent' s description of the invention will be, in the end, the correct construction."
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`Renishaw PLC v. Marposs Societa ' per Azioni, 158 F.3d 1243, 1250 (Fed. Cir. 1998). It follows
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`that "a claim interpretation that would exclude the inventor's device is rarely the correct
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`interpretation." Osram GmbHv. Int '! Trade Comm 'n, 505 F.3d 1351 , 1358 (Fed. Cir. 2007)
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`(quoting Modine Mfg. Co. v. U S Int'! Trade Comm 'n, 75 F.3d 1545, 1550 (Fed. Cir. 1996)).
`
`II.
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`CONSTRUCTION OF DISPUTED TERMS3
`
`A.
`
`'357 Patent
`
`"buffer memory ... for removing jitter"4
`
`Future Link
`"buffer memory ... for removing the offset of data transition locations from their ideally
`clocked positions"
`
`Intel
`"buffer memory . .. for the intended purpose of eliminating dynamic or short-term skews from
`an ideal signal"
`
`Court
`"buffer memory .. . for removing the offset of data transition locations from their ideally
`clocked positions"
`
`The parties have several disputes related to this claim term. First, the parties dispute
`
`whether the word "removing" should be given its plain and ordinary meaning or whether it
`
`should be construed as "eliminating" all jitter. The Court agrees with Future Link that the word
`
`"removing" does not require elimination of all jitter. The plain and ordinary meaning of
`
`3The parties have agreed to certain constructions, all of which the Court will adopt.
`
`4This term appears in claims 1-27 of the ' 357 patent.
`
`5
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`"removing" is not synonymous with "removing all." Moreover, the specification of the '357
`
`patent discloses embodiments of the invention that are not designed to remove all jitter. (See
`
`'357 patent at 10:38-41 ("[T]he FIFO device (or phase aligning system) may also include a bit
`
`slip detect circuit 962 which produces an error signal 964 when the amount of jitter is too much
`
`for the phase aligning system 300 to absorb.") (emphasis added); id. at 5:3-4 (describing "phase
`
`aligning system 300" as embodiment of invention); see also id. at 8:53-54 ("[T]he jitter up to a
`
`predetermined amount is removed by the FIFO device 800.") (emphasis added); id. at 9:27-30
`
`("In this implementation, the maximum jitter amount that the FIFO device 800 can handle is
`
`four unit interval if data is arriving too fast and three unit intervals if the data is arriving too
`
`slow.") (emphasis added)) Because Intel' s proposed construction reads in a limitation that is not
`
`required by the specification, and because the word "removing" is sufficiently understandable for
`
`a jury without further construction, the Court will construe the word "removing" to have its plain
`
`and ordinary meaning, as proposed by Future Link.
`
`Next, the parties dispute the definition of 'jitter." Future Link proposes a definition from
`
`a patent cited during prosecution of the ' 357 patent. (D.I. 288 at 2) (citing U.S. Patent No.
`
`4,821 ,297 at 7: 1-4 (defining jitter as "the offset of data transition locations from their ideally
`
`clocked positions")) Intel argues that the specification "explicitly defines 'jitter"' as "dynamic
`
`skews." (D.I. 290 at 4) Intel also cites extrinsic dictionary definitions of "jitter" as "short-term
`
`skews." (Id.) The Court agrees with Future Link' s definition of jitter. Rather than narrowly
`
`define "jitter," the entirety of the intrinsic record- including the cited-patent source of Future
`
`Link' s definition of "jitter" - appears to characterize "jitter" as a broader term which
`
`encompasses, but is not limited to, the "dynamic skews" mentioned in the ' 357 patent.
`
`6
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`Therefore, the Court will adopt Future Link's definition of "jitter."
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`Finally, the parties dispute whether the Court should construe this term to include an
`
`"intended purpose" for the "buffer memory" component referred to in the disputed term. The
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`Court agrees with Future Link that the intrinsic record does not require an "intent" element to be
`
`added to the Court' s construction. The Court agrees with Future Link that Intel' s cited portions
`
`of the intrinsic record refer to an outcome that the buffer memory provides rather than an
`
`aspirational objective of the buffer memory component. (See D.I. 315 at 2) In addition, the
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`Court agrees with Future Link that there is no disclaimer or disavowal in the specification or
`
`prosecution history that would require Intel' s "intended purpose" limitation. (See id. at 3)
`
`For the foregoing reasons, the Court will adopt Future Link's proposed construction for
`
`this term.
`
`B.
`
`'867 Patent
`
`"means for selecting an external to internal clock frequency ratio" 5
`
`Future Link
`Function: "selecting an external to internal clock frequency ratio"
`
`Structure: "a signal sent to a BUS FREQUENCY pin of the CPU"
`
`Intel
`Function: "selecting an external to internal clock frequency ratio"
`
`Structure: "a signal sent to a RESET pin, a RESET pin, a signal sent to a BUS FREQUENCY
`pin, and a BUS FREQUENCY pin"
`
`5This term appears in claims 1, 2, and 4 of the '867 patent.
`
`7
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`Court
`Function: "selecting an external to internal clock frequency ratio"
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`Structure: "a signal sent to a RESET pin, a RESET pin, a signal sent to a BUS FREQUENCY
`pin, and a BUS FREQUENCY pin"
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`The parties agree that this term should be construed pursuant to 35 U.S .C. § 112, ii 6.6
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`The parties also agree upon the function for this means-plus-function term. The parties disagree,
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`however, about the corresponding structure. Intel argues that RESET and BUS FREQUENCY
`
`pins and corresponding signals are required to select an external to internal clock frequency ratio.
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`Future Link argues that only a BUS FREQUENCY signal is required. The Court agrees with
`
`Intel's proposed construction.
`
`The language of claim 1 makes clear that "altering said means for selecting an external to
`
`internal clock frequency ratio" is done "to lower the power consumption by said CPU and
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`therefor power consumption of said computer system while maintaining maximum performance
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`of said computer system." (' 867 patent at 3:47-53) Therefore, according to the claim language,
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`only the "means for selecting an external to internal clock frequency ratio" may accomplish these
`
`claimed objectives by being "alter[ed]." In addition, there is only one structure described in the
`
`specification that, when altered, will accomplish the claimed power consumption and
`
`performance characteristics - namely, the combination of RESET and BUS FREQUENCY pins
`
`with signals sent to these respective pins. (See id. at 3: 10-20) The specification clearly requires
`
`use of the RESET pin to select a frequency ratio. (See id. at 3: 17-20)
`
`Future Link argues that the function associated with this term requires "selecting" and
`
`6The parties agree as to the applicability of 35 U.S.C. § 112, ii 6 for all of the disputed
`means-plus-function terms in the Patents-in-Suit.
`
`8
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`attempts to distinguish "selecting" from actually "changing" the frequency ratio. (D.l. 288 at 6-
`
`8) However, as already discussed, the surrounding claim language indicates that the "means for
`
`selecting" must actually change the frequency ratio. "Proper claim construction ... demands
`
`interpretation of the entire claim in context, not a single element in isolation."
`
`Hockerson-Halberstadt, Inc. v. Converse Inc., 183 F.3d 1369, 1374 (Fed. Cir. 1999). The Court
`
`rejects Future Link' s attempt to distinguish "select" from "change."7
`
`Future Link also argues that the doctrine of claim differentiation supports a presumption
`
`that the "power-on reset means for selecting an external to internal clock frequency ratio" recited
`
`in claim 5 is not present in claim 1 and, therefore, that the RESET pin and signal are not required
`
`elements of the structure recited in claim 1. (See D.l. 315 at 7) The Court agrees that the
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`additional ''power-on" limitation in claim 5 narrows claim 5' s scope from what is claimed in
`
`claim 1. However, this narrowing does not necessarily mean that a RESET pin and signal are not
`
`included in claim 1. In fact, both claims require "reset" functionality, for the reasons described
`
`above. Claim 5 is nevertheless narrower because it requires a reset at "power-on" while claim 1
`
`does not. '"It is not necessary that each claim read on every embodiment. '" PPC Broadband,
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`Inc. v. Corning Optical Commc 'ns RF, LLC, 815 F.3d 747, 755 (Fed. Cir. 2016) (quoting Baran
`
`v. Med. Device Techs., Inc. , 616 F.3d 1309, 1316 (Fed. Cir. 2010)).
`
`7Future Link draws attention to Intel ' s originally proposed construction for the structure
`associated with this term: "a RESET pin and a BUS FREQUENCY pin, which are a physical
`pin that resets the processor and a physical pin used to select the external to internal clock
`frequency ratio, respectively." (D.I. 288 at 7) (emphasis in original) Future Link argues that this
`construction shows how Intel's "additional structure ... performs a function different than the
`recited function of ' selecting,"' namely, "reset[ing]." (Id. ) The Court declines to give
`dispositive weight to a construction that was later abandoned by Intel. In addition, as already
`explained, the "selecting" and "changing" here are accomplished by the same structure and
`describe the same functionality.
`
`9
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`For the foregoing reasons, the Court will adopt Intel 's proposed construction for this
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`term.
`
`C.
`
`'570 Patent
`
`"identification device select decoder" 8
`
`Future Link
`"a decoder that identifies the target of a configuration access"
`
`Intel
`"a decoder of an initialization device select (IDSEL) signal, as defined by the PCI Local Bus
`Specification"
`
`Court
`"a PCI-compliant decoder that identifies the target of a configuration access"
`
`Intel argues that this term should be limited to cover only a decoder of a specific signal
`
`used in the Peripheral Component Interconnect ("PCI") architecture. (See D.I. 290 at 9-12)
`
`Future Link argues for a broader construction that tracks language from the specification. (See
`
`D.I. 288 at 8-11) (citing '570 patent at 8:66-9:1 ) The Court will include the language from
`
`Future Link's proposed construction in the Court's construction, because it will aid the jury by
`
`describing the function of an "identification device select decoder" in the context of the patent.
`
`However, the Court will also include in its construction a requirement that the decoder must be
`
`PCI-compliant. The intrinsic record strongly supports the conclusion that the scope of the claims
`
`is limited to PCI-compliant embodiments and Future Link has identified no evidence to the
`
`contrary.
`
`Future Link argues that this term should not be limited to covering only decoders of an
`
`initialization device select ("IDSEL") signal defined in PCI specifications. There is substantial
`
`8This term appears in claims 1-14 and 17-18 ofthe ' 570 patent.
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`10
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`intrinsic evidentiary support for Future Link' s position. For example, claim 17 includes the term
`
`"identification device select decoder" without referring to PCI. In this regard, claim 17 stands in
`
`contrast to all of the other claims in the ' 570 patent, each of which explicitly refer to PCI. The
`
`prosecution history reveals that this distinction between claim 1 7 and the other claims was
`
`purposeful, in that the applicants purposely attempted to remove "the limitation of PCI
`
`compliance" from claim 17 during prosecution. (D.I. 276-7 Ex. NN at 6-7) Claim 18, which
`
`depends from claim 1 7 and was added concurrently with claim 1 7, adds a limitation that the "bus
`
`agents" referenced in claim 17 must be PCI-compliant, invoking a claim-differentiation
`
`presumption that at least the bus agents in claim 17 need not be PCI-compliant. In light of the
`
`above, the Court rejects Intel ' s construction as overly narrow, because the prosecution history
`
`clearly evinces the applicants ' intent to broaden claim 17, and because there is no disclaimer or
`
`disavowal in the intrinsic evidence that would require this term to be limited to any specific
`
`version of the PCI specifications or to the IDSEL signal described therein.
`
`However, the Court agrees with Intel that this claim term should be limited to PCI bus
`
`architectures. The specification of the ' 570 patent makes it clear that the invention is limited to
`
`implementations on PCI bus architectures. (See, e.g. , ' 570 patent at 4:17-18) ("The system of the
`
`present invention provides sufficient resources to ensure PCI bus protocols are complied with.")
`
`Plaintiff acknowledges that all of the embodiments disclosed in the specification include PCI.
`
`(See Tr. at 67) The entirety of the "Disclosure of the Invention" section of the patent exclusively
`
`refers to PCI functionality. (See id. at 3:48-4:27) Every embodiment disclosed in the detailed
`
`description of the invention uses PCI. (See generally id. at 4:57-10:50; see also MySpace, Inc. v.
`
`GraphOn Corp. , 672 F.3d 1250, 1256 (Fed. Cir. 2012) ("An inventor is entitled to claim in a
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`11
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`patent what he has invented, but no more."))
`
`Intel' s arguments regarding the prosecution history of the ' 570 patent are also persuasive.
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`Intel points out that, although the bus agents recited in claim 17 do not need to be PCI-compliant
`
`after addition of claims 17 and 18 during prosecution, the "multiple bus agent integrated circuit
`
`device" claimed in claim 17 still includes an "identification device select decoder" which is
`
`defined in relation to PCI specifications. (D.I. 290 at 12) In fact, the only "identification device
`
`select decoder" referred to in the specification is PCI-compliant. (See '570 patent at 4:46-48
`
`(referring to Figure 6 as depiction of "identification device select decoder"); id. at 8 :42-9:36
`
`(describing identification device select decoder in Figure 6 as PCI-compliant)) Thus, claim 17's
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`removal of all express references to "PCI" will not be construed as broadening the scope of the
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`claims beyond the PCI-compliant device that the applicants described as their invention in the
`
`specification. Honeywell, 452 F.3d at 1319.
`
`For the foregoing reasons, the Court will construe "identification device select decoder"
`
`as "a PCI-compliant decoder that identifies the target of a configuration access."
`
`D.
`
`'754 Patent
`
`"external bus control circuit"9
`
`Future Link
`"circuitry which controls the shared signals of the circuit blocks, and which is external to the
`plurality of circuit blocks"
`
`Intel
`"circuitry external to a circuit block that allows the circuit block to be connected to a wide
`variety of shared bus standards while the circuit block' s internal circuitry remains unchanged"
`
`9This term appears in claims 1-3, 5, 7-9, and 14 of the ' 754 patent.
`
`12
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`Court
`"circuitry external to circuit blocks, wherein the circuitry is part of an apparatus for providing
`communication that allows a plurality of circuit blocks to be connected to a wide variety of
`shared bus standards while the circuit blocks' internal circuitry remains unchanged"
`
`Intel argues that this term should be limited to implementing a key advantage of the
`
`invention: providing a system "which enables circuit components of a computer system to be
`
`connected in a wide variety of shared bus schemes while remaining substantially unchanged."
`
`(' 754 patent at 2:23-26) The Court agrees that the claims must be limited to covering only
`
`apparatuses that implement this key advantage. The specification shows a clear intention to
`
`exclude implementations that do not include this key advantage by defining the invention as
`
`"provid[ing] this advantage" and by disparaging prior art implementations that do not include the
`
`advantage. (See id. at 2:5-34) The Court rejects Future Link' s proposed construction because it
`
`does not include this limitation.
`
`The parties' proposed constructions may imply that the "external bus control circuits" are
`
`the only components that control connection to a bus or busses in independent claims 1 and 9.
`
`The claim language indicates that "an external arbitration control unit" in claim 1 or "an external
`
`address arbitration control unit" in claim 9 are also involved in establishing communication
`
`pathways involving the bus or busses. The Court' s construction includes the key advantage
`
`discussed above without implying that the external bus control circuits are the sole components
`
`controlling bus arbitration, which may otherwise be confusing to a jury. Independent claims 1
`
`and 9 are each broadly directed to an "apparatus for providing communication," and it is the
`
`"apparatus" as a whole that must implement the key advantage rather than the external bus
`
`control circuits by themselves.
`
`13
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`For the foregoing reasons, the Court will construe "external bus control circuit" to mean
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`"circuitry external to circuit blocks, wherein the circuitry is part of an apparatus for providing
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`communication that allows a plurality of circuit blocks to be connected to a wide variety of
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`shared bus standards while the circuit blocks ' internal circuitry remains unchanged."
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`"slave port" 10
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`Future Link
`"a port which is capable of accepting a read and/or write cycle from another module"
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`Intel
`"interface circuitry directed by a master port and capable of transmitting and receiving
`information to and from the master port"
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`Court
`"a port which is capable of responding to a master port by transmitting information, receiving
`information, or both"
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`Intel proposes replacing the word "port" in this term with "interface circuitry" (D.I. 318 at
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`14), while Future Link disagrees (D.I. 288 at 14-15). The Court agrees with Future Link that
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`inclusion of "interface circuitry" in the Court' s construction for this term is unnecessary and
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`could potentially confuse a jury.
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`Regarding the word "slave," the Court rejects both parties' proposed constructions.
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`Future Link attempts to read in a limitation from the embodiment depicted in Figure 3 and
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`described in accompanying text. (See D.I. 288 at 14) (citing '754 patent at 6:61-64) There is no
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`clear intention in the specification to limit the claims to the embodiment shown in Figure 3.
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`Therefore, the Court rej ects Future Link' s proposed construction.
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`Intel 's proposed construction would require the slave port to be "directed by a master
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`10This term appears in claims 1-3, 5, 7-9, and 14 of the ' 754 patent.
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`14
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`port." The claims do not clearly require such direction. The Court agrees with Future Link's
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`argument that "the remaining claim language [in independent claims 1 and 9] ' for responding to
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`a master port in transmitting or receiving information' strongly implies that ' slave port' should
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`not itself be defined according to its communication capabilities relative to a master port, as Intel
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`suggests." (D.I. 288 at 15) The claims make clear that direction of the slave port is not entirely
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`accomplished by the master port, as could be implied in Intel's construction. (See, e.g., ' 754
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`patent, claim 1 at 24:49-53) (reciting "external arbitration control unit" that "establish[ es]
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`dedicated communication pathways" between master and slave ports)
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`The claim language requires that the slave port respond to a master port by "transmitting
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`or receiving information." The Court agrees with Future Link that "transmitting or receiving" in
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`the context of the specification (' 754 patent at 6:61-64) can cover ports that are capable of
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`performing one or both of these functions . Therefore, the Court will include a limitation to this
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`effect.
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`For the foregoing reasons, the Court will construe "slave port" as "a port which is capable
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`of responding to a master port by transmitting information, receiving information, or both."
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`E.
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`'804 Patent
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`"serial port" 11
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`Future Link
`"a port that transfers bits, characters, or data units sequentially"
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`Intel
`"a port that transfers data one bit at a time"
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`11This term appears in claims 1-5, 8, 9, 16-18, 21 -24, 26-28, and 40 of the ' 804 patent.
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`Court
`"a port that transfers information sequentially"
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`Intel ' s proposed construction is contradicted by the intrinsic evidence. Although the
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`specification does not explicitly define the term "serial port," Figure 1 shows five serial ports
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`(labeled 40, 42, 44, 46, and 48) that each communicate over dedicated "data," "command," and
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`"clock" lines. (See ' 804 patent at 5:29-43) For a "read request command," certain information is
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`"supplied on the data line concurrently with the read request command on the command line."
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`(See id. at 9:65-67) Thus, the specification contemplates transfer of information to "serial ports"
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`on multiple lines concurrently instead of "one bit at a time" on a single line, as implied by Intel ' s
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`proposed construction.
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`Future Link ' s proposed construction is better-aligned with the intrinsic evidence, and the
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`Court bases its construction on the intrinsic evidence. Future Link' s construction also aligns
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`with the extrinsic evidence presented by Intel. (See, e.g., D.I. 290 at 16 n.6) (Intel citing
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`dictionary definitions) As persuasively summarized by Future Link, Intel ' s extrinsic evidence
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`demonstrates that "the term ' serial "' means that information is "transferred sequentially" in
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`"single or multi-bit" units. (See D.I. 315 at 16) Thus, the Court will construe this term according
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`to Future Link' s proposed construction, but with the word "information" used in place of "bits,
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`characters, or data units," because the latter phrase is vague (at least with respect to "data units")
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`and may confuse a jury.
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`For the foregoing reasons, the Court will construe "serial port" as "a port that transfers
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`information sequentially."
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`16
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`F.
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`'6576 Patent
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`"calibration path for data calibration" 12
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`Future Link
`"a path for passing calibration data between at least two nodes"
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`Intel
`"a path between at least two nodes for passing calibration information that is distinct from the
`data paths"
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`Court
`"a path for passing calibration data between at least two nodes"
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`Intel argues that the "calibration path" in this term must be "distinct from the data paths."
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`Intel' s proposed construction could be read as excluding at least one embodiment disclosed in the
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`specification. (See ' 6576 patent at 4:45-60) ("In one example embodiment, this additional
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`calibration path is selectively assigned to act either as a calibration data path for passing
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`calibration data or as one of the data paths for passing a respective one of the N bits of data in
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`parallel. In one application, this selective assignment rotates through each of the M data paths
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`while using the remaining M-1 data paths for passing . . . data unrelated to the calibration[].").
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`Intel argues that the prosecution history evidences a disavowal of calibration paths that
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`are not distinct fr