Case 1:14-cv-00377-LPS Document 303 Filed 04/28/16 Page 1 of 39 PageID #: 13545
`
`IN THE UNITED STATES DISTRICT COURT
`FOR THE DISTRICT OF DELAWARE
`
`INTEL CORPORATION,
`
`Plaintiff and Counterclaim-Defendant,
`
`v.
`
`FUTURE LINK SYSTEMS, LLC,
`
`Defendant and Counterclaimant.
`
`)
`)
`)
`)
`)
`)
`)
`)
`)
`
`Civil Action No. 14-377 (LPS)
`
`CONFIDENTIAL – FILED UNDER
`SEAL
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`CONTAINS MATERIAL DESIGNATED
`OUTSIDE COUNSEL EYES ONLY
`
`FUTURE LINK’S OPENING CLAIM CONSTRUCTION BRIEF
`
`Dated: April 21, 2016
`
`Benjamin Hattenbach (admitted pro hac vice)
`Ellisen S. Turner (admitted pro hac vice)
`Richard W. Krebs (admitted pro hac vice)
`Amy E. Proctor (admitted pro hac vice)
`Dominik Slusarczyk (admitted pro hac vice)
`IRELL & MANELLA LLP
`1800 Avenue of the Stars, Suite 900
`Los Angeles, California 90067-4276
`Telephone: (310) 277-1010
`Facsimile: (310) 203-7199
`bhattenbach@irell.com
`eturner@irell.com
`rkrebs@irell.com
`aproctor@irell.com
`dslusarczyk@irell.com
`
`Brian E. Farnan (Bar No. 4089)
`Michael J. Farnan (Bar No. 5165)
`FARNAN LLP
`919 N. Market Street, 12th Street
`Wilmington, Delaware 19801
`Telephone: (302) 777-0300
`Facsimile: (302) 777-0301
`bfarnan@farnanlaw.com
`mfarnan@farnanlaw.com
`
`Attorneys for Defendant
`Future Link Systems, LLC
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`IPR2022-00208
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`Case 1:14-cv-00377-LPS Document 303 Filed 04/28/16 Page 2 of 39 PageID #: 13546
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`TABLE OF CONTENTS
`
`Page
`
`INTRODUCTION ........................................................................................................................ 1 
`
`ARGUMENT
`
`US Patent No. 5,608,357 (’357 Patent)......................................................................................... 2 
`
`1. 
`
`“buffer memory . . . for removing jitter” (all asserted claims) ......................................... 2 
`
`1. 
`
`Future Link’s Construction Is Consistent with the Intrinsic Evidence ................. 2 
`
`(a) 
`
`(b) 
`
`“Removing” Does Not Require Construction ........................................... 2 
`
`“Jitter” Should Be Defined Using the Intrinsic Evidence ......................... 2 
`
`2. 
`
`Intel Seeks to Narrow and Redraft the Claim Language by Adding
`Requirements that the Intrinsic Record Does Not Support ................................... 3 
`
`(a) 
`
`(b) 
`
`(c) 
`
`Adding a Mens Rea Requirement Would Be Improper ............................ 3 
`
`Changing “Removing” to “Eliminating” Could Improperly
`Narrow the Claims Without Clarifying Their Meaning ............................ 3 
`
`Intel’s Proposed Definition of “Jitter” Is Confusing and
`Unhelpful .................................................................................................. 5 
`
`U.S. Patent No. 5,754,867 (’867 Patent)....................................................................................... 5 
`
`2. 
`
`“means for selecting an external to internal clock frequency ratio” ................................. 5 
`
`1. 
`
`2. 
`
`Future Link’s Construction Tracks the Patent’s Disclosure Verbatim ................. 6 
`
`Intel Improperly Seeks to Add Structure that It Admits Performs the
`Function of “Changing,” Not the Claimed Function of “Selecting” .................... 6 
`
`U.S. Patent No. 5,870,570 (’570 Patent)....................................................................................... 8 
`
`3. 
`
`“identification device select decoder” (claim 17) ............................................................. 8 
`
`1. 
`
`2. 
`
`Future Link’s Construction Adds Clarity from the Specification ......................... 8 
`
`Intel’s Proposed Construction Only Adds an Improper Limitation ...................... 9 
`
`U.S. Patent No. 6,052,754 (‘754 Patent)..................................................................................... 11 
`
`4. 
`
`“external bus control circuit” (all asserted claims) ......................................................... 12 
`
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`Page
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`1. 
`
`2. 
`
`Future Link’s Construction Is from the Intrinsic Evidence ................................ 12 
`
`Intel Seeks to Transform Goals and Benefits into Claim Elements .................... 12 
`
`5. 
`
`“slave port” (’754, all asserted claims) ........................................................................... 14 
`
`1. 
`
`2. 
`
`Future Link’s Construction Comes Straight from the Specification .................. 14 
`
`Intel’s Construction Is Unclear and Contradicts Intrinsic Evidence ................... 14 
`
`U.S. Patent No. 6,317,804 (’804 Patent)..................................................................................... 16 
`
`6. 
`
`“serial port” (all asserted claims) .................................................................................... 16 
`
`1. 
`
`2. 
`
`Intrinsic and Extrinsic Evidence Support Future Link’s Construction ............... 16 
`
`Intel’s Proposed Construction Directly Contradicts the Intrinsic
`Evidence and Its Own Use of the Term “Serial” ................................................ 18 
`
`U.S. Patent No. 6,606,576 (’6576 Patent) ................................................................................... 18 
`
`7. 
`
`“calibration path for data calibration” (all asserted claims) ............................................ 19 
`
`1. 
`
`2. 
`
`Future Link’s Construction Tracks the Claim Language .................................... 19 
`
`Intel Reverses Key Language and Contradicts the Intrinsic Evidence ............... 20 
`
`8. 
`
`“means for comparing a sequence of data over the calibration path relative to a
`matched sequence of data being passed on one of the multiple paths” .......................... 21 
`
`U.S. Patent No. 6,622,108 (’108 Patent)..................................................................................... 22 
`
`9. 
`
`“testing the interconnects” (all asserted claims) ............................................................. 22 
`
`U.S. Patent No. 7,478,302 (’302 Patent)..................................................................................... 24 
`
`10. 
`
`“functional block” / “module(s)” (all asserted claims) ................................................... 24 
`
`U.S. Patent No. 7,743,257 (’257 Patent)..................................................................................... 26 
`
`11. 
`
`“block” (all asserted claims) ........................................................................................... 27 
`
`U.S. Patent No. 7,917,680 (’680 Patent)..................................................................................... 28 
`
`“packet-based communications” / “communicating packet data” .................................. 28 
`
`“generating a performance-based communications order” / “performance
`arbiter configured and arranged to order the packet data” .............................................. 29 
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`- ii -
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`12. 
`
`13. 
`
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`CONCLUSION ........................................................................................................................... 30 
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`Page
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`Case 1:14-cv-00377-LPS Document 303 Filed 04/28/16 Page 5 of 39 PageID #: 13549
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`
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`TABLE OF PATENTS
`
`Patent
`
`U.S. Patent 5,608,357
`
`U.S. Patent 5,754,867
`
`U.S. Patent 5,870,570
`
`U.S. Patent 6,052,754
`
`U.S. Patent 6,317,804
`
`U.S. Patent 6,606,576
`
`U.S. Patent 6,622,108
`
`U.S. Patent 7,478,302
`
`U.S. Patent 7,743,257
`
`U.S. Patent 7,917,680
`
`
`
`Exhibit
`
`A1,2
`
`B
`
`C
`
`D
`
`E
`
`F
`
`G
`
`H
`
`I
`
`J
`
`
`1 The exhibit numbers in this table correspond to the exhibits filed with the parties’ Joint Claim
`Construction Chart (D.I. 275 & 276).
`2 Unless otherwise noted, all emphasis in case or document quotations has been added and
`any internal quotations and subsequent history have been omitted from the citations.
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`TABLE OF AUTHORITIES
`
`Page(s)
`
`Cases 
`
`Abbott Labs. v. Sandoz, Inc.,
`544 F.3d 1341 (Fed. Cir. 2008).................................................................................. 28
`
`Abtox, Inc. v. Exitron Corp.,
`122 F.3d 1019 (Fed. Cir. 1997).................................................................................... 1
`
`ADC Telecomm’ns Inc. v. Switchcraft, Inc.,
`No 04–1590 ADM/JSM, 2005 WL 2206115 (D. Minn. Sept. 9, 2005) ...................... 3
`
`Asyst Techs., Inc. v. Empak, Inc.,
`268 F.3d 1364 (Fed. Cir. 2001).............................................................................. 8, 22
`
`Bd. of Trustees of Leland Stanford Junior Univ. v. Roche Molecular Sys., Inc.,
`528 F. Supp. 2d 967 (N.D. Cal. 2007) ....................................................................... 29
`
`Caluori v. One World Techs., Inc.,
`No. CV 07–2035 CAS (VBKx), 2010 WL 4794234 (C.D. Cal. Nov. 12, 2010) ...... 28
`
`Certusview Techs. LLC v. S & N Locating Servs., LLC,
`No. 2:13CV346, 2014 WL 2090550 (E.D. Va. May 16, 2014) ................................. 25
`
`Chef Am., Inc. v. Lamb-Weston, Inc.,
`358 F.3d 1371 (Fed. Cir. 2004).................................................................................... 9
`
`Cisco Sys., Inc. v. Teleconference Sys., LLC,
`No. C 09-01550 JSW, 2011 WL 5913972 (N.D. Cal. Nov. 28, 2011) ...................... 26
`
`Ekchian v. Home Depot, Inc.,
`104 F.3d 1299 (Fed. Cir. 1997).................................................................................. 24
`
`Embrex, Inc. v. Service Eng’g Corp.,
`216 F.3d 1343 (Fed. Cir. 2000).................................................................................... 1
`
`Goss Int’l Americas, Inc. v. Graphic Mgmt. Assocs., Inc.,
`739 F. Supp. 2d 1089 (N.D. Ill. 2010) ....................................................................... 28
`
`Hilton Davis Chem. Co. v. Warner-Jenknson Co.,
`62 F.3d 1512 (Fed. Cir. 1995), rev’d on other grounds, 520 U.S. 17 (1997) .............. 3
`
`Innova/Pure Water, Inc. v. Safari Water Filtration Sys., Inc.,
`381 F.3d 1111 (Fed. Cir. 2004).................................................................................... 4
`
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`Case 1:14-cv-00377-LPS Document 303 Filed 04/28/16 Page 7 of 39 PageID #: 13551
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`Page(s)
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`Layne Christensen Co. v. Bro-Tech Corp.,
`No. 09-2381-JWL, 2011 WL 3022445 (D. Kan. July 22, 2011) ............................... 26
`
`Liebel–Flarsheim Co. v. Medrad, Inc.,
`358 F.3d 898 (Fed. Cir. 2004).................................................................................... 11
`
`Markman v. Westview Instruments, Inc.,
`52 F.3d 967 (Fed. Cir. 1995)............................................................................ 4, 24, 28
`
`Micro Chem., Inc. v. Great Plains Chem. Co.,
`194 F.3d 1250 (Fed. Cir. 1999).................................................................................... 6
`
`Negotiated Data Sols., LLC v. Dell, Inc.,
`596 F. Supp. 2d 949 (E.D. Tex. 2009) ....................................................................... 26
`
`Northrop Grumman Corp. v. Intel Corp.,
`325 F.3d 1346 (Fed. Cir. 2003).............................................................................. 7, 22
`
`O2 Micro Int'l Ltd. v. Beyond Innovation Tech. Co.,
`521 F.3d 1351, 1361 (Fed. Cir. 2008)........................................................................ 30
`
`Panel Corp. v. Mac Panel Co.,
`133 F.3d 860 (Fed. Cir. 1997)...................................................................................... 2
`
`Paragon Solutions, LLC v. Timex Corp.,
`566 F.3d 1075 (Fed. Cir. 2009).................................................................................... 3
`
`Phillips v. AWH Corp.,
`415 F.3d 1303 (Fed. Cir. 2005)........................................................................... passim
`
`Retractable Techs., Inc. v. Becton, Dickinson & Co.,
`653 F.3d 1296 (Fed. Cir. 2011).................................................................................. 14
`
`Speracor, Inc. v. Barr Pharms., Inc.,
`No. 5:08–CV–362–H(3), 2010 WL 5589104 (E.D.N.C. Sept. 8, 2010)................ 4, 10
`
`Static Control Components, Inc. v. Lexmark Intern., Inc.,
`502 F. Supp. 2d 568 (E.D. Ky 2007) ........................................................................... 4
`
`U.S. Surgical Corp. v. Ethicon Inc.,
`103 F.3d 1554 (Fed. Cir. 1997).................................................................................. 28
`
`Va. Renishaw PLC v. Marposs Societa’ per Azioni,
`158 F.3d 1243 (Fed. Cir. 1998).................................................................................... 2
`
`Versa Corp. v. Ag-Bag Intern. Ltd.,
`392 F.3d 1325 (Fed. Cir. 2004).................................................................................. 11
`
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`Case 1:14-cv-00377-LPS Document 303 Filed 04/28/16 Page 8 of 39 PageID #: 13552
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`Page(s)
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`Whittaker Corp. v. UNR Indus., Inc.,
`911 F.2d 709 (Fed. Cir. 1990)...................................................................................... 8
`
`Statutes 
`
`35 U.S.C. § 112 .................................................................................................................. 6, 22
`
`Other Authorities 
`
`Wiley Electrical And Electronics Engineering Dictionary ........................................ 16, 17, 24
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`Case 1:14-cv-00377-LPS Document 303 Filed 04/28/16 Page 9 of 39 PageID #: 13553
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`
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`INTRODUCTION
`
`Claim construction “is simply a way of elaborating the normally terse claim language: in
`
`order to understand and explain, but not to change, the scope of the claims.” Embrex, Inc. v.
`
`Service Eng’g Corp., 216 F.3d 1343, 1347 (Fed. Cir. 2000). Consistent with this guidance, Future
`
`Link’s constructions carefully focus on the actual claim language, which “frames and ultimately
`
`resolves all issues of claim interpretation.” Abtox, Inc. v. Exitron Corp., 122 F.3d 1019, 1023 (Fed.
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`Cir. 1997). Intel, in contrast, seeks not to construe claims but to redraft them. So transformational
`
`are Intel’s proposals that the claims would no longer describe the inventions that the Patent Office
`
`examined and found patentable. Gone is the plain claim language set forth in black and white. In
`
`its place, Intel inserts new phrases that would be unhelpful to a jury and are inconsistent with the
`
`evidence and the Federal Circuit’s claim construction precedent. Intel repeatedly approaches its
`
`transformative process by limiting claims to a single embodiment from a patent’s specification. For
`
`example, Intel asserts that an “identification device select decoder” should be limited to a decoder
`
`that can decode only one specific signal that was used in a specification’s merely exemplary
`
`embodiment. Worse yet, most of Intel’s constructions are transparently circular, repeating verbatim
`
`(or reordering) the terms supposedly requiring construction, but then piling on new, narrowing
`
`language that the actual claim language could never support. For example, Intel defines the term
`
`“external bus control circuit” by repeating the words “external” and “circuit” and then grafting on
`
`unrelated requirements about the capabilities of other circuits. In still other instances, Intel adds
`
`subjective intent elements that have no place in the claims’ plain meaning.
`
`It would be “unjust to the public, as well as an evasion of the law, to construe [claim
`
`language] in a manner different from the plain import of its terms,” as Intel proposes. Phillips v.
`
`AWH Corp., 415 F.3d 1303, 1312 (Fed. Cir. 2005). That straightforward guidance from the Federal
`
`Circuit resolves nearly all of the parties’ disputes here.
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`
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`bit samples to the phase decision circuit.” D.I. 275, Ex. L, col. 7:1-4. This definition properly
`
`captures jitter’s relevant meaning in a way that adds clarity. See Conte Decl., ¶¶ 17-18.
`
`2.
`
`Intel Seeks to Narrow and Redraft the Claim Language by Adding
`Requirements that the Intrinsic Record Does Not Support
`
`(a)
`
`Adding a Mens Rea Requirement Would Be Improper
`
`Intel does not propose any construction for most of the phrase it seeks to construe (“buffer
`
`memory . . . for removing jitter”). Intel’s construction simply repeats the words “buffer memory.”
`
`But to those words, Intel asks the Court to add an intent requirement that the claims never state:
`
`“for the intended purpose.” Intel thus seeks to replace the buffer memory’s recited capability and
`
`result—jitter removal—with a new requirement that a circuit designer intended to remove jitter,
`
`regardless of whether any such removal actually occurs or even could occur. Converting an
`
`outcome or a capability into a mens rea requirement is improper in this context. It is well-
`
`established that “[i]ntent is not an element of infringement.” Hilton Davis Chem. Co. v. Warner-
`
`Jenknson Co., 62 F.3d 1512, 1519 (Fed. Cir. 1995), rev’d on other grounds, 520 U.S. 17 (1997).
`
`Although a patentee can explicitly require it, intent generally should not be read into claims,
`
`particularly apparatus claims. See, e.g., Paragon Solutions, LLC v. Timex Corp., 566 F.3d 1075,
`
`1091 (Fed. Cir. 2009) (“Absent an express limitation to the contrary, any use of a device that meets
`
`all of the limitations of an apparatus claim written in structural terms infringes that apparatus
`
`claim.”); ADC Telecomms. Inc. v. Switchcraft, Inc., No 04–1590 ADM/JSM, 2005 WL 2206115,
`
`at *6 (D. Minn. Sept. 9, 2005) (rejecting an intent element because term did not “inherently
`
`require[] foreknowledge”).
`
`(b)
`
`Changing “Removing” to “Eliminating” Could Improperly Narrow
`the Claims Without Clarifying Their Meaning
`
`Intel next attempts to alter claim scope by replacing the common word “removing.” But
`
`that word is perfectly clear and understandable. Intel nonetheless attempts to substitute another
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`word for the patentee’s carefully chosen language, which the Patent Office already examined and
`
`issued. Because “removing” is a term that the jury will readily understand, deleting it favor of an
`
`alleged synonym is necessarily either improper or pointless. See Static Control Components, Inc. v.
`
`Lexmark Int’l, Inc., 502 F. Supp. 2d 568, 576 (E.D. Ky. 2007) (“The Counterclaim Defendants’
`
`exhortation to attach a synonym to self-defined and simple words invites a meaningless result that
`
`mocks the notion of construction.”).
`
`To the extent “removing” and “eliminating” have different scopes, Intel’s construction
`
`improperly revises the claims. For example: one can “remove” pollution by removing 50%, or
`
`80%, of air contaminants, but to “eliminate” pollution, one must eradicate 100% of contaminants.
`
`Altering claim scope to require complete removal is contrary to law. Alternatively, if Intel contends
`
`“removing” and “eliminating” are true synonyms, then its construction serves no purpose.
`
`Nor can Intel rely on examples from the specification to argue that the claims require jitter
`
`elimination. Again, to the extent “eliminating” and “removing” differ, the specification cannot be
`
`used to enlarge, diminish, or vary the limitations of the claims. See Markman v. Westview
`
`Instruments, Inc., 52 F.3d 967, 980 (Fed. Cir. 1995) (“The written description part of the
`
`specification itself does not delimit the right to exclude. That is the function and purpose of
`
`claims.”). Courts turn to the specification and other evidence only when necessary to give context
`
`to the claim language. Here, there is no need to redefine the term “removing.”3
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`This rule would apply even if complete removal of “jitter” was the only embodiment
`
`discussed in the specification. See Innova/Pure Water, Inc. v. Safari Water Filtration Sys., Inc.,
`
`3 The specification also uses the term “removing” (see, e.g., Abstract; 3:30), which further
`underscores that “removing” and “eliminating” have different meanings. See Speracor, Inc. v.
`Barr Pharms., Inc., No. 5:08–CV–362–H(3), 2010 WL 5589104, at *7 (E.D.N.C. Sept. 8, 2010)
`(“[T]he references to both ‘sedation and somnolence’ in the specification strongly indicate that
`the two terms have different meanings.”).
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`
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`internal clock
`frequency ratio”
`
`1.
`
`FREQUENCY pin of the CPU”4
`
`pin, a RESET pin, a signal sent to a
`BUS FREQUENCY pin, and a BUS
`FREQUENCY pin”
`Future Link’s Construction Tracks the Patent’s Disclosure Verbatim
`
`“Application of § 112, ¶ 6 requires identification of the structure in the specification which
`
`performs the recited function.” Micro Chem., Inc. v. Great Plains Chem. Co., 194 F.3d 1250, 1257
`
`(Fed. Cir. 1999). “The statute does not permit limitation of a means-plus-function claim by
`
`adopting a function different from that explicitly recited in the claim. Nor does the statute permit
`
`incorporation of structure from the written description beyond that necessary to perform the
`
`claimed function.” Id. at 1258. Here, these rules require identifying only the structure that is
`
`responsible for the recited function of selecting, which is “a signal . . . sent to a BUS
`
`FREQUENCY pin of the CPU.” ’867 Patent, 2:22-24 (“A signal is then sent to a BUS
`
`FREQUENCY pin of the CPU in order to select the desired external to internal clock frequency
`
`ratio.”). See also Figure 1; 3:11-14; Conte Decl., ¶ 21.
`
`2.
`
`Intel Improperly Seeks to Add Structure that It Admits Performs the
`Function of “Changing,” Not the Claimed Function of “Selecting”
`
`Intel initially cites the same specification passage as Future Link. But Intel then adds
`
`structure that performs an additional step beyond the recited function of “selecting an internal to
`
`external clock frequency ratio.” In particular, Intel adds structure that performs the different step of
`
`changing the external to internal clock frequency ratio, which is performed by “sending a signal to
`
`a RESET pin on the CPU.” ’867 Patent, 2:18-22. The specification is clear that the RESET pin’s
`
`“changing” function is distinct from the claimed “selecting” function: “The external to internal
`
`clock frequency ratio is then changed by sending a signal to a RESET pin of the CPU. A signal is
`
`
`4 Of course, the structures corresponding to all means-plus-function elements also properly
`include any equivalents. See, e.g., 35 U.S.C. § 112, ¶ 6 (pre-AIA).
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`then sent to a BUS FREQUENCY pin of the CPU to select the desired external to internal clock
`
`frequency ratio.” ’867 Patent, 3:10-14. The distinction between selecting and changing is
`
`underscored by the patent’s figure, which identifies the step “assert signal to RESET pin on the
`
`CPU” as a different step, in a separate box, from selecting: “send signal to BUS FREQUENCY pin
`
`on the CPU to select desired ratio.” The same distinction carries over into the claims themselves.
`
`See, e.g., ‘867 Patent, cl. 1 (“selecting”); cl. 3 (“further comprises the steps of . . . changing said
`
`means . . . and changing said external clock frequency . . . .”); cl. 4 (“said step of changing . . .
`
`further comprises the steps of: asserting a signal to a RESET pin of said CPU . . . .”).
`
`Indeed, the fact that the RESET pin and BUS FREQUENCY pin perform two different
`
`functions, and that only the signal sent to a BUS FREQUENCY pin is responsible for “selecting an
`
`external to internal clock frequency ratio,” was highlighted by Intel’s own original claim
`
`construction for this term. Intel’s original construction of this term defined the structure as “a
`
`RESET pin and a BUS FREQUENCY pin, which are a physical pin that resets the processor and
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`a physical pin used to select the external to internal clock frequency ratio, respectively.” Proctor
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`Decl., Ex. A. Intel abandoned that construction only after recognizing that it so clearly explained
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`how the additional structure (which Intel still seeks to include, now without the original italicized
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`explanatory language) performs a function different than the recited function of “selecting.”
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`The law on this point is clear: “structure disclosed in the specification is ‘corresponding’
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`structure only if the specification or the prosecution history clearly links or associates that
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`structure to the function recited in the claim.” Northrop Grumman Corp. v. Intel Corp., 325 F.3d
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`1346, 1352 (Fed. Cir. 2003). Here, there is no evidence clearly (or even otherwise) linking the
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`RESET pin and corresponding signal to the function of “selecting”; to the contrary, Intel’s
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`additional structures are clearly linked only to the distinct function of “changing.” See Conte Decl.,
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`Case 1:14-cv-00377-LPS Document 303 Filed 04/28/16 Page 16 of 39 PageID #: 13560
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`Case 1:14-cv-00377-LPS Document 303 Filed 04/28/16 Page 17 of 39 PageID #: 13561
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`tracks the specification, which explains that in PCI-compliant embodiments, “the assertion of
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`IDSEL for a particular PCI agent indicates the particular PCI agent is the target of a configuration
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`access.” ’570 Patent, 8:66-9:1. See also id. at 4:45-47 (explaining that the figure being referenced
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`at 8:66-9:1, Figure 6, “shows a diagram of an identification device select decoder in accordance
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`with one embodiment of the present invention”). The IDSEL signal is merely one example of an
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`identification device select signal within certain PCI specifications. See Conte Decl., ¶¶ 32-33. But
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`PCI’s IDSEL signal is not the only way to identify the target of a configuration access. As the
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`patent explains, the relevant field is broader than PCI, which is but one possible “expansion bus
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`architecture.” See ’570 Patent, 1:50-55; Conte Decl., ¶¶ 25-36. Given this broader context for the
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`patented inventions, Future Link’s functional definition explains the purpose of the decoder and
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`captures claim 17’s proper scope while also encompassing specific embodiments that are PCI-
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`compliant, such as dependent claim 18. See ’570 Patent, cl. 18 (adding to claim 17 the limitation
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`that the “bus agents are peripheral component interconnect (PCI) compliant.”).
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`2.
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`Intel’s Proposed Construction Only Adds an Improper Limitation
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`In contrast, Intel proposes construing the claimed decoder as “a decoder of an initialization
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`device select (IDSEL) signal, as defined by the PCI Local Bus Specification.” Remarkably, Intel
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`provides no meaning for the claim language. Instead, Intel simply redrafts the term by limiting it to
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`decoding a particular type of signal defined by one particular specification. Intel’s sole purpose in
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`proposing this term for construction is therefore to narrow it to a single embodiment. The law
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`prohibits such blatant claim redrafting. Chef Am., Inc. v. Lamb-Weston, Inc., 358 F.3d 1371, 1373
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`(Fed. Cir. 2004) (“Courts are not permitted to redraft claims.”)
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`Nor do the claims support Intel’s proposal. The term “identification device select decoder”
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`appears only in claim 17. That claim defines the type of signal that is decoded generally as “an
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`identification device select decoder signal”: “an identification device select decoder built into said
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`Case 1:14-cv-00377-LPS Document 303 Filed 04/28/16 Page 18 of 39 PageID #: 13562
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`integrated circuit, . . . coupled to said plurality of bus agents via a corresponding plurality of
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`internal identification device select decoder signal lines for routing an identification device select
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`decoder signal to any one of said plurality of bus agents.” ’570 Patent, cl. 17. When placed in
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`context, Intel’s construction first redefines the relevant signal. Then, Intel ignores the broader
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`scope that the remaining claim language explicitly provides. This results in a construction that is
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`confusing and internally inconsistent. “[T]he context in which a term is used in the asserted claim
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`can be highly instructive.” Phillips, 415 F.3d at 1314. In context, if Intel’s proposal were adopted,
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`the claim would read: “a decoder of an initialization device select (IDSEL) signal, as defined by
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`the PCI Local Bus Specification, built into said integrated circuit, . . . coupled to said plurality of
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`bus agents via a corresponding plurality of internal identification device select decoder signal lines
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`for routing an identification device select decoder signal to any one of said plurality of bus agents.”
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`Intel’s proposal therefore directly clashes with the other claim language.
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`Intel’s proposal also violates foundational rules of claim construction. First, it attempts to
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`limit broader claim language to one specific embodiment referenced in other claims. For example,
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`claim 8 is explicitly limited to an IDSEL signal (as Intel suggests limiting claim 17) (“said IDSEL
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`decoder coupled to . . . a corresponding plurality of internal IDSEL signal lines for routing an
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`IDSEL signal”); claim 17, in contrast, intentionally uses broader language (“identification device
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`select decoder”) without referencing a specific signal. The patentee’s decision to use broader
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`language in claim 17 shows an intent to claim a different scope. Speracor, 2010 WL 5589104, at
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`*7 (“[T]he references to both ‘sedation and somnolence’ in the specification strongly indicate that
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`the two terms have different meanings.”). Intel’s improper construction nullifies that intent.
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`Intel’s construction would also collapse claim 17 into claim 18, which adds only the
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`limitation that “said plurality of bus agents are peripheral component interconnect (PCI)
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`Case 1:14-cv-00377-LPS Document 303 Filed 04/28/16 Page 19 of 39 PageID #: 13563
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`compliant.”5 That violates the claim differentiation doctrine, which creates a “presumption that
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`each claim in a patent has a different scope.” Versa Corp. v. Ag-Bag Intern. Ltd., 392 F.3d 1325,
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`1330 (Fed. Cir. 2004). That doctrine applies with force here, where Intel’s construction would
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`make claim 18 superfluous. See Liebel–Flarsheim Co. v. Medrad, Inc., 358 F.3d 898, 910 (Fed.
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`Cir. 2004) (“[W]here the limitation that is sought to be ‘read into’ an independent claim already
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`appears in a dependent claim, the doctrine of claim differentiation is at its strongest.”). By defining
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`claims 17’s terms according to PCI specifications, Intel deprives claim 17 of its independent scope.
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`Finally, the prosecution history forecloses Intel’s construction. In response to an office
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`action, the patentee explained that “the limitation of PCI compliance is removed from Claim 18
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`[issued as claim 17] and added in dependent Claim 19 [issued as claim 18].” D.I. 276, Ex. NN to
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`Joint Chart (Amendment dated June 18, 1998 at pp. 6-7). Shortly thereafter, the Patent Office
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`allowed the claims, thereby authorizing claim 17 without any PCI compliance limitations. Intel
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`cannot redraft the claim to add back in what the patentee expressly removed.
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`U.S. Patent No. 6,052,754 (’754 Patent)
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`The ’754 Patent relates to a “centrally controlled interface scheme for promoting design
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`reusable circuit blocks.” ’754 Patent, Abstract. One way to allow circuit block reuse is through “the
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`sharing of signals over a shared bus scheme” that “is exclusively controlled by external bus control
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`circuits.” Id. The patent explains these benefits, but never elevates them into claim limitations: “By
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`implementing the circuit blocks and external control of the shared signals in this fashion, the bus
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`interconnec