UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`APPLE INC.
`Petitioner
`
`v.
`
`FUTURE LINK SYSTEMS LLC
`Patent Owner
`_________________
`
`Inter Partes Review Case No. IPR2022-00208
`U.S. Patent No. 6,317,804
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`DECLARATION OF ROBERT HORST
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`IPR2022-00208
`Apple EX1003 Page 1
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`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`APPLE INC.
`Petitioner
`
`v.
`
`FUTURE LINK SYSTEMS LLC
`Patent Owner
`_________________
`
`Inter Partes Review Case No. IPR2022-00208
`U.S. Patent No. 6,317,804
`
`DECLARATION OF ROBERT HORST
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`IPR2022-00208
`Apple EX1003 Page 1
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`IPR2022-00208
`U.S. Patent No. 6,317,804
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`I, Robert Horst, hereby declare the following:
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`I.
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`BACKGROUND AND QUALIFICATIONS
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`1. My name is Robert Horst and I am over 21 years of age and otherwise
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`competent to make this Declaration. I make this Declaration based on facts and
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`matters within my own knowledge and on information provided to me by others.
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`2.
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`I have been retained by counsel for Petitioner as a technical expert in the
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`above-captioned case. Specifically, I have been asked to render certain opinions in
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`regard to the IPR petition with respect to U.S. Patent No. 6,317,804 (the “’804
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`Patent”). I understand that the Challenged Claims are claims 1-5, 8-10, 14, 17, 21-
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`22, 40. My opinions are limited to those Challenged Claims.
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`3. My compensation in this matter is not based on the substance of my
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`opinions or the outcome of this matter. I have no financial interest in Petitioner. I am
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`being compensated at an hourly rate of $650 for my analysis and testimony in this
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`case.
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`4.
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`In writing this declaration, I have considered my own knowledge and
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`experience, including my work experience in the field of electrical engineering and
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`my experience working with others involved in this field, including in the design of
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`computer architectures and on-chip systems. In reaching my opinions in this matter,
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`I have also reviewed the following references and materials:
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`• Petition
`• The ’804 Patent (Ex. 1001)
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`• The ’804 Patent File History (Ex. 1002)
`• U.S. Patent No. 6,065,077 to Fu (“Fu”) (Ex. 1004)
`• U.S. Patent No. 5,889,947 to Stark (“Stark”) (Ex. 1005)
`• Patent Owner’s Proposed Constructions (Ex. 1006)
`• Opening CC Brief (Ex. 1007)
`• Intel Litigation Markman Order (Ex. 1011)
`• U.S. Patent No. 4,942,516 to Hyatt (“Hyatt”) (Ex. 1012)
`• U.S. Patent No. 4,212,057 to Devlin et al. (“Devlin”) (Ex. 1013)
`• U.S. Patent No. 6,401,191 to Jones (“Jones”) (Ex. 1014)
`• U.S. Patent No. 5,513,346 to Satagopan et al. (“Satagopan”) (Ex. 1015)
`• U.S. Patent No. 5,895,487 to Boyd et al. (“Boyd”) (Ex. 1016)
`• U.S. Patent No. 5,909,702 to Jalfon et al. (“Jalfon”) (Ex. 1017)
`• U.S. Patent No. 5,987,587 to Meltzer (“Meltzer”) (Ex. 1018)
`• U.S. Patent No. 6,266,797 to Godfrey et al. (“Godfrey”) (Ex. 1019)
`• European Patent No. 0,371,772 to Carvey et al. (“Carvey”) (Ex. 1020)
`• TNet: A Reliable System Area Network, Horst (“TNet”) (Ex. 2021)
`• Any additional background materials cited below
`A. Educational Background
`5.
`I earned my B.S. (1975) in electrical engineering from Bradley
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`University; and my M.S. (1978) in electrical engineering and Ph.D. (1991) in
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`computer science from the University of Illinois at Urbana-Champaign. During my
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`master’s program, I designed, constructed, and debugged a shared memory parallel
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`microprocessor system. During my doctoral program, I designed and simulated a
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`massively parallel, multi-threaded task flow computer.
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`B.
`6.
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`Professional Experience
`I am currently an Adjunct Research Professor in the Department of
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`Electrical and Computer Engineering at the University of Illinois at Urbana-
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`Champaign and am also an independent consultant at HT Consulting. I have more
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`than 30 years of expertise in designing and architecting computer systems.
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`7.
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`After receiving my bachelor’s degree and while pursuing my master’s
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`degree, I worked for Hewlett-Packard Co. While at Hewlett-Packard, I designed the
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`micro-sequencer and cache of the HP3000 Series 64 processor. From 1980 to 1999,
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`I worked at Tandem Computers, which was acquired by Compaq Computers in
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`1997. While at Tandem, I was a designer and architect of several generations of
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`fault-tolerant computer systems and was the principal architect of the NonStop
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`Cyclone superscalar processor. The system development work at Tandem also
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`included development of the ServerNet System Area Network and applications of
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`this network to fault tolerant systems and clusters of database servers.
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`8.
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`Since leaving Compaq in 1999, I have worked with several technology
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`companies, including 3Ware, Network Appliance, Tibion, and AlterG in the areas
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`of network-attached storage and biomedical devices, including the development of
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`microprocessor and FPGA electronics and interconnect options for network-
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`attached storage subsystems. I also represented Network Appliance in the PCI
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`Express Advanced Switching working group.
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`9.
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`At HP, Tandem, Compaq, 3Ware and Network Appliance my computer
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`design work was done using computer aided design (CAD) tools, with most designs
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`specified in a hardware description language. In fact, the designs used integrated
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`circuits and some involved the creation of new ASICs (application specific
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`integrated circuits) that were manufactured using masks based on the netlists
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`produced by the CAD software. From 2012 to 2015, I was Chief Technology Officer
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`of Robotics at AlterG, Inc., where I worked on the design of anti-gravity treadmills
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`and battery-powered orthotic devices to assist those with impaired mobility.
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`10.
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`In 1998, the University of Illinois department of Electrical and
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`Computer Engineering awarded me the Distinguished Alumni Award for
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`“Pioneering Contributions to Fault-tolerant Computer Architecture.” And in 2001, I
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`was elected an IEEE Fellow “for contributions to the architecture and design of fault
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`tolerant systems and networks.”
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`11.
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`I have authored over 30 publications, including, for example, "A
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`Linear-Array WSI Architecture for Improved Yield and Performance," in Proc. Int.
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`Conf. WSI, San Francisco, CA, pp. 85-91, Jan. 1990; "Task Flow Computer
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`Architecture," in Proc. Int. Conf. Parallel Processing, Vol. I, pp. 533-540, Aug.
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`1990; "Task Flow: A Novel Approach to Fine-grain Wafer-scale Parallel
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`Computing," Coordinated Science Lab. Report CRHC-91-15, University of Illinois,
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`April 1991; "Multiple Instruction Issue in the NonStop Cyclone Processor," in Proc.
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`17th Int. Symp. Computer Architecture, May 1990; "Task-Flow Architecture for
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`WSI Parallel Processing," Computer, vol. 25, no. 4, pp. 10-18, April 1992.
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`I have also worked with patent attorneys on numerous patent
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`12.
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`applications, and I am a named inventor on 86 issued U.S. patents. For example,
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`some of my patents include those related to memory system design including U.S.
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`Patent No. 5,146,589 (Refresh control for dynamic memory in multiple processor
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`system), multi-processor systems including U.S. Patent No. 6,496,940 (Multiple
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`processor system with standby sparing), U.S. Patent No. 5,751,932 (fail-fast, fail-
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`functional, fault-tolerant multiprocessor system) and U.S. Patent No. 5,390,355
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`(computer architecture capable of concurrent issuance and execution of general-
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`purpose multiple instructions), and storage including U.S. Patent No. 6,549,977 (the
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`use of deferred write completion interrupts to increase the performance of disk
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`operations).
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`13. My curriculum vitae, which includes a more detailed summary of my
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`background, experience, and publications, is attached as Appendix A.
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`II. LEGAL FRAMEWORK
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`A. Obviousness
`14.
`I am a technical expert and do not offer any legal opinions. However,
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`counsel has informed me as to certain legal principles regarding patentability and
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`related matters under United States patent law, which I have applied in performing
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`my analysis and arriving at my technical opinions in this matter.
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`I have been informed that the Patent Trial and Appeal Board (“PTAB”)
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`15.
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`now applies the claim construction standard applied by Article III courts (i.e., the
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`Phillips standard) regardless of whether a patent has expired. I have been informed
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`that under the Phillips standard, claim terms are to be given the meaning they would
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`have to a person having ordinary skill in the art at the time of the invention, taking
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`into consideration the patent, its file history, and, secondarily, any applicable
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`extrinsic evidence (e.g., dictionary definitions). I have reviewed the claim
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`construction section in the Petition. In my analyses below, I have applied the express
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`construction set forth in the Petition and a plain and ordinary meaning for all other
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`claim language pursuant to the Phillips standard.
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`16.
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`I have also been informed that a person cannot obtain a patent on an
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`invention if the differences between the invention and the prior art are such that the
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`subject matter as a whole would have been obvious at the time the invention was
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`made to a person having ordinary skill in the art. I have been informed that a
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`conclusion of obviousness may be founded upon more than a single item of prior art.
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`I have been further informed that obviousness is determined by evaluating the
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`following factors: (1) the scope and content of the prior art, (2) the differences
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`between the prior art and the claim at issue, (3) the level of ordinary skill in the
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`pertinent art, and (4) secondary considerations of non-obviousness. In addition, the
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`obviousness inquiry should not be done in hindsight. Instead, the obviousness
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`inquiry should be done through the eyes of a person having ordinary skill in the
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`relevant art at the time the patent was filed.
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`17.
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`In considering whether certain prior art renders a particular patent claim
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`obvious, counsel has informed me that I can consider the scope and content of the
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`prior art, including the fact that one of skill in the art would regularly look to the
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`disclosures in patents, trade publications, journal articles, industry standards,
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`product literature and documentation, texts describing competitive technologies,
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`requests for comment published by standard setting organizations, and materials
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`from industry conferences, as examples. I have been informed that for a prior art
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`reference to be proper for use in an obviousness analysis, the reference must be
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`“analogous art” to the claimed invention. I have been informed that a reference is
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`analogous art to the claimed invention if: (1) the reference is from the same field of
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`endeavor as the claimed invention (even if it addresses a different problem); or (2)
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`the reference is reasonably pertinent to the problem faced by the inventor (even if it
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`is not in the same field of endeavor as the claimed invention). In order for a reference
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`to be “reasonably pertinent” to the problem, it must logically have commended itself
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`to an inventor’s attention in considering his problem. In determining whether a
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`reference is reasonably pertinent, one should consider the problem faced by the
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`inventor, as reflected either explicitly or implicitly, in the specification. My opinions
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`in this IPR are based upon are based on references a person having ordinary skill in
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`the art would have consulted to address the type of problems described in the
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`Challenged Claims.
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`18.
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`I have been informed that, in order to establish that a claimed invention
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`was obvious based on a combination of prior art elements, a clear articulation of the
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`reason(s) why a claimed invention would have been obvious must be provided.
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`Specifically, I am informed that, under the U.S. Supreme Court’s KSR decision, a
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`combination of multiple items of prior art renders a patent claim obvious when there
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`was an apparent reason for one of ordinary skill in the art, at the time of the invention,
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`to combine the prior art, which can include, but is not limited to, any of the following
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`rationales: (A) combining prior art methods according to known methods to yield
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`predictable results; (B) substituting one known element for another to obtain
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`predictable results; (C) using a known technique to improve a similar device in the
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`same way; (D) applying a known technique to a known device ready for
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`improvement to yield predictable results; (E) trying a finite number of identified,
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`predictable potential solutions, with a reasonable expectation of success; (F)
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`identifying that known work in one field of endeavor may prompt variations of it for
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`use in either the same field or a different one based on design incentives or other
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`market forces if the variations are predictable to one of ordinary skill in the art; or
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`(G) identifying an explicit teaching, suggestion, or motivation in the prior art that
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`would have led one of ordinary skill to modify the prior art reference or to combine
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`the prior art references to arrive at the claimed invention.
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`19.
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`I am informed that the existence of an explicit teaching, suggestion, or
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`motivation to combine known elements of the prior art is a sufficient, but not a
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`necessary, condition to a finding of obviousness. This so-called “teaching
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`suggestion-motivation” test is not the exclusive test and is not to be applied rigidly
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`in an obviousness analysis. In determining whether the subject matter of a patent
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`claim is obvious, neither the particular motivation nor the avowed purpose of the
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`patentee controls. Instead, the important consideration is the objective reach of the
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`claim. In other words, if the claim extends to what is obvious, then the claim is
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`invalid. I am further informed that the obviousness analysis often necessitates
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`consideration of the interrelated teachings of multiple patents, the effects of demands
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`known to the technological community or present in the marketplace, and the
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`background knowledge possessed by a person having ordinary skill in the art. All of
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`these issues may be considered to determine whether there was an apparent reason
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`to combine the known elements in the fashion claimed by the patent.
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`20.
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`I also am informed that in conducting an obviousness analysis, a precise
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`teaching directed to the specific subject matter of the challenged claim need not be
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`sought out because it is appropriate to take account of the inferences and creative
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`steps that a person of ordinary skill in the art would employ. The prior art considered
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`can be directed to any need or problem known in the field of endeavor at the time of
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`invention and can provide a reason for combining the elements of the prior art in the
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`manner claimed. In other words, the prior art need not be directed towards solving
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`the same specific problem as the problem addressed by the patent. Further, the
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`individual prior art references themselves need not all be directed towards solving
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`the same problem. I am informed that, under the KSR obviousness standard, common
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`sense is important and should be considered. Common sense teaches that familiar
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`items may have obvious uses beyond their primary purposes.
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`21.
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`I also am informed that the fact that a particular combination of prior art
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`elements was “obvious to try” may indicate that the combination was obvious even
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`if no one attempted the combination. If the combination was obvious to try
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`(regardless of whether it was actually tried) or leads to anticipated success, then it is
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`likely the result of ordinary skill and common sense rather than innovation. I am
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`further informed that in many fields it may be that there is little discussion of obvious
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`techniques or combinations, and it often may be the case that market demand, rather
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`than scientific literature or knowledge, will drive the design of an invention. I am
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`informed that an invention that is a combination of prior art must do more than yield
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`predictable results to be non-obvious.
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`22.
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`I am informed that for a patent claim to be obvious, the claim must be
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`obvious to a person of ordinary skill in the art at the time of the invention. I am
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`informed that the factors to consider in determining the level of ordinary skill in the
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`art include (1) the educational level and experience of people working in the field at
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`the time the invention was made, (2) the types of problems faced in the art and the
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`solutions found to those problems, and (3) the sophistication of the technology in the
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`field.
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`23.
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`I am informed that it is improper to combine references where the
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`references teach away from their combination. I am informed that a reference may
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`be said to teach away when a person of ordinary skill in the relevant art, upon reading
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`the reference, would be discouraged from following the path set out in the reference,
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`or would be led in a direction divergent from the path that was taken by the patent
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`applicant. In general, a reference will teach away if it suggests that the line of
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`development flowing from the reference’s disclosure is unlikely to be productive of
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`the result sought by the patentee. I am informed that a reference teaches away, for
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`example, if (1) the combination would produce a seemingly inoperative device, or
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`(2) the references leave the impression that the product would not have the property
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`sought by the patentee. I also am informed, however, that a reference does not teach
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`away if it merely expresses a general preference for an alternative invention but does
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`not criticize, discredit, or otherwise discourage investigation into the invention
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`claimed.
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`I am informed that even if a prima facie case of obviousness is
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`24.
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`established, the final determination of obviousness must also consider “secondary
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`considerations” if presented. In most instances, the patentee raises these secondary
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`considerations of non-obviousness. In that context, the patentee argues an invention
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`would not have been obvious in view of these considerations, which include: (a)
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`commercial success of a product due to the merits of the claimed invention; (b) a
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`long-felt, but unsatisfied need for the invention; (c) failure of others to find the
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`solution provided by the claimed invention; (d) deliberate copying of the invention
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`by others; (e) unexpected results achieved by the invention; (f) praise of the
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`invention by others skilled in the art; (g) lack of independent simultaneous invention
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`within a comparatively short space of time; (h) teaching away from the invention in
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`the prior art.
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`25.
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`I am further informed that secondary considerations evidence is only
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`relevant if the offering party establishes a connection, or nexus, between the
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`evidence and the claimed invention. The nexus cannot be based on prior art features.
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`The establishment of a nexus is a question of fact. While I understand that the Patent
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`Owner here has not offered any secondary considerations at this time, I will
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`supplement my opinions in the event that the Patent Owner raises secondary
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`considerations during the course of this proceeding.
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`III. OPINION
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`A. Level of a Person of Ordinary Skill in the Art
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`26.
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`I was asked to provide my opinion as to the level of skill of a person
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`having ordinary skill in the art (“POSITA”) of the ’804 Patent at the time of the
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`claimed invention, which counsel has told me to assume is November 30, 1998. In
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`determining the characteristics of a hypothetical person of ordinary skill in the art of
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`the ’804 Patent, I considered several factors, including the type of problems
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`encountered in the art, the solutions to those problems, the rapidity with which
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`innovations are made in the field, the sophistication of the technology, and the
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`education level of active workers in the field. I also placed myself back in the time
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`frame of the claimed invention and considered the colleagues with whom I had
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`worked at that time.
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`27. A POSITA at the time of the claimed invention of the ’804 Patent would
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`have had at least a bachelor’s degree in electrical engineering or a similar field with
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`at least two years of experience in the field of computer architecture, in either a
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`research or work capacity. A person with more direct industry experience could
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`accommodate having less formal education, and more formal education in the field,
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`such as a master’s degree with relevant specialization can accommodate less direct
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`industry experience. Such a POSITA would have been capable of understanding the
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`’804 Patent and the prior art references discussed herein.
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`28. Based on my education, training, and professional experience in the field
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`of the claimed invention, I am familiar with the level and abilities of a person of
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`ordinary skill in the art at the time of the claimed invention. Additionally, I met at
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`least these minimum qualifications to be a person having ordinary skill in the art as
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`of the time of the claimed invention of the ’804 Patent.
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`B. Background of Technology
`29.
`I was asked to briefly summarize the background of the technology from
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`the standpoint of a POSITA prior to November 30, 1998.
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`Microcomputers (Single Integrated Circuit Chip)
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`30. For this proceeding, I have been instructed to apply the date of
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`November 30, 1998 as the priority date of the ’804 Patent. Before this date, it was
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`known to utilize a microcomputer architecture that “facilitates a fully integrated
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`circuit computer on a single integrated circuit chip.” Hyatt at Abstract. Hyatt teaches
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`said single chip microcomputer architecture includes “an integrated circuit ROM for
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`program storage” and “an integrated circuit RAM or scratch pad memory for
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`alterable operand storage[.]” Hyatt at Abstract. “This monolithic data processor can
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`be implemented on a single integrated circuit chip which can include a read only
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`memory, an alterable memory, and program execution circuitry on the same chip.”
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`Hyatt at 8:43-46. Hyatt also teaches using serial data transfer to advantageously
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`minimize the logic and interconnections required for the single chip microcomputer.
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`Hyatt at 12:26-28.
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`Multiple Processors/Modules in a Microcomputer (Single Integrated Circuit Chip)
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`31.
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`It was also known well before the priority date of the ’804 Patent to
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`implement a single integrated circuit chip with multiple processors. One example is
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`Devlin, which was filed in 1976 and issued in 1980. Devlin teaches a “multiprocessor
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`microcomputer system having two or more substantially independent processors”
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`and a “shared memory accessible by any of the processors without interfering with
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`the proper operation of the other processors.” Devlin at Abstract. Devlin teaches that
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`“with respect to a multiprocessor microcomputer having two processors, that those
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`skilled in the art will readily appreciate that two, three or more processors may
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`readily be employed with a single shared memory in accordance with the teachings
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`of this invention.” Devlin at 3:4-8. Devlin expressly teaches numerous advantages
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`of implementing a microcomputer with a plurality of processors, including (1)
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`dividing functions performed by a microcomputer to increase system capacity, (2)
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`achieve lower cost, (3) providing redundancy not found in single processor systems,
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`and (4) establishing communications between two or more processors to share data
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`and allow one processor to control another processor.
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`32. Devlin explains the benefits of microcomputers:
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`Microcomputers are becoming increasingly important in a wide ranging
`variety of applications. As economies involved in the production of
`microprocessors and microcomputers continue to reduce the cost
`thereof, they will be utilized in more and more applications. It may
`often times be desirable to utilize more than one processing unit in
`conjunction with a single memory or a portion thereof. This may be
`desirable
`in order
`to divide
`the functions performed by a
`microcomputer among two or more processors in order to increase the
`capacity of the microcomputer system. Another advantage of a
`multiprocessor system is that lower cost may be achieved by enabling
`the implementation of a complex system with two or more relatively
`low cost processors as opposed to a single more complicated and
`consequently higher cost processor. A further advantage which may be
`obtained is that a system may be designed such that, in the event of
`failure of a single processor a second processor will assume the
`functions of the failed processor and thus provide a degree of
`redundancy not found in single processor systems. A still fu[r]ther
`advantage attendant a multiprocessor microcomputer system is that
`communications may be established between two or more processors
`through a shared memory directly accessible to any processor. A system
`of this type has the capacity for sharing not only data but also
`programming information and has the further advantage of allowing
`one processor to control the programming of another by modifying the
`instructions stored in a single memory.
`Devlin at 1:10-39.
`
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`33. Another example of a microcomputer with multiple processors is taught
`
`by Jones. Jones teaches “a computer system comprising a microprocessor on a single
`
`integrated circuit chip connected to an external computer device.” Jones at Abstract.
`
`Jones teaches that the “single integrated circuit chip has a plurality of CPUs on the
`
`same chip each connected to said communication bus whereby each CPU on said
`
`chip may address said external port.” Jones at 2:5-8. In one embodiment, Jones
`
`teaches “a single integrated circuit chip 11 on which is provided two CPU circuits
`
`12 and 13 as well as a plurality of modules 14. The CPU’s 12 and 13 as well as each
`
`module 14 are interconnected by a bus network 15 having bi-directional connections
`
`to each module.” Jones at 3:30-35. Jones also teaches that each CPU has an
`
`instruction cache 42 and a data cache 43. Jones at 3:61-64 (“The CPU’s can be
`
`operated in conventional manner receiving instructions from the instruction caches
`
`42 on chip and effecting data read or write operations with the data cache 43 on
`
`chip.”).
`
`34. Further, an additional example of a single integrated circuit with
`
`multiple processors is taught by Satagopan. Satagopan teaches “the present
`
`invention concerns interrupt handling for integrated circuits containing a plurality of
`
`processors.” Satagopan at 1:9-12. Specifically, Satagopan teaches “a complex
`
`integrated circuit having a plurality of general purpose microprocessors which may
`
`
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`be incorporated into a general purpose computer.” Satagopan at 2:42-46. Satagopan
`
`also teaches memory on said integrated circuit. Satagopan at 4:13-24.
`
`35. Moreover, Boyd teaches multiple processors integrated on a single chip
`
`along with memory. Boyd teaches a single chip with multiple processors and L2
`
`DRAM cache (either private or shared) and that this design advantageously reduces
`
`latency.
`
`An integrated processor and level two (L2) dynamic random access
`memory (DRAM) are fabricated on a single chip. As an extension
`of
`this basic structure,
`the
`invention also contemplates
`multiprocessor "node" chips in which multiple processors are
`integrated on a single chip with L2 cache. By integrating the
`processor and L2 DRAM cache on a single chip, high on-chip
`bandwidth, reduced latency and higher performance are achieved.
`A multiprocessor system can be realized in which a plurality of
`processors with integrated L2 DRAM cache are connected in a loosely
`coupled multiprocessor system. Alternatively, the single chip
`technology can be used to implement a plurality of processors
`integrated on a single chip with an L2 DRAM cache which may be
`either private or shared. This approach overcomes a number of
`issues which limit the performance and cost of a memory
`hierarchy. When the L2 DRAM cache is placed on the same chip
`as the processor, the time needed for two chip-to-chip crossings is
`eliminated. Since these crossings require off-chip drivers and
`receivers and must be synchronized with the system clock, the time
`
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`involved is substantial. This means that with the integrated L2
`DRAM cache, latency is reduced.
`Boyd at Abstract
`(emphases added); see also Boyd at 1:7-13, 2:2-5
`
`(“[S]emiconductor technology has reached the point where multiple processors and
`
`multiple memory hierarchies can be integrated on one chip.”), 2:32-35 (“It is a
`
`further object of the invention to provide a single chip technology in which a
`
`plurality of processors are integrated on a single chip with an L2 DRAM cache.”).
`
`Boyd teaches that this design advantageously reduces stages of delay. Boyd at 2:62-
`
`65 (“Building the L2 cache with DRAM technology and moving it on to the same
`
`chip as the processor eliminates the chip-to-chip crossings. It also eliminates the
`
`stages of delay associated with the off-chip circuitry.”). Boyd also teaches that the
`
`integrated L2 cache advantageously is “lower power compared to other approaches.”
`
`Boyd at 5:11-23.
`
`36. A further example of a single chip integrated circuit with multiple
`
`processors and on-chip memory is taught by Jalfon. Jalfon teaches a microprocessor
`
`32, two digital signal processors (DSP) DSP1 and DSP2, and “an array of random
`
`access memories (RAM) or memory banks designated MB1-MB4.” Jalfon at 2:44-
`
`60. Jalfon also teaches arrays of RAM MB5-MB8 and that the multiprocessor
`
`system is not limited to two DSPs, four banks each of program and data memory,
`
`number or type of processors, or number of shared memory banks. Jalfon at 3:2-10.
`
`Jalfon also teaches that “[d]ue to limitations on the number of pins in a package and
`
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`the long access times to access data from external memory, it is preferable that
`
`multiple processors in a single-chip multiprocessor execute from internal memory.”
`
`Jalfon at 2:15-18.
`
`37. Yet another example of a prior art system that interconnected multiple
`
`modules on a single chip was taught by Godfrey. Godfrey teaches that advances in
`
`computer manufacturing
`
`techniques were causing computer systems and
`
`manufacturers to evolve toward integrating “a plurality of modules or functions on
`
`a single computer chip.”
`
`[C]omputer systems are evolving toward an integration of functions
`into a handful of computer chips. This coincides with the ability of chip
`makers to place an increasingly large number of transistors on a single
`chip. For example, currently chip manufacturers are able to place up to
`ten million transistors on a single integrated circuit or monolithic
`substrate. It is anticipated that within several years chip makers will be
`able to place one billion transistors on a single chip. Thus, computer
`systems are involving toward comprising a handful of computer
`chips, where each computer chip comprises a plurality of functions.
`The integration of a plurality of modules or functions on a single
`computer chip requires an improved data transfer chip architecture.
`Also, due to the shorter distances and tighter integration of components
`on a chip, new data transfer architectures are necessary to take
`advantage of this environment. Therefore,
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