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`CLAIMS ALLOWED
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`25
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`NOTICE OF ALLOWANCE MAILED
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`0 a) The term of this patent
`subsequent to _____ (date)
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`Date Paid
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`ISSUE BATCH NUMBER
`+-(!/;
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`this patent have been disclaimed.
`
`(Legal Instruments Examiner)
`
`(Date)
`
`WARNING:
`The information disclosed herein may be restricted. Unauthorized disclosure may be prohibited by the United States Code Title 35, Sections 122, 181 and 368.
`Possession outside the U.S. Patent & Trademark Office is restricted to authorized employees and contractors only.
`
`Form PT0·436A
`(Rev. 6/98)
`
`\
`
`(LABEL AREA)
`
`(FACE)
`
`IPR2022-00208
`Apple EX1002 Page 1
`
`

`

`TENT APPLICATION
`
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`CONTENTS
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`or
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`or
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`IPR2022-00208
`Apple EX1002 Page 2
`
`

`

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`IPR2022-00208
`Apple EX1002 Page 3
`
`

`

`ISSUE SLIP STAPLE AREA (for. addWonal cross references)
`
`POSI'riON
`
`INITIALS
`
`..-----·-·"-- -- ·-·- -....--------.,
`IDNO.
`DATE
`
`FEE DETERMINATION
`
`O.I.P.E. CLASSIFIER
`FORMALITY REVIEW
`
`INDEX OF CLAIMS
`,
`v ................................. Rejected
`N ...................... /( ...... Non-elected
`= ................................. Allowed
`I
`.................... .,.~~ .......... Interference
`(Through numeral) ... Canceled
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`If more than 150 claims or 1 0 actions
`staple additional sheet here
`
`(LEFT INSIDE)
`
`Date
`
`..
`
`--
`
`I
`
`--1--
`
`IPR2022-00208
`Apple EX1002 Page 4
`
`

`

`PATENT APPLICATION SERIAL NO . - - - - - - - -
`
`U.S. DEPA&~NT OF COMMERCE
`PATENT. ·At'ro TRADEMARK OFFICE
`FE'B'IlliCORD SHEET
`. . .~
`.
`
`01 Ftd01
`02 Ft:102
`03 FC:103
`
`, ~ Rilla. Rtft 12109/1998 PM.I.EN
`000. 7164'700
`IAia233000 · ··
`llallellluHetaOB1450 ···.
`.
`FC: 704
`$114.00 CR,. ·
`
`PT0-1556
`(5/87)
`
`'U.S. GPO: 1998-433-:214/80404
`
`IPR2022-00208
`Apple EX1002 Page 5
`
`

`

`SERIAL NUMBER
`
`FILING DATE
`
`CLASS
`
`yROUP ART UNIT
`
`A HORNEY DOCKET NO.
`
`09/201,450
`257
`11/30/98
`VLSI/07
`~------------~----~----~~~----~--------­
`,._
`,z PAUL S. LEVY, CHANDLER, AZ; JUDSON ALAN LEHMAN,
`(5
`:::;
`D..
`D..
`<(
`
`**CONTINUING DOMESTIC
`VERIFIED
`
`/
`
`,.,..I
`
`/
`
`**371 (NAT'L STAGE) DATA******* *************
`VERIFIED
`
`**FOREIGN APPLICATIONS************
`VERil~IED
`~-<?L-
`
`FOREIGN FILING LICENSE GRANTED12/18/98
`
`Foreign Priority claimed
`35 USC 119 (a-d) conditions met
`
`o OMet after Allowance
`
`SHEETS
`DRAWING
`9
`
`TOTAL
`CLAIMS
`40
`
`INDEPENDENT
`CLAIMS
`4
`
`COQpo~ p
`wooD HER N AND EVANs PHrup9 6U=CnU>Nl
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`CONCURRENT SERIAL INTERCONNECT
`~ AN INTEGRATED CIRCUIT DEVICE
`!::
`f-
`
`BLOCKS IN
`
`FILING FEE
`RECEIVED
`
`$1,198
`
`FEES: Authority has been giv n in Paper
`No. ___ to charge/credit DEPOSIT ACCOUNT
`NO.
`for the following:
`
`L
`
`0 All Fees
`0 1.16 Fees (Filing)
`0 1.17 Fees (Processing Ext. of time)
`0 1.18 Fees (Issue)
`0 Other ____ _
`0 Credit
`
`-~-·-----~-------'
`
`IPR2022-00208
`Apple EX1002 Page 6
`
`

`

`- - ' - ' ·
`::;:::;:n
`~ U1
`~-\0
`- - -U1
`(....>=c:
`---·(ll
`<==~==.
`....o;;;;;;;;;;;;;;;.
`co
`"C Applicant:
`~--!
`
`0 Title:
`
`IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`PaulS. Levy, Judson Alan Lehman
`
`CONCURRENT SERIAL INTERCONNECT FOR INTEGRATING FUNCTIONAL
`BLOCKS IN AN INTEGRA TED CIRCUIT DEVICE
`
`u =
`
`I"] ~
`
`0 ....
`;;;;;;;;;;;
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`0
`Atty. Docket: VLSI I 07 o~ ~
`Client Ref.: 3267 · :;~
`~
`
`'Express Mail' mailing label number: EESS1S44 60
`Date of Deposit: November 30. 1998
`
`UTILITY PATENT APPLICATION TRANSMITTAL
`
`BOX PATENT APPLICATION
`Assistant Commissioner for Patents
`Washington, D.C. 20231
`
`This is a request for filing, under 37 CFR § 1.53(b), a(n):
`
`181 Original (non-provisional) application.
`o Divisional of prior application Serial No. _, filed on_.
`o Continuation of prior application Serial No. _, filed on _.
`o Continuation-in-part of prior application Serial No. _, filed on_.
`
`PRELIMINARY AMENDMENT/CALCULATION OF FEES
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`o Please cancel claims_ without prejudice, and prior to calculating the fees. _total claim(s), of
`which_ is( are) independent, is(are) pending after the amendment.
`
`o Please enter the enclosed preliminary amendment identified below prior to calculating the fees. _
`total claim(s), of which_ is( are) independent, is(are) pending after the amendment.
`
`181 The Fees are Calculated as Follows:
`
`Number of Claims:
`
`In Excess of:
`
`Extra:
`
`At Rate:
`
`Amount:
`
`Fee:
`
`Total Claims
`
`Independent Claims
`
`40
`
`4
`
`20
`
`3
`
`20
`
`1
`
`MULTIPLE DEPENDENT CLAIM FEE
`
`BASIC FEE
`
`I TOTAL OF ABOVE CALCULATIONS
`~~ON BY SO% FOR FILING BY SMAll EN1TfY
`
`$22
`
`$82
`
`'
`
`$440.00
`
`$82.00
`
`$790.00
`
`$1,312.00
`
`VLSI I 07
`Client Ref.: 3267
`Express Mail No. EE551544760US
`Page 1 of2
`
`IPR2022-00208
`Apple EX1002 Page 7
`
`

`

`ENCLOSURES
`
`1:81 Utility Patent Application Transmittal Form (in duplicate) containing Certificate of Mailing By
`Express Mail Under 37 CFR 1.10.
`1:81 Return Postcard.
`
`APPLICATION PAPERS
`
`1:81 Utility Patent Application, with: cover sheet, _jL page(s) specification (including~ total
`claim(s), of which....!.. is(are) independent), and _1_ page(s) abstract.
`1:81 Drawings: _2_ sheet(s) of formal drawings l.!§_ total figure(s)).
`o Microfiche Computer Program (Appendix).
`o Nucleotide and/or Amino Acid Sequence, including (all are necessary): Computer Readable Copy,
`Paper Copy (identical to computer copy), and Statement verifying identity of copies.
`1:81 An Executed Declaration, Power of Attorney and Petition Form.
`o Copy of Executed Declaration, Power of Attorney and Petition Form from prior application
`identified above.
`o Certified Copy of priority document(s) identified as attached above.
`
`ADDITIONAL PAPERS
`
`1:81 Assignment to VLSI Technology, Inc. , Recordation Cover Sheet (Form PT0-1595)
`o Verified Statement to Establish Small Entity Status under 37 CFR 1.9 and 1.27.
`o Preliminary Amendment (to be entered prior to calculation of fees)
`o
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`Foreign Patent Reference(s) and_ Other Reference(s)
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`1:81 A Check of $1,312.00 for the filing fee.
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`in the amount of_.
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`DEPOSIT ACCOUNT AUTHORIZATION
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`1:81 The Commissioner is authorized to charge any fees under 37 CFR 1.16 and 1.17 which may be
`required during the entire pendency ofthe application, or credit any overpayment, to Deposit
`Account No. 23-3000 . A duplicate of this transmittal is attached.
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`o THE PAYMENT OF FEES IS BEING DEFERRED.
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`
`IPR2022-00208
`Apple EX1002 Page 8
`
`

`

`Express Mail No. EE551544760US
`
`VLSI DOCKET: 3267
`WHE DOCKET: VLSI-07
`
`APPLICATION
`
`FOR
`
`UNITED STATES LETTERS PATENT
`
`TITLE:
`
`CONCURRENTSERIALINTERCONNECTFOR
`INTEGRATING FUNCTIONAL BLOCKS IN AN
`INTEGRATED CIRCUIT DEVICE
`
`APPLICANT(S):
`
`PaulS. Levy, Judson Alan Lehman
`
`ASSIGNEE:
`
`VLSI Technology, Inc.
`
`Wood, Herron & Evans, L.L.P.
`2700 Carew Tower
`Cincinnati, Ohio 45202
`. 513-241-2324
`
`SPECIFICATION
`
`IPR2022-00208
`Apple EX1002 Page 9
`
`

`

`- 1 -
`
`A tty Docket No. VLSI/07
`
`CONCURRENTSERIALINTERCONNECTFORINTEGRATING
`FUNCTIONAL BLOCKS IN AN INTEGRATED CIRCUIT DEVICE
`
`5
`
`10
`
`Field of the Invention
`
`The invention is generally related to integrated circuit device design and
`
`architecture, and in particular, to an interface for interconnecting multiple functional
`
`blocks together in an integrated circuit device.
`
`Background of the Invention
`
`Computer technology has advanced a great deal over the last several decades.
`
`Whereas computers once filled entire rooms, and were constructed using individually
`
`packaged transistors and/or vacuum tubes to perform different logical functions,
`
`innovations in semiconductor manufacturing techniques have enabled multiple
`
`15
`
`transistors, or logic gates, to be integrated together on a single integrated circuit
`
`device, or "chip" to perform a greater number of logical functions. The size and
`
`number of logic gates that can be integrated together on a chip continues to improve,
`
`and whereas early chips had at most only a few hundred gates, more recent chips have
`
`been developed that incorporate more on the order of millions of gates. Furthermore,
`
`20
`
`advances in integration have permitted designs that were at one time implemented
`
`using multiple chips to be implemented in a single chip.
`
`As chip designs become more complex, however, the design and development
`
`process becomes more expensive and time consuming. To alleviate this difficulty,
`
`design tools have been developed that enable developers to build custom chips by
`
`25
`
`assembling together smaller, generic components that perform basic functions
`
`required for the design. By using generic components, design time and effort are
`
`reduced, since circuits do not need to be designed gate by gate. Moreover, the
`
`components usually can be tested and optimized prior to assembly in a particular
`
`Page I of43
`VLSI/07
`Patent Application
`
`---- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - _ _ 1
`
`IPR2022-00208
`Apple EX1002 Page 10
`
`

`

`- 2-
`
`design, so that the testing effort placed on the developer of an overall design is
`
`substantially reduced.
`
`The ability to integrate greater numbers of gates onto a chip has also permitted
`
`the complexity of the generic components used by design tools to increase. Whereas
`
`5
`
`early generic components replicated basic functions such as multiplexers, registers,
`
`counters, etc., more advanced components typically replicate higher level functions
`
`such as that of microprocessors, memory controllers, communications interface
`
`controllers, etc. These more advanced components are referred to herein as functional
`
`blocks, insofar as they are configured to perform one or more high level functions in a
`
`1 0
`
`design. Functional blocks typically are portable to the extent that they are reusable in
`
`different designs. Moreover, they are often autonomous, and thus capable of
`
`operating independently and concurrently with other components in a design.
`
`One difficulty associated with the use of components such as functional blocks
`
`arises from the need for the various components in a design to communicate with and
`
`15
`
`transfer information among one another. Each component typically has one or more
`
`interfaces defined therefor through which communication with other components, or
`
`with other devices external to a chip, is handled. These interfaces are typically
`
`interconnected with one another over an interconnect system such as a bus to support
`
`communication between the different components.
`
`20
`
`For example, one common manner of interconnecting multiple components is
`
`through the use of a multi-drop bus. With a multi-drop bus, each component is
`
`coupled to a common set of lines, so that each component is capable of receiving
`
`every communication passed over the bus. Information passed over a bus is usually
`
`associated with a particular address or other identifier so that, only the component that
`
`25
`
`is the target of the information actually receives and processes that information. The
`
`other components that are not targeted for the information ignore the information.
`
`Typically, a bus is parallel, incorporating multiple lines so that multiple bits of
`
`information can be transmitted simultaneously. Moreover, both control information,
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`used by one component to control the operation of another comporient, and data,
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`30
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`representing the information being manipulated by the components, are typically sent
`
`over the same lines in the bus. For example, one bus architecture used in integrating
`
`multiple functional blocks in a chip is the Peripheral Component Interconnect (PCI)
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`bus architecture, which is more conventionally used at the board level to interconnect
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`a microprocessor with different peripheral devices in a computer.
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`However, bus-type interconnections suffer from a number of drawbacks that
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`limit their usefulness in interconnecting multiple functional blocks in a chip. First,
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`5
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`parallel bus architectures require a relatively large number of lines, or wires, to run
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`between the various components connected to the bus. Routing wires between
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`components can take up valuable space in a design and reduce the number of
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`components that can fit into the design. Many parallel buses, for example, transmit
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`data in 32- or 64-bit words, requiring at a minimum 32 or 64lines to be routed to each
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`1 0
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`component, not counting any additional control signals that may be required.
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`Second, typically only one component can transmit information over a parallel
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`bus at a time. Therefore, other components that desire to transmit information
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`typically must wait until that component is done transmitting its information, or in the
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`alternative, each component must share the bus and transmit pieces of information one
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`15
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`after another, which slows down the transmission rate for all components. Also,
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`control information and data typically share the same lines in a parallel bus, and as a
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`result, control operations that might otherwise be capable of being performed within a
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`particular component without requiring access to the bus may have to wait until a data
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`transmission, started prior to the desired control operation, is complete.
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`20
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`Third, the overall speed of a parallel bus may be limited, and thus limit the
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`potential bandwidth of information that can be communicated between components.
`
`Bandwidth in a parallel bus is typically improved by increasing the width of the bus or
`
`increasing the clock speed of the bus. Increasing the width, however, adds additional
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`lines to the bus, thus adding to the routing density of the design. Increasing the clock
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`25
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`speed, on the other hand, may limit the number of components that can be attached to
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`the bus, since the number of components can affect the amount of load and routing
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`parasitics on the bus, each of which limits permissible clock speed.
`
`Therefore, a significant need exists in the art for an improved manner of
`interconnecting components such as functional blocks and the lik~ in an integrated
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`30
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`circuit design, and in particular, for a manner of interconnecting components that is
`
`more flexible, compact, fast, reusable, and expandible than conventional designs.
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`l/ (
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`Summary of the Invention
`
`The invention addresses these and other problems associated with the prior art
`
`by providing a circuit arrangement and method that interface multiple functional
`
`blocks within an integrated circuit device via a concurrent serial interconnect that is
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`5
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`capable of routing separate serial command, data and clock signals between functional
`
`blocks in the device. A concurrent serial interconnect consistent with the invention
`
`utilizes a plurality of serial ports that are selectively coupled to one another by an
`
`interface controller to define one or more logical communication channels between
`
`two or more of the serial ports. The logical communication channels in essence
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`10
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`function as point-to-point serial interconnections between functional blocks, so that
`
`direct communications between logically connected functional blocks can occur.
`
`Through the use of serial interconnects, the number of lines required to be
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`routed to and from individual functional blocks is reduced, thereby simplifying the
`
`integration of functional blocks into a design and reducing the routing congestion
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`15
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`associated with inter-block communication. In addition, by communicating via
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`separate serial command, data and clock signals, high speed data throughput can be
`
`supported. Furthermore, should more than one logical communication channel be
`
`supported by an interface controller consistent with the invention, multiple
`
`communication sessions can occur in parallel, thereby further increasing overall data
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`20
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`throughput.
`
`Another benefit of a concurrent serial interconnect consistent with the
`
`invention is that the design of integrated circuit devices and the like is substantially
`
`simplified. Fl_.lllctional blocks may be assembled together through the addition of a
`
`serial interconnect, with each functional block associated with one of a plurality of
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`25
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`serial ports in the serial interconnect by routing separate serial command, data and
`
`clock wires therebetween. Design and development is simplified as the addition of
`
`new functional blocks to a design typically affects only the design of the serial
`
`interconnect, and specifically, the interface controller used therein. Moreover,
`
`modular testing and verification is facilitated insofar as communi<(ations between
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`30
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`functional blocks primarily passes through the serial interconnect, and the need for
`
`testing and verifying individual interconnections between functional blocks is often
`
`reduced or eliminated.
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`These and other advantages and features, which characterize the invention, are
`
`set forth in the claims annexed hereto and forming a further part hereof. However, for
`
`a better understanding of the invention, and of the advantages and objectives attained
`
`through its use, reference should be made to the Drawings, and to the accompanying
`
`5
`
`descriptive matter, in which there is described exemplary embodiments of the
`
`invention.
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`Brief Description of the Drawings
`
`FIGURE 1 is a block diagram of a circuit arrangement for an integrated circuit
`
`device consistent with the invention.
`
`FIGURE 2 is a block diagram of the interface controller in the circuit
`
`5
`
`arrangement of Fig. 1.
`
`FIGURE 3 is a block diagram of a three channel implementation of the
`
`interface controller of Fig. 2.
`
`FIGURE 4 is a flowchart illustrating the sequence of operations performed
`
`during a system reset by the interface controller of Fig. 2.
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`10
`
`FIGURE 5 is a flowchart illustrating a sequence of operations performed when
`
`establishing a logical communication channel in the circuit arrangement of Fig. 1.
`
`FIGURE 6 is a flowchart illustrating a sequence of operations performed when
`
`releasing a logical communication channel in the circuit arrangement of Fig. 1.
`
`FIGURE 7 A, 7B and 7C are timing diagrams respectively illustrating
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`15
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`exemplary data stream transmissions between two ports during establishment of a
`
`logical channel, processing of a read request over the established channel, and release
`
`of the channel.
`
`FIGURE 8 is a flowchart illustrating a sequence of operations performed
`
`during an implicit preemption operation for the circuit arrangement of Fig. 1.
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`20
`
`FIGURE 9 is a flowchart illustrating a sequence of operations performed
`
`during an explicit preemption operation for the circuit arrangement of Fig. 1.
`
`FIGURE 10 is a block diagram of the primary logic components in a
`
`functional block circuit arrangement consistent with the invention.
`
`FIGURE 11 is a block diagram of a development environment data processing
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`25
`
`system consistent with the invention.
`
`FIGURE 12 is a block diagram of the system controller in the development
`
`environment data processing system of Fig. 11.
`
`FIGURE 13 is a block diagram of a set top box data prbcessing system
`
`consistent with the invention.
`
`30
`
`FIGURE 14 is a block diagr~ of the set top box controller in the set top box
`
`data processing system of Fig. 13.
`
`1
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`Detailed Description
`
`The illustrated embodiments of the invention generally rely on a concurrent
`
`serial interconnect to interface a plurality of functional blocks together in an
`
`integrated circuit device circuit arrangement. A concurrent serial interconnect
`
`5
`
`consistent with the invention includes a plurality of serial ports under the control of an
`
`interface controller, and coupled via a plurality of direct point-to-point serial
`
`interconnects to different functional blocks in the circuit arrangement. The interface
`
`controller selectively couples serial ports together to define one or more logical
`
`communications channels through which information is passed by the functional
`
`1 0
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`blocks associated with the coupled serial ports.
`
`A functional block may be considered to include any logic circuitry configured
`
`to perform one or more high level functions in an integrated circuit device design.
`
`Most functional blocks are "portable", whereby they are reusable in different designs.
`
`Moreover, many functional blocks are also "autonomous", and thus capable of
`
`15
`
`operating independently and concurrently with other components in a design.
`
`Examples of functional blocks include, but are not limited to processors, controllers,
`
`external interfaces, encoders, decoders, signal processors, and any other analog and/or
`
`digital circuitry performing a particular function or set of functions. Often, functional
`
`blocks are designed, developed and verified as independent entities, and may even be
`
`20
`
`obtained from third parties, rather than the designers of the overall integrated circuit
`
`device.
`
`The integration of multiple functional blocks via a concurrent serial
`
`interconnect consistent with the invention is typically implemented in a circuit
`
`arrangement for a processor or other programmable integrated circuit device, and it
`
`25
`
`should be appreciated that a wide variety of programmable devices may utilize the
`
`various features disclosed herein. Moreover, as is well known in the art, integrated
`
`circuit devices are typically designed and fabricated using one or more computer data
`
`files, referred to herein as hardware definition programs, that define the layout of the
`
`circuit arrangements on the devices. The programs are typically generated by a design
`
`30
`
`tool and are subsequently used during manufacturing to create the"layout masks that
`
`define the circuit arrangements applied to a semiconductor wafer. Typically, the
`
`programs are provided in a predefined format using a hardware definition language
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`(HDL) such as VHDL, verilog, EDIF, etc. While the invention has and hereinafter
`
`will be described in the context of circuit arrangements implemented in fully
`
`functioning integrated circuit devices and data processing systems utilizing such
`
`devices, those skilled in the art will appreciate that circuit arrangements consistent
`
`5
`
`with the invention are capable of being distributed as program products in a variety of
`
`forms, and that the invention applies equally regardless of the particular type of signal
`
`bearing media used to actually carry out the distribution. Examples of signal bearing
`
`media include but are not limited to recordable type media such as volatile and non(cid:173)
`
`volatile memory devices, floppy disks, hard disk drives, CD-ROM's, and DVD's,
`
`1 0
`
`among others and transmission type media such as digital and analog communications
`
`links.
`
`Turning now to the Drawings, wherein like numbers denote like parts
`
`throughout the several views, Fig. 1 illustrates a representative integrated circuit
`
`device circuit arrangement 1 0 consistent with the invention. A concurrent serial
`
`15
`
`interconnect 12, including an interface controller 14, is used to interface a host 20
`
`with a plurality of functional blocks 22, 24, 26 and 28 (also denoted as FB l .. n). Host
`
`20 may also be considered as a functional block that has, in addition to any other high
`
`level functionality defined therefor, further logic circuitry to operate as a master
`
`device for concurrent serial interconnect 12.
`
`20
`
`Each functional block 20, 22, 24, 26 and 28 includes a respective port
`
`interface 30, 32, 34, 26 and 38 that interfaces with a plurality of serial ports 40, 42,
`
`44, 46 and 48 (also denoted as Ports O .. n) over direct point-to-point serial
`
`interconnections 50, 52, 54, 56 and 58. Each serial port 40-48 is under the control of
`
`interface controller 14 to selectively define one or more logical communication
`
`25
`
`channels between two or more functional blocks 20-28. Moreover, with host 20
`
`functioning as the master for interconnect 12, port 40 defines a master port for the
`
`interconnect, through which initialization information is provided by the host.
`
`Each serial interconnection 50-58 includes separate serial command, data and
`
`clock lines. The serial command lines are used to transmit serial encoded command
`'
`& control information between functional blocks or between the interface controller
`
`30
`
`and a functional block. The serial data lines are used to transmit serial encoded data
`
`between functional blocks or between the interface controller and a functional block,
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`with the data lines further used to provide additional information for the various
`
`commands transmitted over the serial command lines, as will be outlined in greater
`
`detail below. The serial data is framed by the serial command information.
`
`The serial clock lines are used to transmit clock signals to synchronize the
`
`5
`
`command and data lines, thereby permitting the functional blocks to operate
`
`substantially asynchronously from one another and/or from the interface controller, if
`
`desired. In the alternative, the functional blocks may be synchronized by the same
`
`distributed clock signal. The command and data lines may be double edge or single
`
`edge clocked as desired.
`
`10
`
`Each such line may be implemented in a number of manners. For example,
`
`each line may be implemented using a bidirectional wire, or a pair of unidirectional
`
`wires may be provided to support concurrent communication in both directions
`
`between a serial port and its associated functional block. In addition, lines may be
`
`implemented with single-ended wires, or may be implemented by differential pairs of
`
`15
`
`wires to improve performance. In the implementation discussed hereinafter, for
`
`example, differential wire pairs are provided for each of command in, data in and
`
`clock in signals (from a functional block to a serial port), as well as for each of
`
`command out, data out, and clock out signals (from a serial port to a functional
`
`block), resulting in a total of only 12lines for each serial interconnection 50-58.
`
`20
`
`In addition, as shown by line 60, each functional block may or may not
`
`provide external input and/or output for the integrated circuit device, as dictated by
`
`the particular design of the functional block.
`
`As shown in Fig. 2, interface controller 14 includes a matrix controller 64
`
`interfaced with a connector matrix 66. The matrix controller is also interfaced with a
`
`25
`
`memory storage device 67 within which arbitration data, defining an arbitration
`
`scheme for the controller, is stored. A set of matrix control lines 68 are output by
`
`controller 64 to control the configuration of matrix 66 based upon the defined
`
`arbitration scheme for the controller. In addition, matrix 66 receives the
`
`command/data/clock signals from each of serial ports 40, 42,44,46 and 48,
`
`30
`
`represented by lines 70, 72, 74, 76 and 78, respectively. The serial lines for each
`
`serial port are also provided to matrix controller 64 to permit the controller to decode
`
`commands passed thereto over the respective serial lines from a particular port so that
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`the matrix controller can reconfigure the matrix as necessary to establish the desired
`
`logical communications channel(s) between selected ports.
`
`The configuration of both matrix controller 64 and connector matrix 66 can
`
`vary significantly based upon the desir~