(12) United States Patent
`Levy et al.
`
`USOO631 7804B1
`(10) Patent No.:
`US 6,317,804 B1
`(45) Date of Patent:
`Nov. 13, 2001
`
`(54) CONCURRENT SERIAL INTERCONNECT
`FOR INTEGRATING FUNCTIONAL BLOCKS
`IN AN INTEGRATED CIRCUIT DEVICE
`
`(*) Notice:
`
`5/1998 Adan et al. .......................... 395/500
`5,754,828
`11/1998 Lee et al. ............................. 710/131
`5,838,937
`2/1999 Malladi .
`... 364/490
`5,870,310
`3/2000 Lee ........................................... 710/8
`6,035,345
`6,035,414 * 3/2000 Okazawa et al. ........................ 714/7
`(75) Inventors: Paul S. Levy, Chandler; Judson Alan
`6,041,400
`3/2000 Oz.celik et al. ........................ 712/35
`Lehman. Scottsdale, both of AZ (US)
`6,094,436
`7/2000 Runaldue et al. ................... 370/420
`s
`s
`6,112,241 * 8/2000 Abdelnour et al. ..
`709/224
`O TO
`6,138,185 * 10/2000 Nelson et al. .......
`... 710/33
`(73) Assignee: Philips Semiconductors Inc., New
`6,145,024 * 11/2000 Maezawa et al. ..................... 710/14
`York, NY (US)
`FOREIGN PATENT DOCUMENTS
`Subject to any disclaimer, the term of this
`O3O8890A2
`3/1989 (EP).
`patent is extended or adjusted under 35
`O 653 896 A2
`5/1995 (EP).
`U.S.C. 154(b) by 0 days.
`* cited by examiner
`(21) Appl. No.: 09/201,450
`Primary Examiner-Sumati Lefkowitz
`1-1.
`y
`(22) Filed:
`Nov.30, 1998
`(74) Attorney, Agent, or Firm Wood, Herron & Evans,
`LLP.
`(51) Int. Cl." ............................. G06F 13/00; G06F 13/14
`(52) U.S. Cl. ............................................. 710/129; 710/126
`ABSTRACT
`(57)
`(58) Field of Search ..................................... 710/129-132,
`710/38; 709/252-253; 370/360-385, 498–545 A circuit arrangement and method interface multiple func
`tional blocks within an integrated circuit device via a
`concurrent Serial interconnect capable of routing Separate
`Serial command, data and clock signals between functional
`blocks in the device. The concurrent Serial interconnect
`ity - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 35 utilizes a plurality of Serial ports that are Selectively coupled
`
`(56)
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`s: 11/1991
`
`- - - - 3.02.
`SSC : g: SN, et al.
`... 710f132
`5,261,059
`11 /1993 Hedberg et al
`37s
`5311.459
`5/1994 DLunet al...
`5,428,750
`6/1995 Hsieh et al. ......................... 710/129
`5,430,442 * 7/1995 Kaiser et al. ......
`... 340/825.79
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`11/1995 Vanbuskirk et al.
`... 395/200.01
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`4/1996 Patel et al. .........
`... 395/800
`5,537.583 : 7/1996 Truong ................................. 713/500
`5,555,540
`9/1996 Radke ........................... 370/462
`5,555,543 * 9/1996 Grohoski et al. ..
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`2/1997 Levinson et al. .................... 370/360
`5,655,142
`8/1997 Gephardt et al. ..
`... 395/800.32
`5,680,402 * 10/1997 Olnowich et al. ................... 370/498
`
`to one another by an interface controller to define one or
`more logical communication channels between two or more
`of the serial ports. Each serial port is coupled via a point
`to-point interconnection with a port interface in a functional
`block. In addition, the concurrent Serial interconnect facili
`tates the design of an integrated circuit device by Supporting
`the addition of a Serial interconnect to an assemblage of
`functional blocks, with each functional block associated
`with one of a plurality of Serial ports in the Serial intercon
`nect
`
`40 Claims, 9 Drawing Sheets
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`U.S. Patent
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`Nov. 13, 2001
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`Sheet 1 of 9
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`US 6,317,804 B1
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`Nov. 13, 2001
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`U.S. Patent
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`Nov.13, 2001
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`US 6,317,804 B1
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`U.S. Patent
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`Nov. 13, 2001
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`Sheet 4 of 9
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`US 6,317,804 B1
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`U.S. Patent
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`Nov.13, 2001
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`US 6,317,804 B1
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`U.S. Patent
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`Nov.13, 2001
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`Sheet 6 of 9
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`US 6,317,804 B1
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`U.S. Patent
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`Nov.13, 2001
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`Sheet 7 of 9
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`US 6,317,804 B1
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`U.S. Patent
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`Nov.13, 2001
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`Sheet 8 of 9
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`US 6,317,804 B1
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`U.S. Patent
`U.S. Patent
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`Nov.13, 2001
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`Sheet 9 of 9
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`US 6,317,804 B1
`US 6,317,804 B1
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`US 6,317,804 B1
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`1
`CONCURRENT SERIAL INTERCONNECT
`FOR INTEGRATING FUNCTIONAL BLOCKS
`IN AN INTEGRATED CIRCUIT DEVICE
`
`2
`With a multi-drop bus, each component is coupled to a
`common Set of lines, So that each component is capable of
`receiving every communication passed over the bus. Infor
`mation passed over a bus is usually associated with a
`particular address or other identifier So that, only the com
`ponent that is the target of the information actually receives
`and processes that information. The other components that
`are not targeted for the information ignore the information.
`Typically, a bus is parallel, incorporating multiple lines So
`that multiple bits of information can be transmitted simul
`taneously. Moreover, both control information, used by one
`component to control the operation of another component,
`and data, representing the information being manipulated by
`the components, are typically Sent over the same lines in the
`buS. For example, one bus architecture used in integrating
`multiple functional blocks in a chip is the Peripheral Com
`ponent Interconnect (PCI) bus architecture, which is more
`conventionally used at the board level to interconnect a
`microprocessor with different peripheral devices in a com
`puter.
`However, bus-type interconnections Suffer from a number
`of drawbacks that limit their usefulness in interconnecting
`multiple functional blocks in a chip. First, parallel bus
`architectures require a relatively large number of lines, or
`wires, to run between the various components connected to
`the buS. Routing wires between components can take up
`valuable Space in a design and reduce the number of
`components that can fit into the design. Many parallel buses,
`for example, transmit data in 32- or 64-bit words, requiring
`at a minimum 32 or 64 lines to be routed to each component,
`not counting any additional control Signals that may be
`required.
`Second, typically only one component can transmit infor
`mation over a parallel bus at a time. Therefore, other
`components that desire to transmit information typically
`must wait until that component is done transmitting its
`information, or in the alternative, each component must
`share the bus and transmit pieces of information one after
`another, which Slows down the transmission rate for all
`components. Also, control information and data typically
`share the same lines in a parallel bus, and as a result, control
`operations that might otherwise be capable of being per
`formed within a particular component without requiring
`access to the buS may have to wait until a data transmission,
`Started prior to the desired control operation, is complete.
`Third, the overall speed of a parallel bus may be limited,
`and thus limit the potential bandwidth of information that
`can be communicated between components. Bandwidth in a
`parallel bus is typically improved by increasing the width of
`the bus or increasing the clock Speed of the bus. Increasing
`the width, however, adds additional lines to the bus, thus
`adding to the routing density of the design. Increasing the
`clock Speed, on the other hand, may limit the number of
`components that can be attached to the bus, Since the number
`of components can affect the amount of load and routing
`parasitics on the bus, each of which limits permissible clock
`Speed.
`Therefore, a significant need exists in the art for an
`improved manner of interconnecting components Such as
`functional blockS and the like in an integrated circuit design,
`and in particular, for a manner of interconnecting compo
`nents that is more flexible, compact, fast, reusable, and
`expandible than conventional designs.
`SUMMARY OF THE INVENTION
`The invention addresses these and other problems asso
`ciated with the prior art by providing a circuit arrangement
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`FIELD OF THE INVENTION
`The invention is generally related to integrated circuit
`device design and architecture, and in particular, to an
`interface for interconnecting multiple functional blockS
`together in an integrated circuit device.
`BACKGROUND OF THE INVENTION
`Computer technology has advanced a great deal over the
`last Several decades. Whereas computers once filled entire
`rooms, and were constructed using individually packaged
`transistors and/or vacuum tubes to perform different logical
`functions, innovations in Semiconductor manufacturing
`techniques have enabled multiple transistors, or logic gates,
`to be integrated together on a Single integrated circuit
`device, or “chip' to perform a greater number of logical
`functions. The size and number of logic gates that can be
`integrated together on a chip continues to improve, and
`whereas early chips had at most only a few hundred gates,
`more recent chips have been developed that incorporate
`more on the order of millions of gates. Furthermore,
`advances in integration have permitted designs that were at
`one time implemented using multiple chips to be imple
`mented in a single chip.
`AS chip designs become more complex, however, the
`design and development process becomes more expensive
`and time consuming. To alleviate this difficulty, design tools
`have been developed that enable developers to build custom
`chips by assembling together Smaller, generic components
`that perform basic functions required for the design. By
`using generic components, design time and effort are
`reduced, Since circuits do not need to be designed gate by
`gate. Moreover, the components usually can be tested and
`optimized prior to assembly in a particular design, So that the
`testing effort placed on the developer of an overall design is
`Substantially reduced.
`The ability to integrate greater numbers of gates onto a
`chip has also permitted the complexity of the generic
`components used by design tools to increase. Whereas early
`generic components replicated basic functions Such as
`multiplexers, registers, counters, etc., more advanced com
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`ponents typically replicate higher level functions Such as
`that of microprocessors, memory controllers, communica
`tions interface controllers, etc. These more advanced com
`ponents are referred to herein as functional blocks, insofar as
`they are configured to perform one or more high level
`functions in a design. Functional blockS typically are por
`table to the extent that they are reusable in different designs.
`Moreover, they are often autonomous, and thus capable of
`operating independently and concurrently with other com
`ponents in a design.
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`One difficulty associated with the use of components Such
`as functional blocks arises from the need for the various
`components in a design to communicate with and transfer
`information among one another. Each component typically
`has one or more interfaces defined therefor through which
`communication with other components, or with other
`devices external to a chip, is handled. These interfaces are
`typically interconnected with one another over an intercon
`nect System Such as a bus to Support communication
`between the different components.
`For example, one common manner of interconnecting
`multiple components is through the use of a multidrop bus.
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`and method that interface multiple functional blocks within
`an integrated circuit device via a concurrent Serial intercon
`nect that is capable of routing Separate Serial command, data
`and clock signals between functional blockS in the device. A
`concurrent Serial interconnect consistent with the invention
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`utilizes a plurality of Serial ports that are Selectively coupled
`to one another by an interface controller to define one or
`more logical communication channels between two or more
`of the Serial ports. The logical communication channels in
`essence function as point-to-point Serial interconnections
`between functional blocks, So that direct communications
`between logically connected functional blocks can occur.
`Through the use of Serial interconnects, the number of
`lines required to be routed to and from individual functional
`blockS is reduced, thereby simplifying the integration of
`functional blocks into a design and reducing the routing
`congestion associated with inter-block communication. In
`addition, by communicating via Separate Serial command,
`data and clock signals, high Speed data throughput can be
`Supported. Furthermore, should more than one logical com
`munication channel be Supported by an interface controller
`consistent with the invention, multiple communication SeS
`Sions can occur in parallel, thereby further increasing overall
`data throughput.
`Another benefit of a concurrent Serial interconnect con
`Sistent with the invention is that the design of integrated
`circuit devices and the like is Substantially simplified. Func
`tional blockS may be assembled together through the addi
`tion of a Serial interconnect, with each functional block
`asSociated with one of a plurality of Serial ports in the Serial
`interconnect by routing Separate Serial command, data and
`clock wires therebetween. Design and development is Sim
`plified as the addition of new functional blocks to a design
`typically affects only the design of the Serial interconnect,
`and Specifically, the interface controller used therein.
`Moreover, modular testing and Verification is facilitated
`insofar as communications between functional blocks pri
`marily passes through the Serial interconnect, and the need
`for testing and verifying individual interconnections
`between functional blocks is often reduced or eliminated.
`These and other advantages and features, which charac
`terize the invention, are Set forth in the claims annexed
`hereto and forming a further part hereof However, for a
`better understanding of the invention, and of the advantages
`and objectives attained through its use, reference should be
`made to the Drawings, and to the accompanying descriptive
`matter, in which there is described exemplary embodiments
`of the invention.
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`BRIEF DESCRIPTION OF THE DRAWINGS
`FIG. 1 is a block diagram of a circuit arrangement for an
`integrated circuit device consistent with the invention.
`FIG. 2 is a block diagram of the interface controller in the
`circuit arrangement of FIG. 1.
`FIG. 3 is a block diagram of a three channel implemen
`tation of the interface controller of FIG. 2.
`FIG. 4 is a flowchart illustrating the Sequence of opera
`tions performed during a System reset by the interface
`controller of FIG. 2.
`FIG. 5 is a flowchart illustrating a Sequence of operations
`performed when establishing a logical communication chan
`nel in the circuit arrangement of FIG. 1.
`FIG. 6 is a flowchart illustrating a Sequence of operations
`performed when releasing a logical communication channel
`in the circuit arrangement of FIG. 1.
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`FIGS. 7A, 7B and 7C are timing diagrams respectively
`illustrating exemplary data Stream transmissions between
`two ports during establishment of a logical channel, pro
`cessing of a read request over the established channel, and
`release of the channel.
`FIG. 8 is a flowchart illustrating a Sequence of operations
`performed during an implicit preemption operation for the
`circuit arrangement of FIG. 1.
`FIG. 9 is a flowchart illustrating a Sequence of operations
`performed during an explicit preemption operation for the
`circuit arrangement of FIG. 1.
`FIG. 10 is a block diagram of the primary logic compo
`nents in a functional block circuit arrangement consistent
`with the invention.
`FIG. 11 is a block diagram of a development environment
`data processing System consistent with the invention.
`FIG. 12 is a block diagram of the system controller in the
`development environment data processing System of FIG.
`11.
`FIG. 13 is a block diagram of a Set top box data processing
`System consistent with the invention.
`FIG. 14 is a block diagram of the set top box controller in
`the set top box data processing system of FIG. 13.
`DETAILED DESCRIPTION
`The illustrated embodiments of the invention generally
`rely on a concurrent Serial interconnect to interface a plu
`rality of functional blocks together in an integrated circuit
`device circuit arrangement. A concurrent Serial interconnect
`consistent with the invention includes a plurality of Serial
`ports under the control of an interface controller, and
`coupled via a plurality of direct point-to-point Serial inter
`connects to different functional blocks in the circuit arrange
`ment. The interface controller Selectively couples Serial
`ports together to define one or more logical communications
`channels through which information is passed by the func
`tional blocks associated with the coupled Serial ports.
`A functional block may be considered to include any logic
`circuitry configured to perform one or more high level
`functions in an integrated circuit device design. Most func
`tional blocks are “portable”, whereby they are reusable in
`different designs. Moreover, many functional blocks are also
`“autonomous', and thus capable of operating independently
`and concurrently with other components in a design.
`Examples of functional blocks include, but are not limited to
`processors, controllers, external interfaces, encoders,
`decoders, Signal processors, and any other analog and/or
`digital circuitry performing a particular function or Set of
`functions. Often, functional blocks are designed, developed
`and Verified as independent entities, and may even be
`obtained from third parties, rather than the designers of the
`overall integrated circuit device.
`The integration of multiple functional blockS via a con
`current Serial interconnect consistent with the invention is
`typically implemented in a circuit arrangement for a pro
`ceSSor or other programmable integrated circuit device, and
`it should be appreciated that a wide variety of programmable
`devices may utilize the various features disclosed herein.
`Moreover, as is well known in the art, integrated circuit
`devices are typically designed and fabricated using one or
`more computer data files, referred to herein as hardware
`definition programs, that define the layout of the circuit
`arrangements on the devices. The programs are typically
`generated by a design tool and are Subsequently used during
`manufacturing to create the layout masks that define the
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`S
`circuit arrangements applied to a Semiconductor wafer.
`Typically, the programs are provided in a predefined format
`using a hardware definition language (HDL) such as VHDL,
`verilog, EDIF, etc. While the invention has and hereinafter
`will be described in the context of circuit arrangements
`implemented in fully functioning integrated circuit devices
`and data processing Systems utilizing Such devices, those
`skilled in the art will appreciate that circuit arrangements
`consistent with the invention are capable of being distributed
`as program products in a variety of forms, and that the
`invention applies equally regardless of the particular type of
`Signal bearing media used to actually carry out the distri
`bution. Examples of Signal bearing media include but are not
`limited to recordable type media Such as volatile and non
`Volatile memory devices, floppy disks, hard disk drives,
`CD-ROMs, and DVD’s, among others and transmission
`type media Such as digital and analog communications linkS.
`Turning now to the Drawings, wherein like numbers
`denote like parts throughout the several views, FIG. 1
`illustrates a representative integrated circuit device circuit
`arrangement 10 consistent with the invention. A concurrent
`Serial interconnect 12, including an interface controller 14,
`is used to interface a host 20 with a plurality of functional
`blocks 22, 24, 26 and 28 (also denoted as FB 1... n). Host
`20 may also be considered as a functional block that has, in
`addition to any other high level functionality defined
`therefor, further logic circuitry to operate as a master device
`for concurrent Serial interconnect 12.
`Each functional block 20, 22, 24, 26 and 28 includes a
`respective port interface 30, 32, 34, 26 and 38 that interfaces
`with a plurality of serial ports 40, 42, 44, 46 and 48 (also
`denoted as Ports 0. . . n) over direct point-to-point serial
`interconnections 50, 52, 54, 56 and 58. Each serial port
`40-48 is under the control of interface controller 14 to
`Selectively define one or more logical communication chan
`nels between two or more functional blocks 20-28.
`Moreover, with host 20 functioning as the master for inter
`connect 12, port 40 defines a master port for the
`interconnect, through which initialization information is
`provided by the host.
`Each serial interconnection 50-58 includes separate serial
`command, data and clock lines. The Serial command lines
`are used to transmit Serial encoded command & control
`information between functional blocks or between the inter
`face controller and a functional block. The Serial data lines
`are used to transmit Serial encoded data between functional
`blocks or between the interface controller and a functional
`block, with the data lines further used to provide additional
`information for the various commands transmitted over the
`Serial command lines, as will be outlined in greater detail
`below. The serial data is framed by the serial command
`information.
`The Serial clock lines are used to transmit clock signals to
`Synchronize the command and data lines, thereby permitting
`the functional blocks to operate Substantially asynchro
`nously from one another and/or from the interface controller,
`if desired. In the alternative, the functional blocks may be
`Synchronized by the same distributed clock Signal. The
`command and data lines may be double edge or Single edge
`clocked as desired.
`Each Such line may be implemented in a number of
`manners. For example, each line may be implemented using
`a bidirectional wire, or a pair of unidirectional wires may be
`provided to Support concurrent communication in both
`directions between a Serial port and its associated functional
`block. In addition, lines may be implemented with Single
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`ended wires, or may be implemented by differential pairs of
`wires to improve performance. In the implementation dis
`cussed hereinafter, for example, differential wire pairs are
`provided for each of command in, data in and clock in
`Signals (from a functional block to a serial port), as well as
`for each of command out, data out, and clock out signals
`(from a serial port to a functional block), resulting in a total
`of only 12 lines for each serial interconnection 50-58.
`In addition, as shown by line 60, each functional block
`may or may not provide external input and/or output for the
`integrated circuit device, as dictated by the particular design
`of the functional block.
`As shown in FIG. 2, interface controller 14 includes a
`matrix controller 64 interfaced with a connector matrix 66.
`The matrix controller is also interfaced with a memory
`Storage device 67 within which arbitration data, defining an
`arbitration Scheme for the controller, is Stored. A set of
`matrix control lines 68 are output by controller 64 to control
`the configuration of matrix 66 based upon the defined
`arbitration scheme for the controller. In addition, matrix 66
`receives the command/data/clock Signals from each of Serial
`ports 40, 42, 44, 46 and 48, represented by lines 70, 72, 74,
`76 and 78, respectively. The serial lines for each serial port
`are also provided to matrix controller 64 to permit the
`controller to decode commands passed thereto over the
`respective Serial lines from a particular port So that the
`matrix controller can reconfigure the matrix as necessary to
`establish the desired logical communications channel(s)
`between Selected ports.
`The configuration of both matrix controller 64 and con
`nector matrix 66 can vary Significantly based upon the
`desired connectivity between the various functional blockS.
`Any number of known Switch matrix implementations may
`be used, including cross-bar Switches, tree Structures, etc.
`Furthermore, a connector matrix may be developed to Sup
`port any number of concurrent logical communications
`channels. Moreover, in Some implementations, it may be
`desirable to Split the input and output lines between ports to
`permit one port to receive information from one channel, yet
`transmit information on another channel.
`For example, FIG. 3 illustrates one suitable implementa
`tion of connector matrix 66 as a three channel cross-bar
`interconnect for in connecting five serial ports 40–48 (Ports
`0... 4). To control matrix 66, matrix controller 64 includes
`three logic blocks: a route command & control block 80; a
`route request block 82, and a channel matrix control block
`84.
`Connector matrix 66 has three channels 86, 88,90 defined
`therein for selectively coupling together ports 40–48. For
`illustrative purposes, each port 40-48 is represented at two
`positions in the figure, with the left representation repre
`Senting the port in an “initiator” or "Source” mode, and the
`right representation representing the port in a “receiver” or
`“target” mode.
`Each of the ports 40-48 is coupled to each of channels
`86-90 by an associated pair of routers. For channel 86,
`5-way routers 92, 94 couple ports 40–48 to the channel. For
`channels 88 and 90, similarly-configured routers 96, 98 and
`100, 102 are used. In the illustrated embodiment, each
`channel is bidirectional, and thus each router 92-102 func
`tions both as a multiplexer and a demultiplexer, multiplexing
`the information passed from the ports to a channel, and
`demultiplexing the information passed from a channel to the
`ports.
`It should be noted that in the illustrated implementation,
`each port is coupled to each channel, and each channel is
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`burst bandwidth of at least about 937.5 MB/sec, without
`overhead, would be possible with this configuration.
`In the illustrated implementation, Serial encoded request
`and response commands or packets are passed between
`functional blocks and/or between a functional block and the
`interface controller to implement a concurrent Serial inter