`
`Internat wf
`
`Preliminary Data Sheet No. PD60162I
`
`IR2106/IR21064
`
`
`HIGH AND LOW
`
`
`SIDE DRIVER
`
`Features
`@ Floating channel designed for bootstrap operation
`Fully operational to +600V
`Tolerant to negative transient voltage
`dV/dt immune
`® Gate drive supply range from 10 to 20V
`@ Undervoltage lockout for both channels
`@ 5V Schmitt triggered input logic
`® Matched propagation delay for both channels
`® Logic and powerground +/- 5V offset.
`@ Lower di/dt gate driver for better noise immunity
`@ Outputs in phase with inputs (IR2106/IR21064)
`@ Outputs out of phase with inputs (IR2107/IR21074)
`
`Product Summary
`
`
`VOFFSET
`
`600V max.
`
`iot/-
`
`VouT
`
`120 mA/ 250 mA
`
`10 - 20V
`
`ton/off (typ.)
`.
`50 ns
`Delay matching
`
`
`180 ns
`
`Description
`P
`
`.
`
`Packages
`
`
`
`The IR2106/1R21064/IR2107/IR21074 are high volt-
`age, high speed power MOSFET and IGBT drivers
`with independent high and low side referenced out-
`
`which operates up to 600 volts. 14 Lead PDIP
`
`
`put channels. Proprietary HVIC and latch immune a
`CMOStechnologies enable ruggedized monolithic
`nye
`construction. The logic input is compatible with stan-
`8 Lead SOIC
`dard CMOS or LSTTL output. The output drivers
`feature a high pulse current buffer stage designed
`for minimum driver cross-conduction. The floating
`channel can be used to drive an N-channel power
`MOSFET or IGBT in the high side configuration
`
`Typical Connection
`
`
`
`-—|
`
`
`
`HIN/AT
`UNCIN
`COM
`
`
`
`Vv
`LO J
`
`IR2VO6IR2107—
`
`up to600V
`
`
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`Page 1 of 10
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`Volkswagen Exhibit 1009
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`Page 1 of 10
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`Volkswagen Exhibit 1009
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`IR2106/IR21064/IR2107/IR21074
`
`International
`Tear Rectifier
`
`Absolute Maximum Ratings
`Absolute maximum ratings indicate sustained limits beyond which damageto the device may occur. All voltage param-
`eters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured
`under board mounted and still air conditions.
`
`
`
`
`
`ymbol Definition
`VB
`:
`“Highside floating| absolute voltage Oo
`
`Vs
`High side floating supply offset voltage
`
`Vio
`|_ High side floating ooutput voltage _
`-
`
`Voo__|Lowsideand logiced supply voltage
`
`
`Vv
`
`
`
`
`
`
`
` Logic ground (IR21064/IR21074 only)
`Ambient temperature
`
`VLo
`Low side output voltage
`
`VIN
`Logic input voltage (HIN & LIN - IR2106/R21064)
`
`(HIN & CIN -
`IR2107/1R21074)
`Vss|Logic ground (IR21084/IR21074 only)
`
`dVs/dt
`Allowable offset supply voltage transient
`:
`Vins
`
`Pp
`Package powerdissipation @ Ta < +25°C
`(8 lead PDIP)
`
`
`(8 lead SOIC)
`
`(14 lead PDIP)
`w
`“(14 leadSOIC)|
`
`Thermal resistance, junction to ambient a lead PDIP)
`Rthua
`(Blead SOIC)
`(i4lead PDIP)CS 75|Cw
`(4lead SOIC) | SS«O
`
`Ty
`Junction temperature
`7 —
`_
`— T 450
`:
`Ts
`Storage temperature
`-50
`150
`°C
`Th
`Lead temperature (soldering, 10 seconds)
`—
`300
`
`|
`
`Recommended Operating Conditions
`The Input/Outputlogic timing diagram is shown in figure 1. For proper operation the device should be used within the
`recommended conditions. The Vg and Vgsoffset rating are tested with all supplies biased at 15V differential.
`
`Definition
`High sidefloating supply absolute voltage
`High side floating supply offset voltage
`High side floating output voltage
`Low side and logic fixed supply voltage
`Low side output voltage
`
`Logic input voltage (HIN & LIN - IR2 1O6HR21064)
`(HIN & CIN - IR2107/1R21074)
`
`Note 1: Logic operational for Vs of -5 to +600V. Logic state held for Vs of -5V to -Vps.
`2
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`Page 2 of 10
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`International
`Te@R Rectifier
`
`IR2106/IR21064/IR2107/IR21074
`
`Dynamic Electrical Characteristics
`Veias (Vcc, Vas) = 15V, Vgg = COM, CL = 1000 pF Ta = 25°C.
`
`
`
`ton
`| Turn-on propagation delay OO
`
`
`toff
`Turn-off propagationdelay
`:
`,
`
`MT
`Delay matching, HS & LS turn-on/off _
`tr
`Jurn-onrise time —
`tf
`Turn-off fall time
`
`
`|
`
`Static Electrical Characteristics
`Veias (Vcc, VBs) = 15V, Vsg = COM and Ta = 25°C unless otherwise specified. The Vit, Vin and ln parameters are
`referenced to Vgs/COM and are applicable to the respective input leads: HIN and LIN (IR2406/IR21064) and HIN and LIN
`(IR21074R21074). The Vo, io and Ron parameters are referenced to COM and are applicable to the respective output
`leads: HO and LO.
`
`
`Symbol Min.|Typ.) Max. Units[Test ConditionsDefinition
`
`
`
`Vie
`Logic “1” input voltage (IR2106/IR21064)
`27
`_
`_
`Veo = 10V to 20V
`Logic “0”input voltage (IR2107/R21074)
`
`Vin
`|
`Logic “0”input voltage (IR2106/IR21064) i og |
`OY
`Veg = 10V to 20V
`
`|
`Logic “4”input voltage (IR2107/R21074)
`|
`VoH
`| High level outputvoltage, Vaiag -Vo a = | oe|14-
`[Ig=20mA|
`VoL
`Low level output voltage, Vo
`,
`: _ , 0.3
`0.6 |
`Iig=20mA
`
`
`ik
`| Offset supply leakage current
`:
`— _ 50 _ Ve =Vs = 600V-
`
`
`
`
`lass 20|60|150)| Quiescent Ves supply current Vin = OV or 5V
`Vin = OV or 5V
`locc
`| Quiescent Voc supply current
`50
`120
`240
`
`
`Vin = 5V (IR2106(4)
`line
`|
`Logic “1” input bias current
`_
`20
`40
`HA
`
`
`Vin = OV IR2107(4))
`L
`|
`|
`
`
`Vin = OV (IR2106(4))
`10 |
`_
`| _
`Logic “0”input bias current
`lIN-
`
`.
`Vin = 5V (IR2107(4)
`i
`3.8
`8.9
`8.0
`Vocuv+ | Vcc and Ves supply undervoltage positive going
`Vesuv+s
`threshold
`
`
`
`
`3.0
`8.2
`7.4
`|
`Vecuv- | Vcc and Ves supply undervoitage negative going
`Vesuv.
`|
`threshold
`
`oT) — |
`r 0.3
`VecuVH | Hysteresis a
`VBSUVH|
`ios | Outputhigh short circuit pulsed current.SS 120| 200) —||Vosoy,
`i
`PW < 10 us
`
`
`
`lo. 250|350)Output low shortcircuit pulsed current — mA Vo= 15V, |
`
`
`
`PW < 10 us
`
`
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` Symbol| Definition.
`
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`V
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`|
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`|
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`Page 3 of 10
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`IR2106/IR21064/IR2107/IR21074
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`international
`ToR Rectifier
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`Functional Block Diagram
`
`
`2106
`
`3
`
`
`
`PULSE
`
` FILTER
`LEVEL
`HEN qn
`ivssicom |
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`ad FP pe ever b
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`a
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`LAPS)ae
`be VS
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`|+
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`
`
`~—___¢.
`LEVEL
`HIN gn
`[|
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`2
`
`
`2<|
`
` vec
`
`LO
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`Page 4 of 10
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`
`
`ene———-@ VCC
`hI
`
`COM
`
`Fyssicom|
`LEN gp if
`|
`
`tA
`
`
`
`
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`Page 4 of 10
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`International
`TeaR Rectifier
`
`IR2106/IR21064/IR2107/IR21074
`
` | VSSiCoM|
`
`
`
`
`
`LO LEVEL
`
`SHIFT COM
`
`vec
`
`
`
`
`
`
`
`
`
`
`LEVEL
`SHIFT
`
`
`
`
`LEVEL
`SHIFT
`
`|}
`
`
`
`PULSE
`
`
`
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`
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`Page 5 of 10
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`Page 5 of 10
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`IR2106/IR21064/IR2107/IR21074
`
`
`
`International
`Tear Rectifier
`
`
`
`Lead Definitions
`“Logicinput ffor“highsicsidegate driveroutput (HO),iin‘phase.(IR2106/IR21064)
`Logic input for high side gate driver output (HO), out of phase (IR2107/R21074)
`
`Logic input for low side gate driver output (LO), in phase (IR2106/IR21064)
`Logic inputfor low side gate driver output (LO
`}, out of phase (IR2107/IR21074)
`
`Logic Ground (IR21064 and IR21074 only)
`
`/
`| High side floating supply
`
`High side gate drive output
`|
`| High side floating supply return
`Low side and logic fixed supply
`| Low side gate drive output
`| Low side return
`
`| |
`
`
`
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`
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`
`
`
`
` HIN
`iIR21064S
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`
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`
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`LIN
`
`
`
`
`
`COM
`LO]
`5
`
`COM
`LO}
`
`
`5
`
` 8 Lead PDIP
`8 Lead SOIC
`
`
`
` IR21066
`IR2106S
`
`
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`
`
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`LO
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`14 Lead SOIC
`14 Lead PDIP
`
`
`IR21064
`
`Page 6 of 10
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`Page 6 of 10
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`International
`TOR Rectifier
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`IR2106/IR21064/IR2107/IR21074
`
`
`
`
`fTaT
`— QT —
`
`
`1} Ve|8| VB|8Voc Lil Voe
`
`
`
`
`
`
`
`
`2 | AN HOT 7|2|HIN HO} 7
`
`
`
`[3| ON Vsft¢ Cs) ON Vs [6]
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`
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`41} LO .5|[4 SOMCOM LO 5
`
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`IR21074S
`
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`8 Lead PDIP
`
`
` IR2107
`
`IR21075 |
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`
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`8 Lead SOIC
`
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`
`
`
`
`
`Lo
`
`14 Lead PDIP
`
`IR21074
`
`14 Lead SOIC
`
`Page 7 of 10
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`Page 7 of 10
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`IR2106/IR21064/IR2107/IR21074
`
`Internationa}
`Tear Rectifier
`
`WN IN
`na
`orcnep 6
`O VEUEC ©
`
`
`
`
`
`01-3003 01
`
`0.204 008]
`
`- BX 1.78 {.0703
`
`
`
`ENSIONS ARE SHOWN IN. MILLIME
`
`© [0.25[010)@ icfa©[8©]
`NOTES:
`
`TRUSIONS
`Foc
`DIMENSIONING & TOLERANCING PER
`1.
`l
`006%
`
`CONTROLLING DIMENSION: MILLIMETER THofspan con~ .
`
`
`
`
`
`& Lead SOIC
`
`8
`
`01-0021 08
`
`Page 8 of 10
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`Page 8 of 10
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`International
`I@R Rectifier
`
`IR2106/IR21064/IR2107/IR21074
`
`
`
`
`
`01-3002 03
` 01-3063
`
`14 Lead SOIC (narrow body)
`
`
`
`
`<r—
`
`x?)&ewood
`
`oao.
`
`Aga
`= Atva)
`
`R SO
`
`L
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`Page 9 of 10
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`Page 9 of 10
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`IR2106/IR21064/IR2107/IR21074
`
`international
`Tear Rectifier
`
`— —
`ee
`
`HIN
`LIN
`
`HO
`
`LO
`
`
`
`Figure 3. Delay Matching Waveform Definitions
`
`
`
`Po
`Figure 2. Switching Time Waveform Definitions
`
`ton
`
`t, k— toff + tf —
`
`| QD le ry Q tl © a OC |
`TER Rectitier
`
`WORLD HEADQUARTERS: 233 KansasSt., El Segundo,California 90245 Tel: (310) 322 3331
`IR GREAT BRITAIN: Hurst Green, Oxted, Surrey RH8 9BB, UK Tel: ++ 44 1883 732020
`IR CANADA: 15 Lincoln Court, Brampton, Ontario L6T 322 Tel: (905) 453-2200
`IR GERMANY: Saalburgstrasse 157, 61350 Bad Homburg Tel: ++ 49 6172 96590
`IR FFALY: Via Liguria 49, 10071 Borgaro, Torino Tel: ++ 39 11 451 0414
`IR FAR EAST: K&H Bidg., 2F, 30-4 Nishi-lkebukuro 3-Chome, Toshima-Ku, Tokyo, Japan 171 Tek 81 3 3983 0086
`IR SOUTHEASTASIA: 1 Kim Seng Promenade, Great World City West Tower, 13-11, Singapore 237994 Tel: 65 838 4630
`IR TAIWAN: 16 FI. Suite D..207, Sec.2, Tun Haw South Road, Taipei, 10673, Taiwan Tel: 886-2-2377-9936
`http://wwwirf.com/
`Data and specifications subject to change without notice.
`3/1/99
`10
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