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`a2) United States Patent
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`(10) Patent No.:
`US 7,049,850 B2
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` Shimizu (45) Date of Patent: May23, 2006
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`US007049850B2
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`(54) SEMICONDUCTOR DEVICE WITH A
`VOLTAGE DETECTING DEVICE TO
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`PREVENT SHOOT-THROUGH
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`PHENOMENONIN FIRST AND SECOND
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`COMPLEMENTARY SWITCHING DEVICES
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`Inventor: Kazuhiro Shimizu, Tokyo (JP)
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`(73) Assignee: Mitsubishi Denki Kabushiki Kaisha,
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`Tokyo (JP)
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`Subject to any disclaimer, the term ofthis
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`patent is extended or adjusted under 35
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`U.S.C. 154(b) by 143 days.
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`(21) Appl. No.: 10/780,735
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`(75)
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`(*) Notice:
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`Filed:
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`Feb. 19, 2004
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`(22)
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`(65)
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`(30)
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`Prior Publication Data
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`US 2004/0212021 Al
`Oct. 28, 2004
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`Foreign Application Priority Data
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`ceeeesecteeeeeserseeee 2003-119641
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`(JP)
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`Apr. 24, 2003
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`Int. CL
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`HO3K 19/91
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`(51)
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`(2006.01)
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`(52) US. CL wee 326/100; 326/80; 326/81
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`(58) Field of Classification Search ................ 326/100,
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`326/80, 81, 68, 72
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`References Cited
`
`
`U.S. PATENT DOCUMENTS
`
`
`
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`4,292,642 A
`9/1981 Appels et al.
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`5,304,870 A *
`4/1994 Nagasawa oo... 326/68
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`
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`5,455,439 A
`10/1995 Terashimaet al.
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`
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`5,506,535 A *
`4/1996 Ratner cee 326/80
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`
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`5,907,182 A
`5/1999 Terashima
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`
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`
`
`
`
`
`6,373,285 B1*
`4/2002 Konishi
`............
`we 326/81
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`
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`
`
`6,774,674 B1*
`8/2004 Okamoto et al.
`....0...... 326/80
`FOREIGN PATENT DOCUMENTS
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`9-172358
`6/1997
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`(56)
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`JP
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`* cited by examiner
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`Primary Examiner—Don Le
`Assistant Examiner—Lam T. Mai
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`(74) Attorney, Agent, or Firm—Oblon, Spivak, McClelland,
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`Maier & Neustadt, P.C.
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`ABSTRACT
`(57)
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`An HNMOStransistor (4) has its drain electrode connected
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`to the gate electrode of an NMOStransistor (21), and a logic
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`circuit voltage (VCC) is applied to the drain electrode of the
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`NMOStransistor (21) through a resistor (32). A ground
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`potential is applied to the source electrode of the NMOS
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`transistor (21). A drain potential (V2) at the NMOStransis-
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`tor (21) is monitored by aninterface circuit (1), for indirectly
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`monitoring a potential (VS). Thus providedis a high voltage
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`integrated circuit for preventing damage to a semiconductor
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`device used for performing bridge rectification of a power
`line.
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`See application file for complete search history.
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`26 Claims, 29 Drawing Sheets
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`HD
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`E108
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`fo
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`we
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`30
`v1
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`ON
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`LOGIC
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`eitea |__«
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`SQ
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` ANT
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`INTERFACE
`CIRCUIT
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`1
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`PULSE
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`GENERATOR
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`sO
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`LIN
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`O
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`“42
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`VSS
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`O
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`GND
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`Page 1 of 44
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`Volkswagen Exhibit 1001
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`Page 1 of 44
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`Volkswagen Exhibit 1001
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`U.S. Patent
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`May 23, 2006
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`Sheet 1 of 29
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`"Old
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`Page 2 of 44
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`US 7,049,850 B2
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`JOVAYILNI
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`LINDY!
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`QN9
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`Page 2 of 44
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`U.S. Patent
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`May 23, 2006
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`Sheet 2 of 29
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`US 7,049,850 B2
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`HO
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`HO------
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`VS--
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`Lo--
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`GNOD------
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`LO
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`vs
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`HV ------
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`GND--——
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`te
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`VS=HV
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`sie
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`VS=GND >!
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`vo
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`VCC--
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`ON
`GND------ ae
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`OFF
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`Page 3 of 44
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`Page 3 of 44
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`U.S. Patent
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`May 23, 2006
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`Sheet 3 of 29
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`US 7,049,850 B2
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`FIG. 3
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`GROUND-FAULT OCCURS AT N1
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`HV ------meenaepeeclee cans *
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`:
`VS
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`GND- -
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`.
`VCC--
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`:
`V2
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`GND: ~~ — —mmeee -
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`GROUND-FAULT IS DETECTED
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`HIN
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`HIN ------
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`GND--
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`OFF SIGNAL IS OUTPUT
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`VCC------_—__s—)emle “~
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`S1
`:
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`GND- -
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`$2
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`VCC. -----
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`GND--
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`VCC ----------------------
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`$3
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`GND- -
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`VB ~~ ~~~pymmmnctc cree *
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`HO
`:
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`TI
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`T2
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`VS --
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`Page 4 of 44
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`Page 4 of 44
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`U.S. Patent
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`May 23, 2006
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`Sheet 4 of 29
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`US 7,049,850 B2
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`FIG.4
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`100
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`HD
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`Page 5 of 44
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`Page 5 of 44
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`US 7,049,850 B2
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`May 23, 2006
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`Sheet 5 of 29
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`VW
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`U.S. Patent
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`May 23, 2006
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`Sheet 6 of 29
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`US 7,049,850 B2
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`FIG. 6
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`FIG. fT
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`ONO
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`JOVIYSLNI
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`LINDY!
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`U.S. Patent
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`May 23, 2006
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`Sheet 7 of 29
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`US 7,049,850 B2
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`Page 8 of 44
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`U.S. Patent
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`May 23, 2006
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`Sheet 8 of 29
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`US 7,049,850 B2
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`FIG.9
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`Page 9 of 44
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`Page 9 of 44
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`U.S. Patent
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`May 23, 2006
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`Sheet 9 of 29
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`US 7,049,850 B2
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`JOVIYIINI OL
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`Page 10 of 44
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`U.S. Patent
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`May 23, 2006
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`Sheet 10 of 29
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`US 7,049,850 B2
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`FIG. 11
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`Page 11 of 44
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`U.S. Patent
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`May 23, 2006
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`Sheet 11 of 29
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`US 7,049,850 B2
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`4
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`P210
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`FIG.183
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`Page 12 of 44
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`Page 12 of 44
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`U.S. Patent
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`Page 13 of 44
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`Sheet 12 of 29
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`US 7,049,850 B2
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`May 23, 2006
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`U.S. Patent
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`May 23, 2006
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`Sheet 13 of 29
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`US 7,049,850 B2
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`FIG.15
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`May 23, 2006
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`Sheet 14 of 29
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`US 7,049,850 B2
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`FIG. 16
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`May 23, 2006
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`Sheet 15 of 29
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`US 7,049,850 B2
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`U.S. Patent
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`May 23, 2006
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`Sheet 16 of 29
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`US 7,049,850 B2
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`FIG.18
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`May 23, 2006
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`Sheet 17 of 29
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`US 7,049,850 B2
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`FIG.20
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`May 23, 2006
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`Sheet 18 of 29
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`US 7,049,850 B2
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`FIG. 21
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`Sheet 19 of 29
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`Sheet 20 of 29
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`US 7,049,850 B2
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`FIG.24
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`May 23, 2006
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`Sheet 21 of 29
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`JOVIYSLNI GN9
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`Sheet 22 of 29
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`US 7,049,850 B2
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`FIG. 26
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`CIRCUIT
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`May 23, 2006
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`Sheet 23 of 29
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`US 7,049,850 B2
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`JOVIY3INI
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`FIG.29
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`JOVIYALNI
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`Sheet 28 of 29
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`FIG. 32
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`US 7,049,850 B2
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`Page 30 of 44
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`Page 30 of 44
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`US 7,049,850 B2
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`1
`SEMICONDUCTOR DEVICE WITH A
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`VOLTAGE DETECTING DEVICE TO
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`PREVENT SHOOT-THROUGH
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`PHENOMENONIN FIRST AND SECOND
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`COMPLEMENTARY SWITCHING DEVICES
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`1. Field of the Invention
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`The present invention relates to a semiconductor device,
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`and moreparticularly, to a high voltage integrated circuit.
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`2. Description of the Background Art
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`A high voltage integrated circuit (HVIC) is a device
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`indispensable for achieving great functionality and cost
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`reduction in the field of mechatronics including motor
`control.
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`For instance, an HVIC is employedas a gate driver in a
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`powertransistor such as an IGBT (Integrated Gate Bipolar
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`Transistor) used for performing bridge rectification of a
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`powerline. In this HVIC, when a high side IGBT and a low
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`side IGBT are brought into an on state at the same time
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`(which is called a “shoot-through” phenomenon), short-
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`circuit occurs between arms (powerlines) to cause a large
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`current to flow into the IGBTs, which are therefore damaged.
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`To prevent this, the HVIC is controlled such that a high
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`side gate driver output and a low side gate driver output are
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`complementarily outputted. However, since the gate driver
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`outputs are not monitored in practice, the high side IGBTis
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`short-circuited in the case where a potential at a node
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`between the high side IGBT and low side IGBT (hereinafter
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`referred to as “potential VS”) is short-circuited to a ground
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`potential (GND)(.e., ground-fault occurs) due to failure in
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`loads or the like while the high side gate driver continues
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`outputting (1.e., while the high side IGBTis in an ONstate).
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`Therefore,
`the high side IGBT needs to be turned off
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`immediately, however, the HVIC is incapable of determin-
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`ing that the potential VS has become GND, and therefore
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`causes the high side gate driver to continue outputting.
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`To prevent this, simply saying, the potential VS may be
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`monitored. However, the potential VS usually reaches sev-
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`eral hundred volts. Thus, it is impossible to monitor the
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`potential VS within the HVIC.
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`For instance, Japanese Patent Application Laid-Open No.
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`9-172358 (1997) discloses detecting overcurrent in the case
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`where an emitter terminal of a high side IGBT is short-
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`circuited to GND,thereby controlling the high side IGBT on
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`the basis of a detection signal (see columns 6—7, FIGS. 1-3).
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`With this method, however, a certain period of time is
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`required until a control signal is applied to the high side
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`IGBT, during which short-circuit continues. Therefore, the
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`high side IGBT needs to have resistance to a short-circuit
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`state for a certain period of time, which is a contributing
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`factor responsible for increase in manufacturing costs.
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`part configured to control conduction/non-conduction of a
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`high side switching device which is one of the first and
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`second switching devices. The low side logic circuit
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`provided in a low potential part operating on the basis of the
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`low main power potential and configured to generate a
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`control signal on the basis of a signal applied from outside,
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`BACKGROUND OF THE INVENTION
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`the control signal havingafirst state indicating conduction
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`of the high side switching device and a secondstate indi-
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`cating non-conduction ofthe high side switching device, and
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`to generate first and second pulse signals on the basis of the
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`control signal in correspondence with the first and second
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`states, respectively. The first and second level shift parts are
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`configured to level-shift the first and second pulse signals to
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`the high potential part to obtainfirst and secondlevel-shifted
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`pulse signals, respectively. The voltage detecting device is
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`provided in the low potential part and configured to detect a
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`potential at an output line of at least one of the first and
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`second level shift parts and to supply a logic value based on
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`the potential for the low side logic circuit, thereby control-
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`ling an operation of the low side logic circuit.
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`The voltage detecting device provided in the low potential
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`part detects the potential at an output line of at least one of
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`the first and second level shift parts, that is, the high main
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`powerpotential. Therefore, in the case where ground-fault
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`occurs at the node between the first and second switching
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`devices, the second pulse signal is generated at that timing
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`to bring the high side switching device into a non-conduct-
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`ing state. Thus, phase fault protection for the high side
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`switching device can be realized at low costs.
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`A second aspect of the invention is directed to a semi-
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`conductor device including a high potential part, a reverse
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`level shift part and a voltage detecting device and performs
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`drive control of first and second switching devices con-
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`nected in series and interposed between a high main power
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`potential and a low main powerpotential. The high potential
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`part includes a control part configured to control conduction/
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`non-conduction of a high side switching device which is one
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`of the first and second switching devices. The reverse level
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`shift part is configured to level-shift a signal from the high
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`potential part to supply the level-shifted signal to a low side
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`logic circuit operating on the basis of the low main power
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`potential. The voltage detecting device is provided in the
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`high potential part and configured to detect a potential at an
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`output line of the reverse level shift part and to supply a logic
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`value based on the potential for the control part, thereby
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`causing the control part to control conduction/non-conduc-
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`tion of the high side switching device.
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`The voltage detecting device provided in the high poten-
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`tial part detects the potential at an output line of the reverse
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`level-shift part,
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`the high main power potential.
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`Therefore, in the case where ground-fault occurs at the node
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`between the first and second switching devices, the control
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`part controls the high side switching device for bringing it
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`into a non-conducting state at that timing, so that the high
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`side switching device is immediately brought into a non-
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`conducting state. Thus, phase fault protection for the high
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`side switching device can effectively be achieved.
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`A third aspect of the invention is directed to a semicon-
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`ductor device including a high potential part, a low side
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`logic circuit and a voltage detecting device and performs
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`drive control of first and second switching devices con-
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`nected in series and interposed between a high main power
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`potential and a low main powerpotential. The high potential
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`part includes a control part configured to control conduction/
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`non-conduction of a high side switching device which is one
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`of the first and second switching devices. The low side logic
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`circuit is provided in a low potential part operating on the
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`SUMMARY OF THE INVENTION
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`An object of the present invention is to provide a high
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`voltage integrated circuit for preventing damage to a semi-
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`conductor device used for performing bridge rectification of
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`a powerline.
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`A first aspect of the present invention is directed to a
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`semiconductor device including a high potential part, a low
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`side logic circuit, first and second level shift parts and a
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`voltage detecting device, and performs drive controloffirst
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`and second switching devices connected in series and inter-
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`posed between a high main powerpotential and a low main
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`power potential. The high potential part includes a control
`Page 31 of 44
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`Page 31 of 44
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`4
`BRIEF DESCRIPTION OF THE DRAWINGS
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`3
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`basis of the low main power potential and configured to
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`generate a control signal on the basis of a signal applied
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`FIG. 1 is an explanatory view illustrating the circuit
`from outside, the control signal havingafirst state indicating
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`configuration of an HVIC according to a first preferred
`conduction of the high side switching device and a second
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`embodimentof the present invention;
`state indicating non-conduction of the high side switching
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`FIGS. 2 and 3 are timing charts explaining the operation
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`device, and to generate first and second pulse signals on the
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`of the HVIC according to the first preferred embodiment;
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`basis of the control signal in correspondence with the first
`FIG.4 is a plan viewillustrating the structure of the HVIC
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`and secondstates, respectively. The voltage detecting device
`according to the first preferred embodiment;
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`is provided in the low potential part and is configured to
`FIG.5 is a sectional view illustrating the structure of the
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`detect a potential at an output line extending out of the high
`HVIC according to the first preferred embodiment;
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`potential part outputting the high main powerpotential and
`FIG.6 is a plan view illustrating the structure of a voltage
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`detector of the HVIC according to the first preferred
`to supply a logic value based on the potential for the low side
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`embodiment;
`logic circuit, thereby controlling an operation of the low side
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`FIG.7 is a sectional view illustrating the structure of the
`logic circuit.
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`voltage detector of the HVIC accordingto thefirst preferred
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`The voltage detecting device detects the potential at an
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`output line extending out of the high potential part and
`FIG. 8 is an explanatory view illustrating the circuit
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`outputting the high main powerpotential, that is, the high
`configuration of a second modification of the HVIC accord-
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`main potential. Therefore, in the case where ground-fault
`ing to the first preferred embodiment;
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`occurs at the node between the first and second switching
`FIG. 9 is a table explaining the operation of a majority
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`logic circuit;
`devices, the second pulse signal is generated at that timing
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`FIG. 10 is an explanatory view illustrating a third modi-
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`fication of the HVIC accordingtothefirst preferred embodi-
`ing state. Thus, phase fault protection for the high side
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`ment;
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`switching device can be achieved. Further, detection of the
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`FIG. 11 is a plan view illustrating the structure of a
`potential at the output line extending out of the high poten-
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`voltage detector of the third modification of the HVIC
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`tial part increases flexibility in arrangement of the voltage
`according to the first preferred embodiment;
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`detecting device.
`FIGS. 12 and 13 are sectional views illustrating the
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`A fourth aspect of the invention is directed to a semicon-
`structure of the voltage detector of the third modification of
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`ductor device including a high potential part and a voltage
`the HVICaccording to the first preferred embodiment;
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`detecting part and performsdrive control of first and second
`FIG. 14 is an explanatory view illustrating the circuit
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`switching devices connected in series and interposed
`configuration of a fourth modification of the HVIC accord-
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`ing to the first preferred embodiment;
`between a high main powerpotential and a low main power
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`FIG. 15 is a plan view illustrating the structure of a
`potential. The high potential part includes a control part
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`voltage detector of the fourth modification of the HVIC
`configured to control conduction/non-conduction of a high
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`according to the first preferred embodiment;
`side switching device which is one ofthe first and second
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`FIG.16 is a sectional view illustrating the structure of the
`switching devices. The voltage detecting device is provided
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`voltage detector of the fourth modification of the HVIC
`in the high potential part and inserted between the high main
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`according to the first preferred embodiment;
`power potential and a node between the first and second
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`FIG. 17 is a graph explaining the operation of the voltage
`switching devices. The voltage detecting device is config-
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`detector of the fourth modification of the HVIC according to
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`ured to detect a potential at the node between the first and
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`the first preferred embodiment;
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`second switching devices and to supply a logic value based
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`FIGS. 18 and 19 are sectional views illustrating the
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`on the potential for the control part, thereby causing the
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`structure of the voltage detector of the fourth modification of
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`control part to control conduction/non-conduction of the
`the HVICaccording to the first preferred embodiment;
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`high side switching device. The voltage detecting device
`FIG.20 is a plan view illustrating a voltage detector of a
`includesat least one MOStransistor whose conduction/non-
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`fifth modification of the HVIC according to the first pre-
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`conduction is controlled on the basis of a potential at an
`ferred embodiment;
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`outputline extending out of the low potential part outputting
`FIG.21is a sectional view illustrating the voltage detector
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`the low main power potential.
`of the fifth modification of the HVIC according to thefirst
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`preferred embodiment;
`The voltage detecting device detecting the potential at the
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`FIG. 22 is a graph explaining the operation of the voltage
`node between the first and second switching devices for
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`detector of the fifth modification of the HVIC according to
`controlling conduction/non-conduction of the high side
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`the first preferred embodiment;
`switching device is provided in the high potential part.
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`FIG. 23 is an explanatory view illustrating the circuit
`Therefore, in the case where ground-fault occurs at the node
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`configuration of the fifth modification of the HVIC accord-
`between the first and second switching devices, the control
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`ing to the first preferred embodiment;
`part is caused to control the high side switching device for
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`FIG. 24 is an explanatory view illustrating the configu-
`bringing it into a non-conducting state at that timing, so that
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`ration of a bias voltage output circuit;
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`the high side switching device is immediately brought into
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`FIG. 25 is an explanatory view illustrating the circuit
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`a non-conducting state. Thus, phase fault protection for the
`configuration of an HVIC according to a second preferred
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`high side switching device can effectively be achieved.
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`embodiment of the invention;
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`These and other objects, features, aspects and advantages
`FIG. 26 is a plan view illustrating the structure of the
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`of the present invention will become more apparent from the
`HVIC according to the second preferred embodiment;
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`following detailed description of the present invention when
`FIG.27 is a sectional view illustrating the structure of the
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`taken in conjunction with the accompanying drawings.
`HVIC according to the second preferred embodiment;
`Page 32 of 44
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`US 7,049,850 B2
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`5
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`FIG. 28 is an explanatory view illustrating the circuit
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`configuration of an HVIC according to a third preferred
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`embodiment of the invention;
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`FIG. 29 is a plan view illustrating the structure of the
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`HVIC according to the third preferred embodiment;
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`FIG.30 is a sectional view illustrating the structure of the
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`HVIC according to the third preferred embodiment;
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`FIG. 31 is an explanatory view illustrating the circuit
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`configuration of an HVIC according to a fourth preferred
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`embodiment of the invention;
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`FIG. 32 is a plan view illustrating the structure of the
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`HVIC according to the fourth preferred embodiment; and
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`FIG.33 is a sectional view illustrating the structure of the
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`HVICaccording to the fourth preferred embodiment.
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`reversely level-shifted signal sent from the high side and
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`outputting the signal to the outside. The pulse generator 3 is
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`also called a one-shot pulse generator. The interface circuit
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`1 and pulse generator 3 may also generally be called a low
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`side logic circuit.
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`The pulse generator 3 has its two outputs respectively
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`connected to the gate electrodes of high voltage N-channel
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`field effect transistors (hereinafter referred to as HNMOS
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`transistors) 4 and 5 which are level shift transistors. The ON
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`signal S2 is applied to the gate electrode of the HNMOS
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`transistor 4, and the OFF signal S3 is applied to the gate
`electrode of the HNMOStransistor 5.
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`The drain electrodes of the HNMOStransistors 4 and 5
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`are respectively connected to one terminals of resistors 29
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`and 30 as well as to inputs of a logicfilter 8. The logicfilter
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`8 has its outputs respectively connected to a set input and a
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`reset input of a reverse input SR flip flop circuit 9. Here, the
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`logicfilter 8 is a filter circuit for preventing malfunctions of
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`the reverse input SR flip flop circuit 9 and is formed by logic
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`gates.
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`The reverse input SR flip flop circuit 9 has its Q output
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`connected to the gate electrodes of the PMOStransistor 24
`and NMOStransistor 25.
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`The other terminals of the resistors 29 and 30 are con-
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`nected to the source electrode of the PMOStransistor 24,
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`i.e., one electrode of the capacitor 10 (a potential here will
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`be referred to as a high side floating power supply absolute
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`potential VB). The drain electrode of the PMOStransistor
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`24, 1.e., the other electrode of the capacitor 10 (a potential
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`here will be referred to as a high side floating power supply
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`offset potential VS) is connected to the node N1.
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`Adc powersupply 41 for supplying a logic circuit voltage
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`VCCfor the capacitor 10 is connected to the HVIC 100, and
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`hasits positive pole connected to the anode of a high voltage
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`diode 31 through a current-limiting resistor 43. The high
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`voltage diode 31 has its cathode connected to the one
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`electrode of the capacitor 10 (i.e., the source electrode side
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`of the PMOStransistor 24).
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`The high side power device driving circuit HD operates
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`using charges stored in the capacitor 10, i.e., the logic circuit
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`voltage VCC. When charges stored in the capacitor 10 are
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`reduced to such a degree that cannot maintain the logic
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`circuit voltage VCC, charges are supplied from the de power
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`supply 41 throughthe high voltage diode 31, so that the logic
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`circuit voltage VCC is restored. A dc power supply 42 for
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`supplying an operating supply voltage VDDforthe interface
`circuit 1 is also connected to the HVIC 100.
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`The low side power device driving circuit LD includes a
`PMOStransistor 27 and an NMOStransistor 28 connected
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`in series between the twoelectrodes of a capacitor 11 which
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`is a power supply for the driving circuit LD, and comple-
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`mentarily turns on/off the PMOStransistor 27 and NMOS
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`transistor 28 to switch on/off the powerdevice 13. A voltage
`at a node between the PMOStransistor 27 and NMOS
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`transistor 28 is called a low side output voltage or control
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`signal LO.
`The PMOStransist