Doc Code: PA..
`Document Description: Power of Attorney
`
`PTO/AIA/82A (07-13)
`Approved for use through 11/30/2014. 0MB 0651-0051
`U.S. Patent and Trademark Office; U.S. DEPARTMENT OF COMMERCE
`Under the Paperwork Reduction Act of 1995, no persons are required to respond to a collection of information unless it displays a valid 0MB control number.
`
`TRANSMITTAL FOR POWER OF ATTORNEY TO ONE OR MORE
`REGISTERED PRACTITIONERS
`
`,
`
`\..
`
`NOTE: This form is to be submitted with the Power of Attorney by Applicant form (PTO/AIA/82B) to identify the application to which the
`Power of Attorney is directed, in accordance with 37 CFR 1.5, unless the application number and filing date are identified in the Power of
`Attorney by Applicant form. If neither form PTO/AIA/82A nor form PTO/AIA82B identifies the application to which the Power of Attorney is
`directed, the Power of Attorney will not be recognized in the application.
`
`Application Number
`
`Filing Date
`
`First Named Inventor
`
`RAO, G.R. MOHAN
`
`Title
`
`LIFETIME MIXED LEVEL NON-VOLATILE MEMORY SYSTEM
`
`Art Unit
`
`Examiner Name
`
`Attorney Docket Number GRTD60-34138
`
`Signature
`
`Name
`
`SIGNATURE of Applicant or Patent Practitioner
`/Keith D. Harden, Reg.# 74472/ Date (Optional)
`Keith D. Harden
`
`Registration
`Number
`
`74472
`
`Title (if Applicant is a
`juristic entity)
`
`Applicant Name (if Applicant is a juristic entity)
`
`NOTE: This form must be signed in accordance with 37 CFR 1.33. See 37 CFR 1.4(d) for signature requirements and certifications. If
`more than one applicant, use multiple forms.
`
`~ *Total of 0~ E
`
`forms are submitted.
`
`This collection of information is required by 37 CFR 1.131, 1.32, and 1.33. The information is required to obtain or retain a benefit by
`the public which is to file (and by the USPTO to process) an application. Confidentiality is governed by 35 U.S.C. 122 and 37 CFR
`1.11 and 1.14. This collection is estimated to take 3 minutes to complete, including gathering, preparing, and submitting the completed
`application form to the USPTO. Time will vary depending upon the individual case. Any comments on the amount of time you require
`to complete this form and/or suggestions for reducing this burden, should be sent to the Chief Information Officer, U.S. Patent and
`Trademark Office, U.S. Department of Commerce, P.O. Box 1450, Alexandria, VA 22313-1450. DO NOT SEND FEES OR
`COMPLETED FORMS TO THIS ADDRESS. SEND TO: Commissioner for Patents, P.O. Box 1450, Alexandria, VA 22313-1450.
`
`ff you need assistance in completing the form, ca/11-800-PTO-9199 and select option 2.
`
`Micron Ex. 1008, p. 1
`Micron v. Vervain
`IPR2021-01550
`
`

`

`Doc Code: PA __
`
`fYro.:~\:~-:.._;s2a {(:'t-::3:
`Appt:Jw:::d for ::'$.ft ~h;:.R:t{h i il.3WJ(}14. GMS D6fr1.{K~~>i
`U.S. Pats::::it r:r:d Trf:lic"!m~k GffiGf>~ US, OE:P»,RTtviENT or COMMt:J~Cr:
`Un>'.!-:::t !'!"it· ~t-~:~,~c* R:::xk:c:.:on Ad cf ·; f~~S~ n:) ;;>srscnt c1tt;- ,'(:t1u:r.::.'C t(> i"G:~p◊:1<: t<~ t) ~·.n:lB~·.fa):~ cf ink~nna:i-:-;:·5 ~:1:IB-:::-:-::- k di~:,r~as·s a v~fo.i 0-fvH?, :_::-_.:-,tr:)! n:J·mt:)jf
`
`POWER OF ATTORNEY BY APPLICANT
`
`1 l
`
`>;<-;< __ ,, _ _ )
`
`l hereby revoke aH pri;;vkn.is ixwyens. Df attorney given in the appli~!ion identified in either the aitached transmittal letter or
`the boxes bebw,
`
`~ fH~tHby ;:tppolnt ~he r~~>:iten1 r::racttHoner(s) assocLated ~'!:th the fc,Hov•iir:-g Customer Numb~3r .as rny/.our :::1tomey{8) or agent(s\ and
`!he at!ac~f::d tr;:1nr,mittal !0t10r (fcrrn PTOIMNS2,<\) er identified abcv~: I ~ _
`iQ transact .an t. .. us~ne:8s in th~: UniB~d St.:1h~~ Pat~~nt and Tradernark (JftlGe connected ttiere\.v:{h for the ;2}pp~iCat:Gn n~:ferer~ced in
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`i fH~:--nby ;:1ppo}n1 Praclitionei{s} narned in the ~~tt;.SH::f:$~i t:st (!O}~n: ~)"[{.)/AL~f82(~; a-s rny.!c:..:r attorn~y{s) or agent(s): and to transact
`an business ~n the Un?t~d St$.tes P&ten~ an,d -T radern~:trk ()ff:ce c::)r-:-:eci:fKi !ht::nt:v .. 4th for t~H~ paten~ apptir.:at:0:1 reft?rf~ntk::d En the
`att~~:.~hed tr.ansrnitta~ ieth~r {forrn PTr)iA!J.\/P~2;\) ~~):· h~:.r:ttfi-ed ~~t:-:~>ve, (No!~~~ C<srnpfi~tB f(s:·rfl PTC(i.:S<fi~/82C~~)
`
`OR
`
`OR
`
`Piease recognize or chan~~ th~ wrrnspi:mdance address for the application Mentmed in the attached trnnsmltfol
`letter or tho !:.mxes abov{::; to:
`r✓-;-i
`LLJ
`:;, addre,,:, asS<odate<l wlth Cu,;;omer Nmnb~,c !.
`□
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`/ GREEN~_t!_~~-~~~~---~=-~_q__________________________________________________________________________
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`
`Person VVho ()th~:rtliS:H Sf!O'tiSf Saffici~nt Flrnpr}etary intere$t {s~g,, a :)et~tion under -:Jr GFR ·L46{b}(2J '..-Vas granted ~n tn~-~
`ii-_ _ _ _ _ s .... :..,~ .. -.._ii_ca~or:_,pr i1!_~~~,::re.r~ti~; hE~.;ng filt:d \f}<ith th~s d;,x:urr~ent} {pn.)v~de si9ner's t~t~e ~f appHcant !s _a judsUc anth;O
`S~GNATURE of .Ap~k,snt for Patent
`1-------------------------
`---~~;;;;~=-~Nl {WfE~f~:c;~;'.ii~,ls:~:~~~~i;; iS~;J~~Yized !t~ ac! Qn ms.h.~it 0i th~j:~;;7~~~,;::~~!;h;rn,'.;~;.'~~~~~,'.:i~;:::~~~:~J::~:~~~--
`! Philip \<v, John Jr,
`Narne
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`GFff:ENTHRE.AD. LLC
`---···--~--------
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`!l_Q.'1~;. Slgnst:;.:te - ·rnis torrri miJst be ~~nr.~d by ~h0 Hppt~cHnt ~n acc<Hti:ance with 37 GFR 1.~)3, S~e 37 C.FR -~ .4 fr'>r si~7~ature :'\~':q~1irt-:-mf:nt~~
`and certif~c~Hk~l1t~ if rncrt:: th~sn on~ app~k:~nt~ US~\ tf!UWf1le torn1~:.
`----,,,,....,.u...._ .... O .. Hnu_ ................ u .. .,,
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`ti-:r;; )').!.h-i:X.:fa~n ,:.f 5:-,:-f~:l-:":·:;:~tK,':r: ;;-;. :~~q:J:f(:X.: tty· 37 Cf-'f~ -1 :: ~-;' ·},.'32' ::,):}C : .(~~~ : ~-..-.;:. 5n1·or:Y!._..~i~;_:f; iS r~•·}q\.t:r-.:,;,.: r:) ohla:s: fjf 5'€l»ff:
`~1 U-:N:J:-:fl": by th<:;- Pi.>t~K; ;_.._;:1:c:, ~s tc rn~ : ::-i:n-c ty th~
`U!:.=P·r ~.) i:J µF .. x:::~s.~ :::~~ .;~f;::h::.x~~t:-:), (>:,;!":fi...¾~H .. ;~;ty ;s 9c~~:r~~~i hy (~~ U.t}. C. ·t~·2 :=5t~:1 ~~7 GFR ~ J 1 ~f:d i. ~·.-$. Thi:> •::f~fa3,;t!~)n ~:-; t·Stirr,-~h:d to ts~·?:· J m:rn..:il~s !:) G'\.":!n~ete.
`i:X::h.!di:1-9 g:3t:~~"::fi~1g, µr::-);x::nng, r.•f'ffj st:bm:W~] Ult--: Gf}rni-:~~!j"ji"J ;:,:;:)~k:a::tm :'(.'-Jm t(; };-~!·: u~.:p:·o, Th":~(:~ .. ,,iH \'(;N)' ,~-~~<~:.:o-id;n9 ~:p•:~--. th:::- :nc~v!d~:.:.~; (:::::"'!cS~. l\ny ~-::-0:~~m€":"1!.~;
`::">n H~t-:"! :3:mi_~)jf)~
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`f)f l~m€
`[_:~pan.m~;:t f:.~ :.::v:,:mr:.:·(~~. P.(:.\ St-:-x ·;4$~. A.k•:-:.::'l:X:ri'3, V~':-;. 22',:~·~'.$- ·! 4{~ . { ) , DC NOT ~:;ENG r:::f::S 0$~ C:GMPU:'.TtO FOR.MS TO T~lS ADG,qE$S, SENO TO: Coffu11iss-!on~f
`for P~<mt,s, !".O .. 6,}x ·\450, .Afex~md~i1>, VA in'!:l-14~li.
`;f _YY-~ll t}f)~H.i i.~ssi'Si::_~nct-• in ~'i.i.:rq:.:iet!ng 1b~ fo:.:n __ cf:H 1 ~fJOo,..prc~-s-; t gg ~_...H_··l f::e!::::-;t op&t"'.•n 2,
`
`Micron Ex. 1008, p. 2
`Micron v. Vervain
`IPR2021-01550
`
`

`

`r--:TCV}\:?,,:(H (t1t~---:~:;
`t\~·~::~•t'.·~,;,:s,:.i fo:· :.~s'3- thic,;~f.: '.)i/:)i!?O ~;!. G~-:~B. (:'35 ": ·00~32
`: .. L~t P2~!f:r:: f:nd Tff:-:.i~'!rm~xk Office-: U~S_. O~F-·~.J~T~·lENT Gr co;-...~:-...rt:RCf.::
`
`Title ot
`!swentfon
`
`UFETHV1E MlXED LEVEL NON-VOLATlLE hM:JvK)FY SYSTEi\/
`
`Th~~ :_)t:t.Jar~~t~on
`.is dir$cted to:.
`
`; hert~by ackn(>"W~eclge that any :i,,'ilii:fu} fa}s~~ stat~:.n1(~nt rr:~<ls in tt:As dectar.ation is ptJtfrsf:~3t;i~-:> under •i8 U.S.C. ·1COi
`by fin-2: or irr:p6sanrr:~nt cf n<~t rn~x-~1 than fi~lt: {S) y~~i~r~~ Qr both.
`
`~
`
`WARNING:
`
`IE t~~~:SK i;I~~ff ii~g~;~g~~f g~~~;i~~~!~~~\~~iI~~~~~Jf;iifu~;~
`
`~;::}tihor~ers/t~ppHcants should consider ~~fdact:nn ~HJct~ P(~rs:>r-:~3: infv:Tnaticn ftorn the docurner:!;') b~~fc:·:J sut:rn~tHng thern to th~,
`l1SPTO. P~tit.k)t'H~rh~.pp::cant }s advi:-;<:f(i th;:~~ th~~ r0cord of$ ::>attH)t app~lc:ation i~;- a·,-la;}ab~i~ to thH ~-st~t:frc 2:-fte: pubHc-2:tion r:-f !ht~
`a.pphcatk~n {u:-·:!~~$:E.~ ~~ nonupubHc~tinn rsque-st in \~(;ff:,pE:::nG{:~ :,.-vH:~·: 37 (:FR 1 ;:·::'.S(a) is n:~~de- k1 tt~e appHe~~~~on} o:· i~S~}~n::_~~ :::.~fa
`~x~ii~f11 Furth~~rrfl'Ore( th~ :"$Cord frorn ;:~n HbHndon:~-d ~1ppHt~3i:k::n rn~~Y ~dso be a .... .,.~i;at)l~ tn ;hJ3 publ·lc :f tht; appfo.).~gon l:s
`n~derer:cecl l.n a pwbHsh~ffJ <1ppH(;aHon or an ~ssu&d patent (see 37 CF-"f-~ ·t, ·1~i;. Cht~(:_k~:- ;~nd Dredh (.ard tHJt:·1{::·:-l2atis>n fGfrns
`p-·r()-2().3~ ~ubrniit.ed for pz~yn1ent pwrpvs~$ :?s~ nGi n~t~~lt:~~d in th~:! ar•pH(· .. :aHon file .2:nd tht:::tE~fon~~ :in;~ n<:! ptibHc\: O\.'aHa~)h~,
`
`LEGAL NAME OF lNVfNTOR
`
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`
`Micron Ex. 1008, p. 3
`Micron v. Vervain
`IPR2021-01550
`
`

`

`GRTD60-34138
`1/5
`
`10
`-
`
`Processor
`
`12
`
`20 I
`
`14
`
`I
`
`16
`
`V
`
`I/0
`
`DRAM
`
`Device
`Controller
`
`18
`
`I/0 V
`
`Disk(s) v24
`
`(e.g., rotating media-
`magnetic or optical)
`
`MLC
`flash
`
`/
`
`26
`
`SLC
`flash
`
`28
`
`FIG. 1
`
`Micron Ex. 1008, p. 4
`Micron v. Vervain
`IPR2021-01550
`
`

`

`GRTD60-34138
`2/5
`
`LOGICAL
`ADDRESS R.ANGE
`
`PHYSICAL
`ADDRESS RANGE
`
`RO
`
`MLC/Block 0
`
`MLC/Block 1
`Rl
`,------------- --------------!
`MLC/Block 2 i
`:
`R2
`'------------ .......... - ........ _ .............................. -
`R~-3
`MLC/Block 3
`
`Failed Data
`Integrity Test
`
`R4
`
`RN
`
`MLC/Block 4
`
`MLC/Block N
`
`FIG.2A
`
`LOGICAL
`ADDRESS RANGE
`
`PHYSICAL
`ADDRESS RANGE:
`
`RO
`
`MLC/Block 0
`
`Remapping to SLC
`flash module
`
`-
`
`Rl
`MLC/Block 1
`,------------· ........................... .,......,,.... ......................
`, ____________
`SLC/Block 0 i
`R2
`..., .... ...,....., ____ .... _ ............. ~
`I
`
`I
`l
`
`I
`
`R3
`
`R4
`
`RN
`
`MLC/Block 3
`
`MLC/Block 4
`
`MLC/Block N
`
`FIG.2B
`
`Micron Ex. 1008, p. 5
`Micron v. Vervain
`IPR2021-01550
`
`

`

`GRTD60-34138
`3/5
`
`Begin
`
`100
`
`Read data quantum
`from DRAM into memory
`of device controller
`
`/
`
`102
`
`Read logical address
`range and N AND flash
`physical address range
`to which data quanturn
`is to be written into
`memory of device
`controller
`!
`
`Combine contents of
`NAND flash me:mory
`with data quantum to be
`written
`
`Erase NAND flash
`physical address range
`
`Write combined data to
`appropriate NAND flash
`physical range
`
`Read NA.ND Flash
`physical address range
`into device controller
`m.ernory
`
`104
`
`/
`
`106
`
`108
`
`110
`
`112
`
`FIG. 3A
`
`Micron Ex. 1008, p. 6
`Micron v. Vervain
`IPR2021-01550
`
`

`

`GRTD60-34138
`4/5
`
`Compare Data Written to
`NAND FLASH Physical
`Address Range to Data Read
`from NAND FLASH Physical
`Address Range
`
`114
`
`116
`
`120
`
`Identify next
`quantum of
`available SLC
`NAND flash
`
`122
`
`Rernap NAND flash
`physical range to
`next available SLC
`NAND flash
`
`126
`
`Success
`
`118
`
`System
`Failure
`
`/
`
`124
`
`FICL 3B
`
`Micron Ex. 1008, p. 7
`Micron v. Vervain
`IPR2021-01550
`
`

`

`GRTD60-34138
`5/5
`
`I
`l
`I
`
`I
`I
`I
`I
`I
`I
`I
`
`MLC
`
`MLC
`
`MLC
`
`MLC
`
`MLC
`
`MLC
`
`MLC
`
`I
`l
`
`' '
`' '
`' I
`
`I
`I
`I
`......_
`
`1--
`
`50
`
`60a .,.,.,.,-
`
`--
`
`MLC
`
`MLC
`
`MLC
`
`MLC
`
`MLC
`
`MLC
`
`MLC
`
`i
`
`I
`
`I
`I
`I
`I
`I
`I
`I
`' '
`~ ' '
`' '
`MLC
`
`I
`I
`------------------------
`
`MLC
`
`I
`I
`-----------------------
`
`I
`
`1.,.,-,
`
`~ '
`
`SLC
`
`I
`I
`I
`I
`I
`I
`
`I
`I
`I
`I
`I
`I
`
`'
`SLC
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`I
`~
`
`62a ---
`56 --
`
`. .----
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`54 ,..,-
`
`-- 60b
`
`t---. 62b
`
`r--
`
`58
`
`~ 52
`
`I
`
`I
`
`I
`
`I
`
`SLC
`
`I
`
`'
`
`I
`I
`I
`I
`I
`I
`I
`
`'
`
`I
`I
`I
`I
`
`SLC
`
`I
`..___
`
`I--
`
`I
`
`-----
`
`.._
`
`~ FTL
`
`Interface
`
`FIG. 4
`
`Micron Ex. 1008, p. 8
`Micron v. Vervain
`IPR2021-01550
`
`

`

`Electronic Patent Application Fee Transmittal
`
`Application Number:
`
`Filing Date:
`
`Title of Invention:
`
`LIFETIME MIXED LEVEL NON-VOLATILE MEMORY SYSTEM
`
`First Named Inventor/Applicant Name:
`
`G.R. MOHAN RAO
`
`Filer:
`
`Keith D. Harden/Paula Sandu
`
`Attorney Docket Number:
`
`GRTD60-34138
`
`Filed as Small Entity
`
`Filing Fees for Utility under 35 USC 111 (a)
`
`Description
`
`Fee Code
`
`Quantity
`
`Amount
`
`Sub-Total in
`USO($)
`
`Basic Filing:
`
`UTILITY FILING FEE (ELECTRONIC FILING)
`
`UTILITY SEARCH FEE
`
`UTILITY EXAMINATION FEE
`
`4011
`
`2111
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`2311
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`1
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`1
`
`1
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`75
`
`330
`
`380
`
`75
`
`330
`
`380
`
`Pages:
`
`Claims:
`
`Miscellaneous-Filing:
`
`Petition:
`
`Patent-Appeals-and-Interference:
`
`Micron Ex. 1008, p. 9
`Micron v. Vervain
`IPR2021-01550
`
`

`

`Description
`
`Fee Code
`
`Quantity
`
`Amount
`
`Sub-Total in
`USO($)
`
`Post-Allowance-and-Post-Issuance:
`
`Extension-of-Time:
`
`Miscellaneous:
`
`Total in USO($)
`
`785
`
`Micron Ex. 1008, p. 10
`Micron v. Vervain
`IPR2021-01550
`
`

`

`Electronic Acknowledgement Receipt
`
`EFSID:
`
`Application Number:
`
`32875519
`
`16006299
`
`International Application Number:
`
`Confirmation Number:
`
`6732
`
`Title of Invention:
`
`LIFETIME MIXED LEVEL NON-VOLATILE MEMORY SYSTEM
`
`First Named Inventor/Applicant Name:
`
`G.R. MOHAN RAO
`
`Customer Number:
`
`25883
`
`Filer:
`
`Keith D. Harden
`
`Filer Authorized By:
`
`Attorney Docket Number:
`
`GRTD60-34138
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`12-JUN-2018
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`200780
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`Keith Harden
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`The Director of the USPTO is hereby authorized to charge indicated fees and credit any overpayment as follows:
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`37 CFR 1.16 (National application filing, search, and examination fees)
`
`37 CFR 1.17 (Patent application and reexamination processing fees)
`
`Micron Ex. 1008, p. 11
`Micron v. Vervain
`IPR2021-01550
`
`

`

`37 CFR 1.21 (Miscellaneous fees and charges)
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`135519
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`Micron Ex. 1008, p. 12
`Micron v. Vervain
`IPR2021-01550
`
`

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`Micron Ex. 1008, p. 13
`Micron v. Vervain
`IPR2021-01550
`
`

`

`GRTD60-34138
`
`PATENT
`
`IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`APPLICATION FOR UNITED STATES PATENT
`
`LIFETIME MIXED LEVEL NON-VOLATILE MEMORY SYSTEM
`
`Inventor:
`
`G. R. Mohan Rao-Allen, Texas
`
`Attorneys:
`Munck Wilson Mandala, LLP
`P.O. Drawer 800889
`Dallas, Texas 75380
`
`I
`
`Micron Ex. 1008, p. 14
`Micron v. Vervain
`IPR2021-01550
`
`

`

`GRTD60-34138
`
`PATENT
`
`IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`LIFETIME MIXED LEVEL NON-VOLATILE MEMORY SYSTEM
`
`CROSS-REFERENCE TO RELATED APPLICATIONS
`
`[0001]
`
`This application is a Continuation of U.S. Patent Application No. U.S. Application
`
`No. 14/950,553 filed on November 24, 2015, entitled LIFETIME MIXED LEVEL NON(cid:173)
`
`VOLATILE MEMORY SYSTEM (Atty. Dkt. No. GRTD-32800), which published on June 2,
`
`2016, as U.S. Application Publication No. 2016-0155496, now U.S. Patent No. 9,997,240 issued
`
`June 12, 2018, which is incorporated by reference in its entirety. U.S. Application No.
`
`14/950,553 is a Continuation of U.S. Patent Application No. 14/525,411, filed October 28, 2014,
`
`entitled LIFETIME MIXED LEVEL NON-VOLATILE MEMORY SYSTEM, which published
`
`on October 1, 2015, as U.S. Publication No. 2015-0278013, now U.S. Patent No. 9,196,385,
`
`issued on November 24, 2015, (Atty. Dkt. No. GRTD-32620). Application No. 14/525,411 is a
`
`Division of U.S. Patent Application No. 13/455,267, filed April 25, 2012, published on January
`
`24, 2013, as U.S. Publication No. 2013-0021846, now U.S. Patent No. 8,891,298, issued on
`
`November 18, 2014, entitled LIFETIME MIXED LEVEL NON-VOLATILE MEMORY
`
`SYSTEM (Atty. Dkt. No. GRTD-32619). Application No. 13/455,267 claims the benefit of U.S.
`
`Provisional Application No. 61/509,257, filed July 19, 2011, entitled LIFETIME MIXED
`
`LEVEL NAND FLASH SYSTEM (Atty. Dkt. No. GRTD-32624). Patent Nos. 9,997,240;
`
`9,196,385; and 8,891,298 and Patent Application Publication Nos. 2015-0278013 and 2013-
`
`0021846 are hereby incorporated by reference in their entirety.
`
`This application also
`
`incorporates by reference the complete disclosure of U.S. Patent Application No. 12/256,362,
`
`filed October 22, 2008, published on April 30, 2009, as U.S. Publication No. 2009-0109787, now
`
`U.S. Patent No. 7,855,916, issued on December 21, 2010, entitled NONVOLATILE MEMORY
`
`SYSTEMS WITH EMBEDDED FAST READ AND WRITE MEMORIES (Atty. Dkt. No.
`
`2
`
`Micron Ex. 1008, p. 15
`Micron v. Vervain
`IPR2021-01550
`
`

`

`GRTD60-34138
`
`PATENT
`
`GRTD-32614). This application also incorporates by reference the complete disclosure of U.S.
`
`Patent Application No. 12/915,177, filed October 29, 2010, published on March 10, 2011, as
`
`U.S. Publication No. 2011-0060870, now U.S. Patent No. 8,194,452, issued on June 5, 2012,
`
`entitled NONVOLATILE MEMORY SYSTEMS WITH EMBEDDED FAST READ AND
`
`WRITE MEMORIES (Atty. Dkt. No. 32615).
`
`TECHNICAL FIELD
`
`[0002]
`
`This application relates to a system and method for providing reliable storage through
`
`the use of non-volatile memories and, more particularly, to a system and method of increasing
`
`the reliability and lifetime of a NAND flash storage system, module, or chip through the use of a
`
`combination of single-level cell (SLC) and multi-level cell (MLC) NAND flash storage without
`
`substantially raising the cost of the NAND flash storage system. The memory in a total non(cid:173)
`
`volatile memory system may contain some SRAM (static random-access memory), DRAM
`
`(dynamic RAM), RRAM (resistive RAM), PCM (phase change memory), MAGRAM (magnetic
`
`random-access memory), NAND flash, and one or more HDDs (hard disk drives) when storage
`
`of the order of several terabytes is required. The SLC non-volatile memory can be flash, PCM,
`
`RRAM, MAGRAM or any other solid-state non-volatile memory as long as it has endurance that
`
`is superior to that of MLC flash, and it provides for data access speeds that are faster than that of
`
`MLC flash or rotating storage media (e.g., HDDs).
`
`3
`
`Micron Ex. 1008, p. 16
`Micron v. Vervain
`IPR2021-01550
`
`

`

`GRTD60-34138
`
`BACKGROUND
`
`PATENT
`
`[0003]
`
`Non-volatile memories provide long-term storage of data. More particularly, non-
`
`volatile memories can retain the stored data even when not powered. Magnetic (rotating) hard
`
`disk drives (HDD) dominate this storage medium due to lower cost compared to solid state disks
`
`(SSD). Optical (rotating) disks, tape drives and others have a smaller role in long-term storage
`
`systems. SSDs are preferred for their superior performance (fast access time), mechanical
`
`reliability and ruggedness, and portability. Flash memory, more specifically NAND flash, is the
`
`dominant SSD medium today.
`
`[0004]
`
`RRAM, PCM, MA GRAM and others, wi l llikely play a larger role in the future, each
`
`of them having their own advantages and disadvantages. They may ultimately replace flash
`
`memories, initially for use as a "write buffer" and later to replace "SLC flash" and "MLC flash."
`
`MLC NAND flash is a flash memory technology using multiple levels per cell to allow more bits
`
`to be stored using the same number of transistors. In SLC NAND flash technology, each cell can
`
`exist in one of two states, storing one bit of information per cell. Most MLC NAND flash
`
`memory has four possible states per cell, so it can store two bits of information per cell.
`
`[0005]
`
`These semiconductor technology driven "flash alternatives," i.e., RRAM, PCM,
`
`MAGRAM and others, have several advantages over any (SLC or MLC) flash because they: 1)
`
`allow data to be written over existing data (without prior erase of existing data), 2) allow for an
`
`erase of individual bytes or pages (instead of having to erase an entire block), and 3) possess
`
`superior endurance (1,000,000 write-erase cycles compared to typical 100,000 cycles for SLC
`
`flash and less than 10,000 cycles for MLC flash).
`
`[0006]
`
`HDDs have several platters. Each platter contains 250-5,000 tracks (concentric
`
`circles). Each track contains 64 to 256 sectors. Each sector contains 512 bytes of data and has a
`
`unique "physical (memory) address." A plurality of sectors is typically combined to form a
`
`"logical block" having a unique "logical address." This logical address is the address at which the
`
`logical block of physical sectors appears to reside from the perspective of an executing
`
`application program. The size of each logical block and its logical address (and/or address
`
`ranges/boundaries) is optimized for the particular operating system (OS) and software
`
`4
`
`Micron Ex. 1008, p. 17
`Micron v. Vervain
`IPR2021-01550
`
`

`

`GRTD60-34138
`
`PATENT
`
`applications executed by the host processor. A computer OS organizes data as "files." Each file
`
`may be located (stored) in either a single logical block or a plurality of logical blocks, and
`
`therefore, the location of files typically traverses the boundaries of individual (physical) sectors.
`
`Sometimes, a plurality of files has to be combined and/ or modified, which poses an enormous
`
`challenge for the memory controller device of a non-volatile memory system.
`
`[0007]
`
`SSDs are slowly encroaching on the HDD space and the vast majority ofNAND flash
`
`in enterprise servers utilizes a SLC architecture, which further comprises a NAND flash
`
`controller and a flash translation layer (FTL). NAND flash devices are generally fragmented into
`
`a number of identically sized blocks, each of which is further segmented into some number of
`
`pages. It should be noted that asymmetrical block sizes, as well as page sizes, are also acceptable
`
`within a device or a module containing devices. For example, a block may comprise 32 to 64
`
`pages, each of which incorporates 2 - 4 Kbit of memory. In addition, the process of writing data
`
`to a NAND flash memory device is complicated by the fact that, during normal operation of, for
`
`example, single-level storage (SLC), erased bits (usually all bits in a block with the value of' I')
`
`can only be changed to the opposite state (usually 'O') once before the entire block must be
`
`erased. Blocks can only be erased in their entirety, and, when erased, are usually written to 'I'
`
`bits. However, if an erased block is already there, and if the addresses (block, page, etc.) are
`
`allowed, data can be written immediately; if not, a block has to be erased before it can be written
`
`to.
`
`[0008]
`
`FTL is the driver that works in conjunction with an existing operating system ( or, in
`
`some embedded applications, as the operating system) to make linear flash memory appear to the
`
`system like a disk drive, i.e., it emulates a HDD. This is achieved by creating "virtual" small
`
`blocks of data, or sectors, out of flash's large erase blocks and managing data on the flash so that
`
`it appears to be "write in place" when in fact it is being stored in different locations in the flash.
`
`FTL further manages the flash so that there are clean/ erased places to store data.
`
`[0009]
`
`Given the limited number of writes that individual blocks within flash devices can
`
`tolerate, wear leveling algorithms are used within the flash devices (as firmware commonly
`
`known as FTL or managed by a controller) to attempt to ensure that "hot" blocks, i.e., blocks that
`
`are frequently written, are not rendered unusable much faster than other blocks. This task is
`
`5
`
`Micron Ex. 1008, p. 18
`Micron v. Vervain
`IPR2021-01550
`
`

`

`GRTD60-34138
`
`PATENT
`
`usually performed within a flash translation layer. In most cases, the controller maintains a
`
`lookup table to translate the memory array physical block address (PBA) to the logical block
`
`address (LBA) used by the host system. The controller's wear-leveling algorithm determines
`
`which physical block to use each time data is programmed, eliminating the relevance of the
`
`physical location of data and enabling data to be stored anywhere within the memory array and
`
`thus prolonging the service life of the flash memory. Depending on the wear-leveling method
`
`used, the controller typically either writes to the available erased block with the lowest erase
`
`count ( dynamic wear leveling); or it selects an available target block with the lowest overall
`
`erase count, erases the block if necessary, writes new data to the block, and ensures that blocks
`
`of static data are moved when their block erase count is below a certain threshold (static wear
`
`leveling).
`
`[0010] MLC NAND flash SSDs are slowly replacing and/ or coexisting with SLC NAND
`
`flash in newer SSD systems. MLC allows a single cell to store multiple bits, and accordingly, to
`
`assume more than two values; i.e., '0' or' l '. Most MLC NAND flash architectures allow up to
`
`four (4) values per cell; i.e., '00', '01', '10', or '11'. Generally, MLC NAND flash enjoys greater
`
`density than SLC NAND flash, at the cost of a decrease in access speed and lifetime (endurance).
`
`It should be noted, however, that even SLC NAND flash has a considerably lower lifetime
`
`(endurance) than rotating magnetic media ( e.g., HDDs ), being able to withstand only between
`
`50,000 and 100,000 writes, and MLC NAND flash has a much lower lifetime (endurance) than
`
`SLC NAND flash, being able to withstand only between 3,000 and 10,000 writes. As is well
`
`known in the art, any "write" or "program" to a block in NAND flash (floating gate) requires an
`
`"erase" ( of a block) before "write."
`
`[0011]
`
`Despite its limitations, there are a number of applications that lend themselves to the
`
`use of MLC flash. Generally, MLC flash is used in applications where data is read many times
`
`(but written few times) and physical size is an issue. For example, flash memory cards for use in
`
`digital cameras would be a good application of MLC flash, as MLC can provide higher density
`
`memory at lower cost than SLC memory.
`
`[0012] When a non-volatile storage system combines HDD, SLC and MLC (setting aside
`
`volatile memory for buffering, caching etc) in a single (hybrid) system, new improvements and
`
`6
`
`Micron Ex. 1008, p. 19
`Micron v. Vervain
`IPR2021-01550
`
`

`

`GRTD60-34138
`
`PATENT
`
`solutions are required to manage the methods of writing data optimally for improved life time
`
`(endurance) of flash memory. Accordingly, various embodiments of a NAND flash storage
`
`system that provides long lifetime (endurance) storage at low cost are described herein.
`
`[0013]
`
`The following description is presented to enable one of ordinary skill in the art to
`
`make and use the disclosure and is provided in the context of a patent application and its
`
`requirements. Various modifications to the preferred embodiment and the generic principles and
`
`features described herein will be readily apparent to those skilled in the art. Thus, the present
`
`disclosure is not intended to be limited to the embodiments shown, but is to be accorded the
`
`widest scope consistent with the principles and features described herein.
`
`7
`
`Micron Ex. 100