Reply Declaration of Dr. David Liu
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`
`
`
`
`
`MICRON TECHNOLOGY, INC.,
`Petitioner
`
`v.
`
`VERVAIN, LLC,
`Patent Owner
`
`
`
`
`Case No.: IPR2021-01550
`U.S. Patent No. 10,950,300
`Original Issue Date: March 16, 2021
`
`Title: LIFETIME MIXED LEVEL NON-VOLATILE MEMORY SYSTEM
`
`
`REPLY DECLARATION OF DR. DAVID LIU
`
`
`
`
`
`
`
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`Micron Ex. 1057, p. 1
`Micron v. Vervain
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`Reply Declaration of Dr. David Liu
`
`
`
`
`I.
`II.
`
`2.
`
`b.
`
`c.
`
`Page
`TABLE OF CONTENTS
`INTRODUCTION .......................................................................................... 4 
`EDUCATION BACKGROUND, PROFESSIONAL EXPERIENCE,
`AND OTHER QUALIFICATIONS ............................................................... 4 
`III. ASSIGNMENT AND MATERIALS CONSIDERED .................................. 5 
`IV. UNDERSTANDING OF THE LAW ............................................................. 6 
`V.
`LEVEL OF SKILL IN THE ART .................................................................. 6 
`VI. THE 300 PATENT’S EFFECTIVE FILING DATE ..................................... 6 
`VII. GROUND 1: DUSIJA IN VIEW OF THE KNOWLEDGE OF A
`POSA .............................................................................................................. 7 
`A.
`Limitation [1.E] .................................................................................... 7 
`1.
`The Claims Do Not Require the “Random Access
`Volatile Memory” to Be in a Specific Location ........................ 7 
`A POSA Would Not Have Been Discouraged from Using
`Dusija with a Controller RAM Cache ........................................ 8 
`a.
`Dusija Does Not Require the Use of a Flash
`Memory Cache ................................................................. 8 
`A POSA Would Have Understood Dusija’s
`“Controller” to Have RAM ............................................ 11 
`The Proposed Combination Does Not “Change the
`Fundamental Principle of Dusija’s Operation” ............. 12 
`i.
`A POSA Would Have Recognized That the
`Use of Controller RAM Cache with Dusija
`Would Be Operable and Desirable ...................... 13 
`A POSA Would Have Understood That
`Avoiding Toggling Is Not “Fundamental” to
`Dusija ................................................................... 15 
`iii. A POSA Would Have Understood That
`Avoiding a Rewrite Is Not Fundamental to
`Dusija ................................................................... 18 
`
`ii.
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`2
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`Reply Declaration of Dr. David Liu
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`d.
`
`A POSA Would Have Known That a Flash
`Memory Cache Has Many Disadvantages When
`Compared to a Cache in Controller RAM ..................... 19 
`i.
`A POSA Would Have Known That the Use
`of a Flash Memory Cache Puts Substantial
`Extra Wear on the Flash Memory ....................... 20 
`A POSA Would Have Known That a Flash
`Memory Cache Would Typically Have
`Slower Real-World Performance Than a
`RAM Cache ......................................................... 22 
`iii. A POSA Would Have Known That the Use
`of a Flash Memory Cache in Dusija Would
`Lead to Greater Cost and Complexity ................. 24 
`iv. A POSA Would Have Recognized a
`Performance Disadvantage in Putting the
`Comparison Logic on a Flash Memory Chip ...... 25 
`The Use of A “Random Access Volatile Memory” In
`Place of Dusija’s Flash Memory Cache Would Have
`Predictable Results to A POSA................................................ 27 
`Limitation [1.H] .................................................................................. 29 
`B.
`C. Other Limitations ............................................................................... 32 
`VIII. DECLARATION .......................................................................................... 32 
`
`
`
`ii.
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`
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`3.
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`
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`3
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`I.
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`Reply Declaration of Dr. David Liu
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`I, Dr. David Liu, hereby declare as follows:
`
`INTRODUCTION
`1.
`I have been retained by Micron Technology, Inc. (“Micron”) as an
`
`independent expert consultant in this proceeding before the United States Patent
`
`and Trademark Office (“PTO”). I am not an employee of Micron or any affiliate
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`or subsidiary of Micron.
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`2.
`
`I have been asked to consider whether certain references teach or
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`suggest the features recited in certain claims of U.S. Patent No. 10,950,300, which
`
`I refer to herein as the 300 Patent, and whether certain claims of the 300 Patent are
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`unpatentable as obvious.
`
`3. My opinions and the bases for my opinions are set forth below.
`
`4.
`
`I am being compensated at $550 per hour for my work, plus
`
`reimbursement for any reasonable expenses. My compensation is based solely on
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`the amount of time that I devote to activity related to this case and is in no way
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`contingent on the nature of my findings, the presentation of my findings in
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`testimony, or the outcome of this or any other proceeding. I have no other
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`financial interest in this proceeding.
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`II. EDUCATION BACKGROUND, PROFESSIONAL EXPERIENCE,
`AND OTHER QUALIFICATIONS
`5. My education, background, and professional qualifications are set
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`forth in Paragraphs 5–14 of the previous declaration that was submitted in
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`
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`4
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`connection with this proceeding (which I understand has been designated as
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`Reply Declaration of Dr. David Liu
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`Exhibit 1009). My curriculum vitae (“CV”) is included as Exhibit 1058 and
`
`provides an accurate identification of my background and experience.
`
`III. ASSIGNMENT AND MATERIALS CONSIDERED
`6.
`I have been asked to provide some additional opinions and elaboration
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`regarding the state of the art and the understanding of a person of skill in the art
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`(“POSA”) as of the effective filing date of the 300 Patent.
`
`7.
`
`The opinions expressed in this declaration are not exhaustive of my
`
`opinions regarding the unpatentability of the claims of the 300 Patent. Therefore,
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`the fact that I do not address a particular point should not be understood to indicate
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`an agreement on my part that any claim complies with the requirements of any
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`applicable patent or other rule.
`
`8.
`
`I reserve the right to amend and supplement this declaration in light of
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`additional evidence, arguments, or testimony presented during this IPR or related
`
`proceedings on the 300 Patent.
`
`9.
`
`In forming the opinions set forth in this declaration, I have considered
`
`and relied upon my education, knowledge of the relevant field, knowledge of
`
`scientific and engineering principles, and my experience. I have also reviewed and
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`considered the 300 Patent (Exhibit 1007), its prosecution history (Exhibit 1008),
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`the materials listed in my prior declaration (Exhibit 1009), the materials cited in
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`
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`5
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`Dr. Khatri’s declarations (Exhibits 2001 and 2014), Dr. Khatri’s deposition
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`Reply Declaration of Dr. David Liu
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`testimony (Exhibit 1060), the Patent Owner Preliminary Response, the Patent
`
`Owner Response, and the following additional materials:
`
`Exhibit
`
`Description
`
`1012
`
`U.S. Patent Application Publication No. 2009/0327591
`(“Moshayedi”)
`
`1068
`
`U.S. Patent No. 8,010,873 (“Kirschner”)
`
`IV. UNDERSTANDING OF THE LAW
`10. Paragraphs 19–34 of my prior declaration (Ex. 1009) included a
`
`section discussing my understanding of the law. I am not an attorney, but I have
`
`been instructed in and applied the law as described in my prior declaration.
`
`V. LEVEL OF SKILL IN THE ART
`11. Paragraphs 35–38 of my prior declaration include my understanding
`
`of the level of skill in the art. I have applied the same definition of a person of
`
`ordinary skill in the art here.
`
`VI. THE 300 PATENT’S EFFECTIVE FILING DATE
`12. As in my prior declaration, my opinions in this declaration are formed
`
`from the perspective of a person of ordinary skill in the art as of July 19, 2011,
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`including both the knowledge of a person of ordinary skill in the art at that time as
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`well as how a person of ordinary skill in the art would have understood the prior
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`art.
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`
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`6
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`Reply Declaration of Dr. David Liu
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`
`VII. GROUND 1: DUSIJA IN VIEW OF THE KNOWLEDGE OF A POSA
`A. Limitation [1.E]
`1.
`The Claims Do Not Require the “Random Access Volatile
`Memory” to Be in a Specific Location
`13. The independent claims of the 300 Patent recite “[a] system for
`
`storing data comprising . . . at least one random access volatile memory.”
`
`Ex. 1007 (“300 Patent”), claims 1, 12. A POSA would have understood that the
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`“random access volatile memory” need not be in any particular location. A POSA
`
`reviewing the claims would understand that no claim element restricts the location
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`of the “random access volatile memory.” For example, no claim element requires
`
`the “random access volatile memory” to be in the same chip as the “controller,” or
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`in the same chip as any “non-volatile memory element.”
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`14. Confirming this understanding, claim 3 of the 300 Patent recites “[t]he
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`system of claim 1, wherein at least one of the random access volatile memory or
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`the MLC and SLC nonvolatile memory elements are embedded in the at least one
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`controller.” 300 Patent, claim 3. A POSA reading claim 3 would understand that
`
`claim 3 potentially restricts the location of the “random access volatile memory” to
`
`being “embedded” in the controller. A POSA would thus understand that claim 1,
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`which would presumably be broader than claim 3, would not restrict the location of
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`the “random access volatile memory” to the controller.
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`
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`Reply Declaration of Dr. David Liu
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`2.
`
`A POSA Would Not Have Been Discouraged from Using
`Dusija with a Controller RAM Cache
`15. As I explained in my original declaration (Exhibit 1009 (“Liu
`
`Decl.”)), a POSA would have been motivated to use Dusija with a controller RAM
`
`cache. Liu Decl., ¶¶ 123–232. Neither Patent Owner’s arguments nor Dr. Khatri’s
`
`testimony alter my conclusion and, in subsections (a)–(d) below, I provide
`
`additional detail responsive to Patent Owner’s arguments and supporting my
`
`conclusions.
`
`16. At bottom, a POSA knew that controller RAM was typically used to
`
`implement caches, had well understood advantages as compared to a flash memory
`
`cache, and could be used to perform Dusija’s data integrity tests. Liu Decl., ¶¶ 60–
`
`62, 129–38. The fact that a controller RAM cache has some disadvantages as
`
`compared to a flash memory cache would not have made RAM caches undesirable
`
`to a POSA. The idea of implementing Dusija’s cache in controller RAM, and all
`
`challenged claims as a whole, would have still been obvious.
`
`a.
`
`Dusija Does Not Require the Use of a Flash Memory
`Cache
`17. Contrary to Dr. Khatri’s testimony, Dusija’s cache is not always
`
`disclosed as “being part of flash memory array 200.” Ex. 2014 (“Khatri Decl.”),
`
`¶ 80. While it is true that some embodiments of Dusija use non-volatile memory
`
`as a cache, Dusija also discloses embodiments in which the location of the cache is
`
`
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`8
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`not specified. Dr. Khatri repeatedly cites paragraphs [0127]- [0131] (associated
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`Reply Declaration of Dr. David Liu
`
`with an “alternative embodiment” of Figure 15) and paragraphs [0132]-[0150]
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`(associated with Figures 16A-C). POR, 37-38, 42-44. These embodiments, to be
`
`sure, describe the use of the non-volatile memory for caching. However, Dusija
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`discloses a separate set of embodiments, discussed in paragraphs [0108]-[0118]
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`(associated with Figures 14A-B) and [0119]-[0126] (associated with the primary
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`embodiment of Figure 15). My prior testimony is based on Figures 14A-B and the
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`primary embodiment of Figure 15, not the “alternative embodiment” of Figure 15
`
`and Figures 16A-C (on which PO relies). E.g., Liu Decl., ¶ 176 (citing paragraphs
`
`[0111]-[0116], [0119]-[0124]). For the following reasons, a POSA reviewing
`
`Dusija would have recognized that, in Figures 14A-B and the primary embodiment
`
`of Figure 15, Dusija left the location of the cache open.
`
`18. First, Dusija’s silence as to the location of the cache in Figures 14A-B
`
`would have suggested to a POSA that the cache is not in flash memory. Figures
`
`16A-C of Dusija and the associated description in paragraphs [0132]-[0140]
`
`expressly depict the use of flash memory as the cache. Similarly, Figures 20A-C
`
`of Dusija and the associated description in paragraphs [0163]-[0187] expressly
`
`depict the use of flash memory as a cache. However, Figures 14A-B do not depict
`
`a cache at all. The description associated with Figures 14A-B (specifically,
`
`paragraph [0112]) notes that “cached” data may be used to verify a post-write read
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`
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`9
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`operation, but Dusija does not specify where the cache is. Ex. 1010
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`Reply Declaration of Dr. David Liu
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`(“Dusija”), [0112]. In light of Dusija’s decision to specify the location of the
`
`cache in the Figure 16 and Figure 20 embodiments, a POSA would have
`
`understood Dusija’s decision to not specify the location of the cache in paragraph
`
`[0112] (or in associated Figures 14A-B) to be a conscious decision by Dusija to
`
`leave the location of the cache open. And a POSA would have immediately
`
`thought of controller RAM as a common, intuitive, and desirable location for the
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`cache referenced in paragraph [0112]. Liu Decl., ¶¶ 60–62, 129–130, 133–36, 178.
`
`19. Second, regarding Figure 15, Dusija states that “[i]n an alternative
`
`embodiment, the first portion serves as a cache for incoming data, so a cache[d]
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`copy of the input data is programmed into the cache.” Dusija, [0127]. That the use
`
`of the “first portion” for the cache is an “alternative embodiment” strongly
`
`suggests that there is at least one embodiment in which the “first portion” is not
`
`used for the cache. Thus, a POSA would have understood that paragraphs [0109]–
`
`[0126] of Dusija describe embodiments in which the non-volatile memory
`
`(specifically, the “first portion”) would not be used for the cache.
`
`20. Third, the differences between Figures 14A-B on the one hand, and
`
`Figures 16A-C on the other hand, further indicate that not all embodiments of
`
`Dusija involve the use of the non-volatile memory as a cache. Figures 16A-C
`
`depict the use of the non-volatile memory as a cache. Figures 14A-B, on the other
`
`
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`10
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`hand, are silent as to where the cache is. A POSA would have interpreted Figures
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`Reply Declaration of Dr. David Liu
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`14A-B to use a cache that is not non-volatile memory because, otherwise, Figures
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`14A-B (and the associated textual description) would serve no purpose in the
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`specification.
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`21. For these reasons, a POSA would not have understood the proposed
`
`combination to involve replacing Dusija’s cache with a fundamentally different
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`component.
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`b.
`
`A POSA Would Have Understood Dusija’s
`“Controller” to Have RAM
`I understand Patent Owner to be arguing that a POSA would have
`
`22.
`
`understood Dusija’s controller to lack RAM. POR, 45. I disagree.
`
`23. As an initial matter, I note that although the Patent Owner cites Dr.
`
`Khatri’s declaration in support of this assertion, Dr. Khatri never testifies that
`
`Dusija’s controller lacks RAM. POR, 45 (citing Khatri Decl., ¶ 83). And, contrary
`
`to Patent Owner’s assertion, I have already explained why a POSA would have
`
`understood Dusija’s controller to have RAM. Liu Decl., ¶ 130.
`
`24. First, as I explained in my previous declaration, the use of RAM was
`
`typically used with SSD controllers at the relevant time. Liu Decl., ¶ 130;
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`Ex. 1019 (“Micheloni”), 14 (showing “DRAM” as part of a solid-state drive); Id.,
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`516 (showing “DRAM” connected to a controller as part of the “[h]ardware
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`11
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`architecture of [an] SSD”); Ex. 1012 (“Moshayedi”), [0028] (noting that “DRAM
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`Reply Declaration of Dr. David Liu
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`106 may be used to buffer data to be written into the flash array 108”).
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`25. Second, Dusija incorporates by reference multiple references—
`
`namely Paley (Ex. 1028) and Harari (Ex. 1049)—that expressly disclose the use of
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`RAM with flash memory controllers. Liu Decl., ¶¶ 131–33 (discussing Paley),
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`134–36 (discussing Harari).
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`26. Third, Dusija discloses features that a POSA would have understood
`
`to be implemented using RAM. For example, Dusija discloses that its controller
`
`performs logical-to-physical address translation. Dusija, [0060]. And Dusija
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`discloses that its controller runs firmware code. Dusija, [0062]. A POSA would
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`have understood that these features would be implemented with the use of
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`controller RAM. Ex. 1060 (“Khatri Dep.”), 69:1–14 (admitting that RAM was
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`commonly and desirably used by SSD controllers for logical-to-physical address
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`translation); Micheloni, 12 (showing the use of RAM for firmware code
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`execution).
`
`c.
`
`The Proposed Combination Does Not “Change the
`Fundamental Principle of Dusija’s Operation”
`I understand Patent Owner and Dr. Khatri to be asserting that the
`
`27.
`
`proposed modification “changes the fundamental principle of Dusija’s operation
`
`with respect to cache usage.” POR, 43; Khatri Decl., ¶ 80. I disagree for at least
`
`the following reasons.
`
`
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`12
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`Reply Declaration of Dr. David Liu
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`i.
`
`A POSA Would Have Recognized That the Use
`of Controller RAM Cache with Dusija Would
`Be Operable and Desirable
`
`28. A POSA would have recognized that the use of a controller RAM
`
`cache with Dusija would be operable and in fact desirable because it improves
`
`reliability. As Dusija explains and was well known in the art, the programming of
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`pages of data into flash memory creates the potential for errors resulting from over
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`programming and field coupling. Dusija, [0093]–[0097]. As a result, the data
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`stored in a flash memory cell may not necessarily be the data that was intended to
`
`be stored.
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`29. Dusija addresses this problem through its “post-write read operation.”
`
`Dusija, [0018]. The crux of Dusija’s post-write read operation is writing data to a
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`less-expensive but also less reliable form of storage (Dusija’s “second portion”),
`
`reading it back, and determining whether the data has errors. If errors are detected,
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`the data is written to a more reliable (but more expensive) form of storage
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`(Dusija’s “first portion”). Id., [0018]; id., Figure 15.
`
`30. Dusija describes two ways of determining whether there are errors in
`
`the “second portion.” First, Dusija discloses storing ECC (error-correction code)
`
`bits with the data; these ECC bits can be checked upon reading the data and used to
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`determine whether the data has been corrupted. Dusija, [0112]. Second, Dusija
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`discloses storing an “original” copy of the data in a cache and comparing the copy
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`13
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`to the data read from the second portion. Id. If the copies of the data don’t match,
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`Reply Declaration of Dr. David Liu
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`the copy from the second portion is determined to be erroneous. Id.
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`31. One purpose of Dusija is to provide “a nonvolatile memory of high
`
`storage capacity without the need for a resource-intensive ECC over designed for
`
`the worse-case.” Dusija, [0017]. The post-write read operation helps achieve this
`
`because it tests data after it is written and, by doing so, detects write errors. These
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`errors can then be corrected and made less likely in the future by saving the data to
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`a more reliable storage medium (i.e., the “first portion”). In this way, the chance
`
`of data being stored with write errors is minimized. As a result, fewer ECC bits
`
`are needed to ensure the correctness of the data.1
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`32. A POSA would have understood that, in embodiments of Dusija that
`
`use a cache, it is important that the cache store the cached copy accurately. The
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`method relies on the cached copy being accurate because, in the event of a
`
`mismatch between the retained copy and the copy stored in the second portion, the
`
`technique assumes that the cached copy is the correct one.
`
`
`1 Some ECC bits are necessary even in systems that perform Dusija's post-write
`
`read at least because errors may also occur while the data is stored or due to read
`
`operations. Dusija, [0098]–[0101].
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`
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`14
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`Reply Declaration of Dr. David Liu
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`33. A POSA would have understood that the use of a RAM cache, instead
`
`of a cache in the “first portion,” provides a better guarantee that the cached copy is
`
`accurate. This is because the “first portion,” like the “second portion,” is flash
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`memory. Although the first portion is more reliable flash memory, it is still
`
`vulnerable to over-programming and field coupling—the same mechanisms which
`
`Dusija describes as causing write errors. A POSA would have known that RAM
`
`(whether DRAM or SRAM) is far less likely to be subject to a write error. Khatri
`
`Dep., 86:8–12 (noting that DRAM can sustain more write cycles than flash
`
`memory), 89:6–14 (noting that SRAM can sustain more write cycles than flash
`
`memory); Ex. 1068 (U.S. Pat. No. 8,010,873), 1:23–52 (noting that RAM is more
`
`reliable than flash memory); Ex. 1015 (“Varkony”), 6:49-51 (noting that “since
`
`NAND Flash is more prone to bit errors, a mechanism is needed to ensure data
`
`integrity when loading data from or into the NAND Flash,” and explaining that a
`
`RAM cache is used for this purpose). Thus, a POSA would have understood that a
`
`RAM cache would serve Dusija’s purpose of ensuring reliability.
`
`ii.
`
`A POSA Would Have Understood That
`Avoiding Toggling Is Not “Fundamental” to
`Dusija
`
`34. A POSA would have understood that avoiding toggling (a purported
`
`benefit of a flash memory cache) is not “fundamental” to Dusija. Dr. Khatri makes
`
`much of a passage in Dusija stating that “[b]y not making the comparison at the
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`
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`15
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`controller, the data does not have to be toggled out to the controller, [and] much
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`Reply Declaration of Dr. David Liu
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`time can be saved.” Khatri Decl., ¶ 51 (quoting Dusija, [0136]). This passage
`
`describes an advantage of making the comparison on the flash memory chip. But
`
`nowhere does Dusija state that the alternative—that is, making the comparison at
`
`the controller—would not work or be incompatible with a working system.
`
`35. On the contrary, a POSA would have understood that the use of a
`
`RAM cache would equally, if not more so, improve reliability and meet Dusija’s
`
`stated purpose of providing “a nonvolatile memory of high storage capacity
`
`without the need for a resource-intensive ECC over designed for the worse-case.”
`
`Dusija, [0017]. As I explained above in paragraphs 28–33, the crux of Dusija’s
`
`technique is the post-write read operation, which detects errors that can occur in
`
`flash memory writes. Dusija’s post-write read operation, by detecting write errors,
`
`reduces the number of ECC bits required to ensure data integrity, thus maintaining
`
`the reliability of the system while reducing the computational costs associated with
`
`ECC. See paragraphs 28–33, supra. The proposed combination’s use of a
`
`controller RAM cache furthers this goal because RAM caches have greater
`
`endurance and are less likely to have write errors than flash memory caches. See
`
`id.
`
`36. To a POSA, the context of Dusija’s “toggling” discussion would have
`
`illustrated its lack of importance to Dusija as a whole. The advantage of avoiding
`
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`16
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`toggling is discussed in the context of what Dusija describes in the preceding
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`Reply Declaration of Dr. David Liu
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`paragraph as “another preferred embodiment.” Dusija, [0135]. That avoiding
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`toggling is a benefit of “another preferred embodiment” would have suggested to a
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`POSA that there are preferred embodiments that require toggling.
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`37.
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`Indeed, a POSA would have understood Dusija to expressly disclose
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`embodiments that require toggling. Dusija explains that in a “preferred”
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`embodiment, ECC (as opposed to a comparison with a cached copy) is used to
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`verify data after a post-write read. Dusija, [0109] (noting that Figure 14A
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`discloses a “preferred embodiment of the invention”); id., [0112] (description,
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`associated with Figure 14A, noting the use of ECC to verify the post-write read).
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`Dusija describes ECC checking as occurring at the controller. E.g., id., Figure 1
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`(showing ECC Processor 62 as part of Controller 102), [0062], [0087]. Thus,
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`Dusija’s ECC embodiments necessarily involves the “toggling” of data from the
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`flash memory device to the controller to be checked. What’s more, if the post-
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`write read fails, Dusija necessarily requires another toggle operation to transfer the
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`data from the controller back to the flash memory device. Indeed, Dr. Khatri
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`admitted that these ECC embodiments require “toggling” data out to the controller
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`and, if errors are detected, “toggling” data back to the flash memory. Khatri Dep.,
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`135:16-136:8, 136:15-21, 137:13-138:3, 141:13-17.
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`Reply Declaration of Dr. David Liu
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`38. Dusija’s ECC embodiments thus confirm what a POSA would have
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`already known, which is that avoiding toggling data is not “fundamental” to
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`Dusija.
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`iii. A POSA Would Have Understood That
`Avoiding a Rewrite Is Not Fundamental to
`Dusija
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`39.
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`I understand Patent Owner to suggest that avoiding a rewrite of data
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`when excessive error bits are detected (which, to PO, is a benefit of the use of the
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`flash memory cache) is “fundamental” to Dusija. POR, 44-45. Specifically, Patent
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`Owner appears to assert that the use of a flash memory cache is beneficial because
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`it enables the redirection of data to the cache, as opposed to a rewrite, in the event
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`of excessive errors in the version of the data stored in the “second portion.” Id.
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`But PO never asserts that Dusija’s system would be rendered inoperable or
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`undesirable if rewrites were necessary. And, as I explain elsewhere in this
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`declaration, embodiments using a RAM cache not only would be operable, but also
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`desirable. See Section VII.A.2.c.i, supra; Section VII.A.2.d, infra.
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`40.
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`Indeed, Dusija discloses multiple embodiments—including
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`embodiments that use a flash memory cache—in which rewriting data is necessary.
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`See, e.g., Dusija, Figure 16C (showing a rewrite despite the use of a flash memory
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`cache). And Dusija discloses embodiments not involving the use of flash memory
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`cache—such as embodiments using ECC—in which a rewrite is necessary. E.g.,
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`id., [0116]; Khatri Dep., 140:10–141:17 (acknowledging that, in Dusija’s ECC
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`Reply Declaration of Dr. David Liu
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`embodiments, data must be rewritten to the “first portion” if errors are detected).
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`A POSA would not have considered avoiding a rewrite to be “fundamental” to
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`Dusija when Dusija discloses multiple embodiments that perform rewrites.
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`41.
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`In sum, a POSA would have recognized that avoiding rewrites is a
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`benefit of some flash memory cache embodiments of Dusija, but not a necessary
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`characteristic of a desirable system, and certainly not “fundamental” to Dusija.
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`d.
`
`A POSA Would Have Known That a Flash Memory
`Cache Has Many Disadvantages When Compared to
`a Cache in Controller RAM
`I understand Patent Owner to argue that a flash memory cache has two
`
`42.
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`purported advantages: (1) avoiding the need to “toggle” data from flash memory to
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`the controller; and (2) enabling a redirection of accesses to the existing cached
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`copy in the first portion (as opposed to a rewrite of the data to the first portion).
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`POR, 44-45, 50. But a POSA would have understood that flash memory caches
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`come with significant disadvantages as compared to a RAM caches. In light of
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`these disadvantages, a POSA would not have been discouraged from using a RAM
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`cache. Instead, a POSA would have understood that Dusija’s cache could
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`desirably be implemented either in flash memory or in RAM, and that each of
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`these options would have advantages and disadvantages.
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`
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`Reply Declaration of Dr. David Liu
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`i.
`
`A POSA Would Have Known That the Use of a
`Flash Memory Cache Puts Substantial Extra
`Wear on the Flash Memory
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`43. As I explained in my previous declaration, flash memory has a limited
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`lifetime; it can only sustain a certain number of write cycles before its reliability is
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`compromised. Liu Decl., ¶¶ 85, 129 n.6; Khatri Dep., 86:8–12, 89:6–14; 300
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`Patent, 3:41–50. RAM (whether DRAM or SRAM) has much greater write
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`endurance than flash memory. Liu Decl., ¶ 61; Khatri Dep., 86:8–12, 89:6–14.
`
`44. The use of flash memory for Dusija’s cache will necessarily cause
`
`additional write cycles on the flash memory. For example, in the embodiment
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`described in Figures 16A-C of Dusija, the best case (i.e., when no errors are
`
`detected) is two writes to flash memory per write operation: one write to the
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`“second portion” and one write to the “first section” of the “first portion.” The
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`worst case (i.e., when errors are detected) is three writes to flash memory per write
`
`operation: one write to the “second portion,” one write to the “first section” of the
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`“first portion,” and one write to the “second section” of the “first portion.” See
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`Dusija, Figures 16A-C. In the embodiment described in paragraphs [0127]–
`
`[0129], there are always two writes to flash memory: one to the “second portion”
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`and one write to the “first portion.” Id., [0127]–[0129].
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`45. A POSA would have known that the use of a RAM cache would result
`
`in fewer write cycles on the flash memory. In the best case (i.e., when no errors
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`
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`20
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`are detected), the use of a RAM cache means that there is only one write to flash
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`Reply Declaration of Dr. David Liu
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`memory: a write to the “second portion.” Dusija, [0111]. In the worst case (i.e.,
`
`when errors are detected), the use of a RAM cache would result in two writes to
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`flash memory: a write to the “second portion,” and a write to the “first portion.”
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`Id., [0111], [0116].
`
`46. A POSA would have understood that in a properly designed and
`
`manufactured system, most writes to flash memory will not result in errors. Thus,
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`the “best case” will be much more common than the “worst case.” See also Dusija,
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`[0024] (noting that the “additional rewrites” are “infrequent”). As a result, the
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`benefit of a RAM cache in the best case (requiring just one write to flash memory
`
`instead of two) will predominate.
`
`47. This understanding is consistent with the general knowledge of a
`
`POSA as to the benefits of RAM caches in flash memory devices. The Harari
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`reference, which is incorporated by Dusija, notes that a RAM cache can be used to
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`“insulate” a flash memory from writes, “reduc[ing] the number of writes to the
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`Flash EEprom memory.” Ex. 1049 (“Harari”), at 12:65–13:7. And the Micheloni
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`textbook similarly notes that a DRAM cache can beneficially be used to decrease
`
`wear on flash memory:
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`There are also hybrid architectures which combine different
`
`types of memory. Most common is usage of DRAM as
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`Reply Declaration of Dr. David Liu
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`memory cache. During write access the cache is used for
`
`storing data before transfer to the Flash. The benefit is that
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`data updating, e.g. in tables, is faster and does not wear out
`
`the Flash.
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`Micheloni, 44 (emphasis added).
`
`48. A POSA would thus have understood that the use of a RAM cache is
`
`desirable over the use of a flash memory cache because it causes much less wear
`
`on the flash memory device. And a POSA would have recognized that using the
`
`flash memory as the cache would cause the flash memory to wear out significantly
`
`sooner than if a RAM cache were used.
`
`ii.
`
`A POSA Would Have Known That a Flash
`Me