(19) United States
`(12) Patent Application Publication (10) Pub. No.: US 2009/0300269 A1
`(43) Pub. Date:
`Dec. 3, 2009
`Radke et al.
`
`US 200903 00269A1
`
`(54) HYBRID MEMORY MANAGEMENT
`
`Publication Classification
`
`(76) Inventors:
`
`William H. Radke, Los Gatos, CA
`(US); Michael Murray, Mountain
`View, CA (US); Martin Ragnar
`Furuhjelm, Grass Valley, CA (US);
`John Geldman, Los Gatos, CA
`(US)
`Correspondence Address:
`LEFFERT JAY & POLGLAZE, P.A.
`Attn: Thomas W. Leffert
`P. O. Box 581009
`Minneapolis, MN 55458-1009 (US)
`
`(21) Appl. No.:
`
`12/127,945
`
`(22) Filed:
`
`May 28, 2008
`
`(51) Int. Cl.
`(2006.01)
`G06F 2/02
`(52) U.S. Cl. ................................. 711/103; 711/E12.008
`(57)
`ABSTRACT
`Methods and apparatus for managing data storage in hybrid
`memory devices utilizing single leveland multilevel memory
`cells. Logical addresses can be distributed between single
`level and multilevel memory cells based on a frequency of
`write operations performed. Initial storage of data corre
`sponding to a logical address in memory can be determined
`by various methods including initially writing all data to
`single level memory or initially writing all data to multilevel
`memory. Other methods permit a host to direct logical
`address writes to single level or multilevel memory cells
`based on anticipated usage.
`
`200
`
`
`
`WRITE DATA TO
`INTENDED LBA
`
`CONTROLLER
`DIRECTS WRITE OF
`DATA TOINTENDED
`LBAN MLC MEMORY
`
`
`
`
`
`CONTROLLER
`DiRECTS WRITE OF
`DATA TO INTENDED
`LBA IN SLC MEMORY
`
`
`
`
`
`214
`
`208
`
`CONTROLLER
`TRACKS WRITESTO
`LBAS RESIDING IN
`MLC AND SC
`MEMORY
`
`CONTROLLER
`TRACKS WRITES TO 216
`BAS RESIDING IN
`MLC AND SLC
`MEMORY
`
`ANYMCLBA
`USAGE EXCEEDING
`THRESHOLD?
`
`
`
`SUFFICIENT
`SPARES IN SLC
`MEMORY?
`
`
`
`
`
`
`
`
`
`
`
`
`
`MOVELEAST
`WRITTENTO LEA
`RESIDING IN SLC
`MEMORY TO MLC
`MEMORY
`
`*
`
`
`
`MOVE IDENTIFIED
`LBATO SLC
`MEMORY
`
`
`
`
`
`Micron Ex. 1052, p. 1
`Micron v. Vervain
`IPR2021-01550
`
`

`

`Patent Application Publication
`
`Dec. 3, 2009 Sheet 1 of 6
`
`US 2009/0300269 A1
`
`
`
`AO-AX
`CONTROLLER
`PROCESSOR AH) 170
`
`---
`
`142
`
`MEMORY
`ARRAY
`132
`
`MLC
`MEMORY
`ARRAY
`134
`
`FIG. 1
`
`Micron Ex. 1052, p. 2
`Micron v. Vervain
`IPR2021-01550
`
`

`

`Patent Application Publication
`
`Dec. 3, 2009 Sheet 2 of 6
`
`US 2009/0300269 A1
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`206
`
`208
`
`200
`
`WRITE DATA TO
`INTENDED LBA
`
`CONTROLLER
`DIRECTS WRITE OF
`DATA TO INTENDED
`LBAN MLC MEMORY
`
`
`
`
`
`CONTROLLER
`DIRECTS WRITE OF
`DATA TO INTENDED
`BAIN SLC MEMORY
`
`
`
`214
`
`CONTROLLER
`TRACKS WRITESTO
`BAS RESIDING IN
`MLC AND SLC
`MEMORY
`
`CONTROLLER
`TRACKS WRITES TO 216
`LBAS RESIDING IN
`MLC AND SLC
`MEMORY
`
`ANY MLCLBA
`USAGE EXCEEDING
`THRESHOLD?
`
`
`
`SUFFICIENT
`SPARES IN SLC
`MEMORY?
`
`212
`
`
`
`MOVE DENTIFIED
`LBA TO SLC
`MEMORY
`
`
`
`MOVE LEAST
`WRITTENTO LEA
`RESIDING IN SLC
`MEMORY TO MLC
`MEMORY
`
`FIG. 2
`
`Micron Ex. 1052, p. 3
`Micron v. Vervain
`IPR2021-01550
`
`

`

`Patent Application Publication
`
`Dec. 3, 2009 Sheet 3 of 6
`
`US 2009/0300269 A1
`
`
`
`
`
`
`
`306
`
`302
`
`CONTROLLER
`
`SLC TER
`
`
`
`
`
`310 N
`
`304
`
`3 1
`
`322
`
`(SPARE)
`(SPARE)
`LBA=9, USAGE=17
`LBA=6, USAGE=112
`BAE2, USAGE=1
`LBAF3, USAGE=2
`
`3 O 8
`
`MCTER
`
`314
`
`(SPARE)
`(SPARE)
`LBA=9, USAGE=17
`LBA=6, USAGE=112
`LBA=2, USAGE=1
`LBA=3, USAGE=2
`
`316
`
`
`
`
`
`
`
`
`
`
`
`FIG. 3
`
`Micron Ex. 1052, p. 4
`Micron v. Vervain
`IPR2021-01550
`
`

`

`Patent Application Publication
`
`Dec. 3, 2009 Sheet 4 of 6
`
`US 2009/0300269 A1
`
`300
`
`306
`
`302
`
`CONTROLLER
`
`
`
`322
`
`SLC TER
`
`310-
`(SPARE)
`(SPARE)
`LBA=9, USAGE=17
`LBA6, USAGE=112
`k(BAS2. USAGEST
`LBA=3, USAGE=2
`
`- a
`
`3O8
`
`418
`
`MLCTER
`
`314 N
`
`312
`(SPARE)
`(SPARE)
`LBA=9, USAGE=17
`LBA=6, USAGE=112
`(BAE2, USAGEst
`
`418
`
`LBA.2, USAGE=1
`
`LBAE2, USAGE=1
`
`
`
`FIG. 4
`
`Micron Ex. 1052, p. 5
`Micron v. Vervain
`IPR2021-01550
`
`

`

`Patent Application Publication
`
`Dec. 3, 2009 Sheet 5 of 6
`
`US 2009/0300269 A1
`
`ra 302
`
`CONTROLLER
`
`
`
`
`
`SLC TER
`
`310 N
`(SPARE)
`LBA=7, USAGE=1
`LBA=9, USAGE=17
`LBA=6, USAGE=112
`(SPARE)
`LBA=3, USAGEF2
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`LBA=3, USAGE=2
`
`
`
`
`
`LBA-2, USAGE=1
`
`LBA=2, USAGE=1
`
`FIG. 5
`
`Micron Ex. 1052, p. 6
`Micron v. Vervain
`IPR2021-01550
`
`

`

`Patent Application Publication
`
`Dec. 3, 2009 Sheet 6 of 6
`
`US 2009/0300269 A1
`
`
`
`
`
`
`
`EGIOOBC1 NWT TOO
`
`gºg
`
`???
`EHOVO V LVC] / ESNES
`
`
`
`ÅRH LATIO?HIO
`
`Õ55
`
`AAO?!
`
`EGOOBC1
`
`575
`
`SSERHCJCIV/
`
`
`
`KE) Aguiñ5810
`
`/19
`
`Micron Ex. 1052, p. 7
`Micron v. Vervain
`IPR2021-01550
`
`

`

`US 2009/03 00269 A1
`
`Dec. 3, 2009
`
`HYBRD MEMORY MANAGEMENT
`
`TECHNICAL FIELD
`0001. The present disclosure relates generally to memory
`devices and in particular the present disclosure relates to
`managing data stored in a memory device having single and
`multilevel memory cell storage capability.
`
`BACKGROUND
`0002 Memory devices are typically provided as internal,
`semiconductor, integrated circuits in computers or other elec
`tronic devices. There are many different types of memory
`including random-access memory (RAM), read only memory
`(ROM), dynamic random access memory (DRAM), synchro
`nous dynamic random access memory (SDRAM), and flash
`memory.
`0003 Flash memory devices have developed into a popu
`lar source of non-volatile memory for a wide range of elec
`tronic applications. Flash memory devices typically use a
`one-transistor memory cell that allows for high memory den
`sities, high reliability, and low power consumption. Common
`uses for flash memory include personal computers, personal
`digital assistants (PDAs), digital cameras, and cellular tele
`phones. Program code and system data, such as a basic input/
`output system (BIOS), are typically stored in flash memory
`devices for use in personal computer systems.
`0004 Flash memory typically utilizes one of two basic
`architectures known as NOR Flash and NAND Flash. The
`designation is derived from the logic used to read the devices.
`In a NAND type flash memory array architecture, the floating
`gate memory cells of the memory array are arranged in a
`matrix of rows and columns. The memory cells of the array
`are also arranged together in Strings, typically of 8, 16, 32, or
`more each, where the memory cells in the string are con
`nected together in series, Source to drain, between a common
`source line and a column transfer line, often referred to as a bit
`line. The array is then accessed by a row decoderactivating a
`row of floating gate memory cells by selecting the word line
`connected to their gates. In addition, bit lines can also be
`driven high or low depending on the current operation being
`performed.
`0005. As the performance and complexity of electronic
`systems increase, the requirement for additional memory in a
`system also increases. However, in order to continue to
`reduce the costs of the system, it is desirable to keep the parts
`count low. This can be accomplished by increasing the
`memory density of an integrated circuit by using Such tech
`nologies as multilevel cells (MLC). For example, MLC
`NAND flash memory is a cost effective non-volatile memory.
`0006 Multilevel memory cells assign a data state (e.g., as
`represented by a bit pattern) to a specific range of threshold
`voltages (Vt) stored on the memory cell. Single level memory
`cells (SLC) permit the storage of a single bit of data on each
`memory cell. Meanwhile, MLC technology permits the stor
`age of two or more bits per cell (e.g., 2, 4, 8, 16 bits), depend
`ing on the quantity of threshold Voltage ranges assigned to the
`cell and the stability of the assigned threshold Voltage ranges
`during the lifetime operation of the memory cell. The number
`of threshold Voltage ranges (e.g., levels), which are some
`times referred to as Vit distribution windows, used to represent
`a bit pattern comprised of N-bits is 2'. For example, one bit
`may be represented by two levels, two bits by four levels,
`three bits by eight levels, etc.
`
`0007 For example, a cell may be assigned a Vt that falls
`within one of four different voltage ranges of 200 mV, each
`being used to represent a data state corresponding to a bit
`pattern comprised of two bits. Typically, a dead space (which
`is sometimes referred to as a margin) of 0.2V to 0.4V is
`maintained between each range to keep the Vit distributions
`from overlapping. If the voltage stored on the cell is within the
`first of the four Vit distributions, the cell in this case is storing
`a logical 11 state and is typically considered the erased State
`of the cell. If the voltage is within the second of the four Vt
`distributions, the cell in this case is storing a logical 10 state.
`A voltage in the third distribution of the four Vit distributions
`would indicate that the cell in this case is storing a logical '00'
`state. Finally, a Vt residing in the fourth Vt distribution indi
`cates that a logical '01 state is stored in the cell.
`0008. There are advantages and disadvantages associated
`with using SLC or MLC memory. MLC memory is generally
`considered more cost effective in regards to memory density
`as MLC memory can, for example, store multiple bits of data
`in a single memory cell as opposed to SLC memory which is
`conventionally used to store one bit of data per cell. However,
`conventional SLC memory can be written to many (e.g., by an
`order magnitude) more times than conventional MLC
`memory. For example, a characteristic of conventional MLC
`memory is that after data has been erased and re-written about
`10,000 times the memory may become subject to significant
`read and write errors. Conventional SLC memory on the other
`hand typically may be erased and re-written about 100,000
`times before the reliability of the data begins to deteriorate.
`These density and performance characteristics also apply
`between different types of MLC arrays. MLC devices with
`four and eight levels exist today, while denser memories are
`being researched. Whilean MLC with more levels would be
`more efficient (higher density) than an MLC with less levels
`(lower density), these higher density devices may have per
`formance penalties over the lower density devices. The case
`of a device built with SLC (two level) and MLC (more than
`two level) can be generalized as a device with multiple
`memory arrays, each with its own density and performance
`trade-offs. An example is a device built with an array of MLC
`(four level) and an array of MLC (eight level). There could
`even be more than two arrays of memories, such as SLC,
`MLC (four level) and MLC (eight level). A common naming
`convention is to refer to SLC memory as MLC (two level)
`memory as SLC memory utilizes two levels in order to store
`one bit of data as represented by a 0 or a 1, for example. MLC
`memory configured to store two bits of data can be repre
`sented by MLC (four level), three bits of data by MLC (eight
`level), etc. An MLC (four level) memory cell is typically
`referred to as a lower density memory cell than an MLC (eight
`level) memory due to the lower number of bits stored per
`memory cell, for example. SLC (e.g., MLC (two level)) is
`typically referred to as a lower density memory than MLC
`(four level) memory and so on.
`0009 For the reasons stated above, and for other reasons
`stated below which will become apparent to those skilled in
`the art upon reading and understanding the present specifica
`tion, there is a need in the art for hybrid memory devices that
`are adapted to manage the utilization of memory of different
`densities, such as SLC and MLC memory, to take advantage
`of preferred operating characteristics associated with each
`type of memory.
`BRIEF DESCRIPTION OF THE DRAWINGS
`0010 FIG. 1 is a functional block diagram of a memory
`module according to an embodiment of the present disclo
`SUC.
`
`Micron Ex. 1052, p. 8
`Micron v. Vervain
`IPR2021-01550
`
`

`

`US 2009/03 00269 A1
`
`Dec. 3, 2009
`
`FIG. 2 is a flow chart illustrating multiple operations
`0011
`according to various embodiments of the present disclosure.
`0012 FIG. 3 illustrates one storage configuration of a
`memory device according to an embodiment of the present
`disclosure.
`0013 FIG. 4 illustrates a move operation of data according
`to an embodiment of the present disclosure.
`0014 FIG.5 illustrates a write operation of data according
`to an embodiment of the present disclosure.
`0015 FIG. 6 is a functional block diagram of an electronic
`system having at least one memory device according to an
`embodiment of the present disclosure.
`
`DETAILED DESCRIPTION
`0016. In the following detailed description of the embodi
`ments, reference is made to the accompanying drawings that
`form a part hereof. In the drawings, like numerals describe
`Substantially similar components throughout the several
`views. These embodiments are described in sufficient detail
`to enable those skilled in the art to practice the invention.
`Other embodiments may be utilized and structural, logical,
`and electrical changes may be made without departing from
`the scope of the present invention. The following detailed
`description is, therefore, not to be taken in a limiting sense,
`and the scope of the present disclosure is defined only by the
`appended claims, along with the full scope of equivalents to
`which such claims are entitled.
`0017. As discussed above, conventional SLC and MLC
`memory have both positive and negative attributes associated
`with them. SLC memory allows for faster write operations
`and can withstand far more write operations before reliability
`of the memory cells begin to degrade as compared to MLC
`memory. However, SLC memory is not as efficient as MLC
`memory in that MLC memory can store multiple bits of data
`on each memory cell whereas SLC is used to store only a
`single bit per cell. Various embodiments of the present dis
`closure store data that is frequently updated in SLC memory
`and store data that is updatedless frequently in MLC memory.
`This can be used to enhance the efficiency and reliability of
`memory devices. Although some embodiments are disclosed
`with reference to utilizing SLC and MLC memory, the vari
`ous embodiments are not so limited. For example, one
`embodiment may utilize SLC memory, sometimes referred to
`as MLC (two level) memory, and MLC (four level) memory.
`Another embodiment may utilize MLC (four level) and MLC
`(eight level) memory. Still other embodiments can utilize
`three or more memory arrays such as SLC, MLC (four level)
`and MLC (eight level) memory in the same memory device,
`for example. Other combinations are possible according to
`the various embodiments of the present disclosure. Thus the
`embodiments can utilize a combination of different level
`(e.g., density) memory in a memory device.
`0018 Data in a non-volatile memory device can be
`accessed throughan abstraction called a logical blockaddress
`(LBA) that does not define where the data physically resides
`in the device. The device can also have physical block
`addresses (PBA) that define a physical location, but does not
`define or imply what data is kept in this location. In a mag
`netic disk device, a physical block address translates to a
`specific cylinder, head, and sector. In a Solid State non-volatile
`memory device, the physical blockaddress typically refers to
`a specific memory block address in a specific memory array.
`Logical block addresses and physical block addresses are
`well known to those skilled in the art. Memory devices main
`
`tain look up tables which map LBAs to their assigned PBAs.
`Conventional memory devices that have both SLC and MLC
`memory store data in either SLC memory or MLC memory.
`The data does not move between the SLC and MLC memory.
`This is in contrast with various embodiments of the present
`disclosure which cause the data stored in the memory device
`to move between SLC and MLC, such as based on the usage
`(e.g., number of write operations performed) of a given LBA.
`This usage is determined (e.g., tracked) and maintained for
`the LBAs of the memory device according to various embodi
`ments of the present disclosure. Various embodiments of the
`present disclosure might also predict the usage for a given
`LBA and assign it to SLC or MLC memory accordingly. For
`example many file systems keep a data structure which is used
`to reference files to LBAs, such as a File Allocation Table
`(FAT), LBAs associated with such structures are likely to be
`subject to write operations on every file write operation. Thus,
`LBAs associated with the FAT could initially be assigned to
`SLC memory instead of MLC memory. Other embodiments
`adjust the location of a given LBA in SLC or MLC memory by
`acting in response to the actual tracked usage of each LBA.
`According to some embodiments of the present disclosure, an
`LBA may move between the SLC and MLC memory based on
`the actual usage of the LBA during operation of the memory
`device regardless of how the LBA was initially assigned.
`0019 FIG. 1 illustrates a memory device according to an
`embodiment of the present disclosure. The memory device in
`FIG. 1 has been simplified to focus on various embodiments
`of the present disclosure. The memory device 100 comprises
`a controller 170 for controlling and managing the operations
`of the memory device 100 according to various embodiments
`of the present disclosure including managing the assignment
`of LBAS to either SLC or MLC (or between different density
`MLC) memory. The controller 170 can take the form of
`discrete logic or a state machine, for example. The controller
`170 also incorporates various means for communicating with
`a host, such as a processor 110. For example, the controller
`170 may incorporate a Universal Serial Bus (USB), SATA,
`PATA, ATA8-ACS, SD, MMC, Compact Flash, Memory
`Stick, IEEE 1394 or BA-NAND interface as are well known
`in the art. Physical wear leveling of the SLC and MLC
`memory can also be handled by the controller 170.
`0020. The memory device 100 also comprises an array of
`SLC memory 132 and an array of MLC memory 134. In some
`embodiments, the SLC 132 and MLC 134 memory may be
`separate flash memory chips while in others the SLC and
`MLC memory may be contained on one chip. The memory
`arrays 132 and 134 may also be comprised of different density
`MLC memory. Array 132 might be MLC (four level) and
`array 134 might be MLC (eight level), for example. The SLC
`132 and MLC 134 memory illustrated in FIG.1 may each be
`further comprised of multiple banks and blocks of memory.
`Each of the SLC 132 and MLC 134 memory blocks shown in
`FIG. 1 can be comprised of multiple memory chips. The
`amount (e.g. capacity) of SLC and MLC memory of the
`memory device 100 may or may not be equal. In some
`embodiments (e.g. a single chip comprising SLC and MLC
`memory) the size of the SLC array and MLC array may be
`assignable depending on the desired amount of SLC vs. MLC
`memory for a given application. In another embodiment
`according to the present disclosure, the memory device of
`FIG.1 may be a two-way interleaved memory device having
`two SLC chips and two MLC chips. Other quantities of SLC
`
`Micron Ex. 1052, p. 9
`Micron v. Vervain
`IPR2021-01550
`
`

`

`US 2009/03 00269 A1
`
`Dec. 3, 2009
`
`and MLC chips are also possible according to various
`embodiments of the present disclosure.
`0021. The memory device of FIG. 1 also includes a usage
`table 136. The usage table is utilized by the controller 170 to
`store usage data (e.g. write operations performed) for the
`various LBAs of the memory device 100. For example, each
`time a write operation is performed on an LBA, the associated
`usage data for that LBA will updated. The usage table 136
`may also store usage information (e.g., a time stamp) indicat
`ing when a given LBA was last written to as opposed to the
`number of times it has been written to. For example, LBAs
`may be mapped based on how much time has elapsed (e.g., a
`minute, a day, a month, etc.) since a particular LBA was last
`written to instead of a cumulative number of times it has been
`written to. In addition to assigning a time stamp to an LBA,
`LBAS may instead be assigned to a time group. LBAS
`assigned to a first time group may represent LBAS used in the
`current month whereas LBAS assigned to a second time group
`may represent LBAS used last month, for example. According
`to various embodiments, usage might also comprise tracking
`which LBAs are utilized at power up of the memory device or
`during a particular time frame following power up. The par
`ticular time frame may also follow a reset operation, for
`example. These LBAS may then be assigned to lower density
`(e.g., SLC) memory which can typically be accessed faster
`than higher density (e.g., MLC (four level)) memory. This can
`improve start up performance such as reducing access time
`during a bootload operation, for example. Usage data stored
`in the usage table 136 is not limited to usage of individual
`LBAS. Usage data may also be stored pertaining to use of
`multiple or ranges of LBAS. The usage table can also be
`cleared if desired. For example, a host 110 connected to the
`memory device 100 might send a particular command
`instructing that all or part of the usage table 136 be cleared. An
`example of a usage table is shown in block 136 of FIG. 1.
`0022. The usage table 136 may be stored in a standalone
`component such as an integrated circuit device having one or
`both of a volatile and non-volatile memory portion. For
`embodiments having both volatile and non-volatile memory,
`the Volatile memory can maintain the current usage table
`during operation of the memory device. The usage table could
`then periodically be copied from the volatile memory to the
`non-volatile memory. The current usage table 136 can also be
`loaded into the volatile memory at power up and transferred
`back to non-volatile memory during power down of the
`memory device. Other embodiments allow for the usage table
`136 data to be stored in the memory array 132/134 of the
`memory device 100. For example, the usage table data may be
`stored along with (e.g. appended to) the data associated with
`the LBA in the memory device. In other embodiments, the
`usage table may be stored in a dedicated location of either the
`SLC 132 or MLC 134 memory.
`0023 FIG. 1 also illustrates the memory device 100
`coupled to a processor 110. The memory device 100 is
`coupled to the processor 110 by way of an interface 174,
`which may comprise multiple busses and signals. For
`example, control signals generated by the processor can be
`coupled to the memory device by a control bus 172. Addi
`tionally, an address bus 142 and a data bus 162 are also shown
`in the figure. The interface 174 may conform to one of the
`interface protocols discussed above (e.g. USB, SATA, PATA,
`et al.).
`0024 FIG. 2 illustrates a flow chart of some of the various
`activities performed by the controller 170 in implementing
`
`embodiments of the present disclosure. In some embodi
`ments of the present disclosure, the controller of the memory
`device determines where an LBA 200 is to be assigned in the
`memory device 100. As discussed above, the FAT table is
`likely to be frequently used. Thus, according to one embodi
`ment of the present disclosure, the controller 170 of the
`memory device 100 may assign LBAs associated with the
`FAT to SLC (e.g., MLC (two level) memory 214. The FAT
`LBAS according to this embodiment may also be permanently
`assigned (e.g. pinned) to SLC memory. In other embodi
`ments, the controller may assign the FAT LEBAs to MLC
`memory 206 and the controller 170 can move the FAT tables
`based on usage. Thus, according to one embodiment, all
`LBAs may be initially written to MLC memory 206. In other
`embodiments, all LBAs may be initially assigned to SLC
`memory 214. Still other embodiments may assign all LBAs
`having a write operation to be performed thereon to SLC
`memory. In these embodiments, should the LBA currently
`being written to be already assigned to MLC memory, the
`controller 170 can determine if the LBA being written to
`should ultimately be assigned to SLC or MLC memory.
`0025. The controller also tracks and maintains (e.g.,
`updates) 208/216 the usage table data for LBAs of the
`memory device during operation. If the usage of an LBA
`currently assigned to MLC memory exceeds Some threshold
`value 210, the controller will attempt to move the data asso
`ciated with the LBA (and reassign the LBA to the location in)
`to SLC memory 212. In one embodiment, this threshold value
`may be 1000 write operations performed on a given LBA. The
`embodiments however are not limited to a single threshold
`value. For example, the threshold value may be some fraction
`of the total write operations performed on the memory 212. If
`the usage for all the LBAs assigned to MLC memory remain
`less than the threshold value, then those LBAs will continue
`to be assigned to the MLC memory.
`0026. According to one embodiment, each time an LBA is
`assigned to SLC memory, either from the controller 214 or
`because an LBA assigned to MLC memory has exceeded
`Some threshold value 212, a determination is made regarding
`whether a sufficient number of spare locations remain in the
`SLC memory 218. Spare locations are desirable to allow for
`data handling and housekeeping functions to be performed on
`the memory device. If sufficient spares will exist in the SLC
`after the current write operation to SLC takes place, no further
`action by the controller is necessary and the LBA is assigned
`to the SLC memory. If however, the current assignment of an
`LBA to SLC memory will result in too few remaining spare
`locations in SLC memory, the controller will perform data
`management functions according to various embodiments of
`the present disclosure in order to preserve a minimum number
`of spare locations in the SLC memory. For example, the
`controller will review the usage data for each LBA currently
`assigned to SLC. Whichever LBA currently assigned to SLC
`memory has the least usage associated with it, the data asso
`ciated with that LBA will be moved to MLC memory 220
`(e.g., the next higher density memory.) In embodiments uti
`lizing a time stamp to represent usage for the LBAS, the least
`recently used LBA assigned to SLC memory would be moved
`to MLC memory. According to one or more embodiments,
`data may be moved to the more dense memory (e.g., from
`SLC to MLC) if an LBA has not experienced a write operation
`over a particular period of time. For example, data may be
`moved from MLC (four level) to MLC (eight level) memory
`if the time stamp of the corresponding LBA indicates that the
`
`Micron Ex. 1052, p. 10
`Micron v. Vervain
`IPR2021-01550
`
`

`

`US 2009/03 00269 A1
`
`Dec. 3, 2009
`
`LBA has not been written to in more than a month. Other
`durations are possible according to various embodiments of
`the disclosure.
`0027. By performing the move operation of the data asso
`ciated with the least used LBA currently assigned to SLC
`memory to MLC memory 220, a sufficient amount of spare
`locations should remain in SLC memory after the current
`LBA write operation to SLC memory is completed. The con
`troller, according to Some embodiments may also prevent the
`write operation to SLC memory from proceeding if the usage
`of the least used LBA currently assigned to SLC memory
`exceeds some amount. In this situation, the LBA prevented
`from being assigned to SLC memory might be assigned to
`MLC memory instead. When data associated with an LBA is
`moved from SLC to MLC 220, or vice versa 212, the usage
`data associated with that LBA is not incremented, at least
`according to one embodiment of the present disclosure.
`0028. The controller 170 can also perform physical wear
`leveling operations on the memory device while the move
`ment of data associated with LBAs either within or between
`MLC and SLC memory is occurring according to various
`embodiments of the present disclosure. For example, an LBA
`assigned to MLC memory might be re-assigned to another
`PBA also located in MLC memory. Thus, the LBA remains in
`the desired area of memory (e.g. MLC or SLC) without per
`forming all of the write operations on the same physical
`memory cells of the memory area. Similar physical wear
`leveling is also performed on the SLC area of memory.
`0029 FIGS. 3-5 illustrates a data move and write opera
`tion according to an embodiment of the present disclosure.
`FIG. 3 illustrates a two-way interleaved embodiment of a
`memory device 300. This configuration allows for large
`pieces of data to be shared by two memory chips. However,
`memory devices according to the present disclosure are not
`limited to two-way interleaved configurations. The memory
`device 300 of FIG. 3 is shown having a controller 302, a SLC
`memory 306, an MLC memory 308 and a data bus coupling
`the SLC and MLC memory to the controller 304. In the
`embodiment shown in FIG. 3, the SLC memory 306 com
`prises two flash SLC memory integrated circuits (e.g. chips)
`310/312. The MLC memory 308 of the memory device 300
`shown in FIG. 3 comprises two flash MLC memory chips
`314/316. Other embodiments have different numbers of SLC
`and MLC chips, for example. The memory device shown in
`FIG.3 has been simplified to focus on the embodiments of the
`present disclosure. Other components may be included in the
`memory device 300 as are known to those skilled in the art.
`0030 FIG. 3 shows locations 322 in SLC memory 306
`along with their assigned LBAS and respective usage data. As
`discussed with respect to FIG. 1, the usage data may be stored
`in a location associated with the LBA or may be stored in a
`different location 136. The embodiment of FIG. 3 illustrates
`an embodiment wherein four LBAs have been previously
`assigned to SLC memory. Other embodiments may only have
`LBAS assigned to MLC memory at any given time. In the
`present embodiment shown in FIG. 3, the minimum number
`of spare SLC locations is two. However, embodiments of the
`present disclosure are not limited to maintaining two spare
`locations.
`0031
`FIG. 4 illustrates an operation in which an LBA is to
`be assigned to SLC memory as is shown in block 214 of FIG.
`2. In this example, a move operation is performed in order to
`make room for the new data and so as to maintain the required
`two spare locations in the SLC memory 306. Again referenc
`
`ing FIG. 2, the data associated with the LBA having the
`lowest usage is moved 220 to MLC memory in order to
`maintain the minimum number of spare locations in SLC
`memory 306. In this example, the data associated with
`LBA-2 (having a USAGE=1), which is assigned to location
`322 is moved 418 to MLC memory 308. FIG. 5 illustrates a
`write operation 520 on LBA-7, wherein the associated data is
`written to the SLC memory 306. The write operation 520 and
`the move operation 418 may be performed in any order. The
`embodiments are not so limited that the move operation 418
`must occur prior to the write operation 520. As illustrated in
`FIG. 5, one of the two required spare memory locations has
`effectively been relocated in the SLC memory. However,
`upon the conclusion of the write operation 520, two required
`spare locations are shown to still exist in the SLC memory
`306. It should be noted that many more memory locations and
`LBAs are possible according to various embodiments of the
`present disclosure than are shown in FIGS. 3-5. In addition,
`move operations according to various embodiments may also
`involve moving a number of LBAs along with the LBA whose
`usage was used to determine a move operation was desired.
`For example, according to Some embodiments, if any
`memory segment of the memory has an architecture that is
`most effectively used with accesses of multiples of logical
`blocks (e.g. 4LBAs, 8 LBAs, etc.), the various embodiments
`may move groups of LBAs of these various sizes even if LBA
`usage is tracked by single LBAS. For example, if it has been
`determined that LBA=1 is to be moved, LBAS 2, 3, and 4 may
`also be moved during the same operation according to various
`embodiments of the present disclosure.
`0032 Referring again to FIG. 1, embodiments according
`to the present disclosure can incorporate a memory device
`100 having a standard interface 174 to couple the memory
`device with a host, such as processor 110. There are various
`types of standard interfaces such as those adapted for hard
`disk drives (HDDs.) For example, SATA and PATA are com
`mon HDD interfaces. Additional standard non-HDD specific
`interfaces also exist in the art such as USB and SD interfaces.
`Embodiments of the present disclosure employing these and
`other standard interfaces and protocols can be used