United States Patent (19)
`Harari et al.
`
`54 MULTI-STATE FLASH EEPROM SYSTEM
`WITH CACHE MEMORY
`
`75 Inventors: Eliyahou Harari, Los Gatos; Robert
`D. Norman, San Jose; Sanjay
`Mehrotra. Milpitas, all of Calif
`s
`plaS,
`73 ASSignee: SanDisk Corporation, Sunnyvale,
`Calif.
`
`21 Appl. No.: 08/931,133
`22 Filed:
`Sep. 16, 1997
`Related U.S. Application Data
`
`63
`63 Stage of application No. 08/249,049, May 25, 1994,
`at. No. 5,671,229, which is a continuation of application
`No. 07963,837. 6c."26, 1993, Abandoned. Which is a
`division of application No. 07/337,566, Apr. 13, 1989,
`abandoned.
`(51) Int. Cl." ...................................................... G06F 11/00
`52 U.S. Cl. .......................... 371/10.2: 711/136; 365/200
`58 Field of Search ........................... 371/10.2: 365/200,
`365/201; 395/182.04; 711/136
`
`56)
`
`References Cited
`U.S. PATENT DOCUMENTS
`1/1972 Harper.
`3,633,175
`4,051,354 9/1977 Choate.
`4,093.985 6/1978 Das.
`4,210,959
`7/1980 Wozniak.
`4,250,570 2/1981 Tsang et al..
`4,272,830
`6/1981 Moench.
`4,279,024
`7/1981 Schrenk.
`4.2s1398 7/1981 McKenny et al..
`4,287,570 9/1981 Stark.
`4,295.205 10/1981 Kunstadt.
`4,354.253 10/1982 Naden.
`(List continued on next page.)
`FOREIGN PATENT DOCUMENTS
`O557723 1/1987 Australi
`O086886 8/1983 European Pat. Off..
`0243503B1 7/1987 European Pat. Off..
`0300264B1 10/1989 European Pat. Off..
`
`Sala
`
`USOO5.936971A
`Patent Number:
`11
`(45) Date of Patent:
`
`5,936,971
`Aug. 10, 1999
`
`58-215794 12/1983 Japan.
`58-215795 12/1983 Japan.
`59-45695 3/1984 Japan.
`59-162695 9/1984 Japan.
`60-076097 4/1985 Japan.
`60-212900 10/1985 Japan.
`A60178564 2/1986 Japan.
`61-96598 5/1986 Japan.
`62-283496 12/1987 Japan.
`62-283497 12/1987 Japan.
`63-183700 7/1988 Japan.
`A01054543 3/1989 Japan.
`2136992 9/1984 United Kingdom.
`WO84.00628 2/1984 WIPO.
`OTHER PUBLICATIONS
`Lucero et al., “A 16 kbit Smart 5 V-only EEPROM with
`Redundancy," IEEE Journal of Solid State Circuits, vol.
`SC-18, No.5, pp. 539-543 (Oct. 1983).
`Torelli et al., “An improved method for programming a
`word-erasable EEPROM,” Alta Frequenza, Vol. 52, No. 6,
`pp. 487-494 (Nov.-Dec. 1983).
`(List continued on next page.)
`Primary Examiner Phung M. Chung
`Attorney, Agent, or Firm Majestic, Parsons, Siebert &
`HSue
`ABSTRACT
`57
`A system of Flash EEprom memory chips with controlling
`circuits serves as non-volatile memory Such as that provided
`by magnetic disk drives. Improvements include Selective
`multiple Sector erase, in which any combinations of Flash
`Sectors may be erased together. Selective Sectors among the
`Selected combination may also be de-Selected during the
`erase operation. Another improvement is the ability to remap
`and replace defective cells with Substitute cells. The remap
`ping is performed automatically as Soon as a defective cell
`is detected. When the number of defects in a Flash sector
`becomes large, the whole Sector is remapped. Yet another
`improvement is the use of a write cache to reduce the
`number of writes to the Flash EEprom memory, thereby
`minimizing the StreSS to the device from undergoing too
`many write/erase cycling.
`
`26 Claims, 5 Drawing Sheets
`
`Tolv
`
`705
`
`CACHE
`BUFFER
`
`
`
`33
`
`
`
`
`
`DATA
`
`HOST
`
`ADDR INTERFACE re
`re FILEAG
`TMN
`ANDTIME
`CONTRO
`SAMP
`
`MEMORY
`ARRAY
`
`
`
`TIMERS
`
`Micron Ex. 1049, p. 1
`Micron v. Vervain
`IPR2021-01550
`
`

`

`5,936,971
`Page 2
`
`U.S. PATENT DOCUMENTS
`
`4,355,376
`4,380,066
`4,405,952
`4,422,161
`4,449,205
`4,450.559
`4,456,971
`4,463,450
`4,466,059
`4,479.214
`4,493.075
`4,498,146
`4,514,830
`4,527,251
`4,530,055
`4,586,163
`4,601,031
`4,612,640
`4,616,311
`4,617,624
`4,617,651
`4,642,759
`4,653,023
`4,654,847
`4,672,240
`4,718,041
`4,733,394
`4,746,998
`4,785,425
`4,794,568
`4,796,233
`4,800,520
`4,805,109
`4,821,240
`4,847,808
`4,882,642
`4,887,234
`4,896.262
`4,914,529
`4,916,605
`4,920,478
`4,920,518
`4,924,331
`4,933,906
`4.942.556
`4,945,535
`4,949.240
`4,953,122
`5,043,940
`5,051,887
`5,053,990
`5,070,474
`5,095,344
`5,136,546
`5,163,021
`5,172,338
`
`10/1982
`4/1983
`9/1983
`12/1983
`5/1984
`5/1984
`6/1984
`7/1984
`8/1984
`10/1984
`1/1985
`2/1985
`4/1985
`7/1985
`7/1985
`4/1986
`7/1986
`9/1986
`10/1986
`10/1986
`10/1986
`2/1987
`3/1987
`3/1987
`6/1987
`1/1988
`3/1988
`5/1988
`11/1988
`12/1988
`1/1989
`1/1989
`2/1989
`4/1989
`7/1989
`11/1989
`12/1989
`1/1990
`4/1990
`4/1990
`4/1990
`4/1990
`5/1990
`6/1990
`7/1990
`7/1990
`8/1990
`8/1990
`8/1991
`9/1991
`10/1991
`12/1991
`3/1992
`8/1992
`11/1992
`12/1992
`
`Gould.
`Spencer et al. .
`Slakmon.
`Kressel et al. .
`Hoffman.
`Bond et al. .
`Fukuda et al. .
`Haeusele.
`Bastian et al. .
`Ryan.
`Anderson et al. .
`Martinez.
`Hagiwara et al. .
`Nibby, Jr. et al..
`Hamstra et al. ........................ 711/136
`Koike.
`Walker et al. .
`Mehrotra et al. .
`Sato .
`Goodman.
`Ip et al. .
`Foster.
`Suzuki et al. .
`Dutton.
`Smith et al. .
`Baglee et al. .
`Burkhard.
`Robinson et al. .
`Lavelle.
`Lim et al. .
`Awaya et al. .
`Iijima.
`Kroll et al. .
`Nakamura et al. .
`Kobatake .
`Tayler et al. .
`Iijima.
`Wayama et al..
`Bonke .
`Beardsley et al. .
`Furuya et al. .
`Nakamura et al. .
`Robinson et al. .
`Terada et al. .
`Sasaki et al. .
`Hosotani et al. .
`Iijima.
`Williams.
`Harari.
`Berger et al. .
`Kreifels et al. .
`Tuma et al. .
`Harari.
`Fukuda et al. .
`Mehrotra et al. .
`Mehrotra et al. .
`
`5,226,168 7/1993 Kobayashi et al..
`5,297,148 3/1994 Harari et al..
`5,359,569 10/1994 Fujita et al. .
`5,430,859 7/1995 Norman et al..
`5,488,711
`1/1996 Hewitt et al..
`5,546,351
`8/1996 Tanaka et al..
`5,606,532 2/1997 Lambrache et al..
`5,671,229 9/1997 Harari et al..
`OTHER PUBLICATIONS
`Data Sheet: “27F256256K(32Kx8) CMOS Flash Memory.”
`Intel Corporation, pp. 1-24 (May 1988).
`Preliminary Data Sheet, “48F512 512K Flash EEPROM,”
`SEEO Technology, Incorporated, pp. 2-1 through 2-12
`(Oct. 1988).
`Advanced Data Sheet, “48FO10 1024K Flash EEPROM,
`SEEO Technology, Incorporated, pp. 2-13 thru 2-24 (Oct.
`1988).
`Lai, Robert S., Writing MS-DOS Device Drivers, The Waite
`Group, Inc., (Sep. 1987), pp. i-Xi and 235-319.
`Miller, “Semidisk Disk Emulator.” Interface Age, p. 102,
`Nov. 1982.
`Clewitt, “Bubble Memories as a Floppy Disk Replacement,”
`1978 MIDCON Technical Papers, vol. 2, pp. 1-7, Dec.
`1978.
`Hancock, “Architecting a CCD Replacement for the IBM
`2305 Fixed Head Disk Drive,” Digest of Papers, Eighteenth
`IEEE Computer Society International Conference, pp.
`182-184, 1979.
`Wilson, “1-Mbit flash memories seek their role in system
`design.” Computer Design, vol. 28, No. 5, pp. 30-32 (Mar.
`1989).
`Bleiker et al., “A Four-State EEPROMUsing Floating-Gate
`Memory Cells,” IEEE Journal of Solid State Circuits,
`SC–22 (1987) Jun., No. 3, New York, NY, USA.
`Intel Corporation, 27F256, 256K (32Kx8) CMOS Flash
`Memory, May 1988, pp. 1-21.
`Krick, “Three-State MNOS FET Memory Array,” IBM
`Technical Disclosure Bulletin, vol. 18, No. 12, May 1976,
`pp. 4192–4.193.
`Alberts C.S. et al., “Multi-Bit Storage FETEAROM Cell,”
`IBM Technical Disclosure Bulletin, vol. 24, No. 74, Dec.
`1981, pp. 3311-3314.
`Horiguchi et al., “An Experimental Large-Capacity Semi
`conductor File Memory Using 16-Levels Cell Storage.”
`IEEE Journal of Solid State Circuits, vol. 23, No. 1, Feb.
`1988, pp. 27–33.
`Furuyama, et al., “An Experimental 2-Bit/Cell Storage
`Dram for Macro Cell or Memory-on-logic Application,”
`Jan. 1988 IEEE, pp. 4.4.1 to 4.4.4.
`Stark, “Two Bits Per Cell ROM,” Jan. 1981 IEEE Catalog
`No. 81-CH1626–1, pp. 201-212.
`
`Micron Ex. 1049, p. 2
`Micron v. Vervain
`IPR2021-01550
`
`

`

`U.S. Patent
`
`Aug. 10, 1999
`
`Sheet 1 of 5
`
`5,936,971
`
`
`
`CONTROLLER
`
`EEPROM
`ARRAY
`
`2
`MICRO
`PROCESSOR
`
`
`
`
`
`25
`
`/0
`DEVICES)
`
`FIG.A.
`
`
`
`SEs DATA
`f
`BUSAACONTROLLER
`CHIP
`39
`
`EEPROM ARRAY
`
`4.
`O
`
`55
`
`
`
`LOGIC
`AND
`REGISTERS
`
`
`
`SYSTEM
`CONTROL LINES
`
`4.
`
`TO OTHER
`EEPROM
`ARRAYS
`
`EEPROM
`CHIP
`
`
`
`
`
`
`
`
`
`
`
`CHIP
`SELECT
`
`CHIP
`SELECT
`
`Micron Ex. 1049, p. 3
`Micron v. Vervain
`IPR2021-01550
`
`

`

`U.S. Patent
`
`Aug. 10, 1999
`
`Sheet 2 of 5
`
`5,936,971
`
`3.
`
`CONTROLLER
`
`L-L
`Aaaay NYaYaNYNY
`
`FLASH MEMORY CHIPS 20
`2
`23
`
`YNSNYANNNNNy
`
`203
`
`25
`
`27s. 2. /
`
`SET ERASE EN
`
`22
`
`
`
`NYSSYNNYSaav
`
`
`
`SECTORSO
`BE ERASED
`
`23
`
`233
`
`
`
`REG
`5. Fiel
`
`2
`
`SECTOR
`
`see
`
`SECTOR
`
`SECTOR
`
`23
`
`SECTOR
`
`SECTOR
`
`SECTOR
`
`
`
`
`
`
`
`
`
`SERIAL
`INTERFACE
`
`
`
`
`
`
`
`
`
`We (ERASE WOLAGE)
`
`Micron Ex. 1049, p. 4
`Micron v. Vervain
`IPR2021-01550
`
`

`

`U.S. Patent
`
`Aug. 10, 1999
`
`Sheet 3 of 5
`
`5,936,971
`
`()
`
`POINT TO SECTOR TO BE ERASED
`
`(2)
`
`(3)
`
`(4)
`
`(5)
`
`(6)
`
`(7)
`
`(8)
`
`(9)
`
`(O)
`
`FIG-4.
`
`()
`
`TAG SECTOR POINTED TO BY
`SETTING THE ASSOCATED
`ERASE ENABLE REGISTER
`
`
`
`
`
`S THERE
`MORE SECTOR TO BE
`ERASED2
`
`NO
`
`NTAE ERASE SEQUENCE WITH
`A GLOBAL ENABLE ERASE COMMAND
`
`APPLY A PULSE OF ERASE WOTAGE
`ONLY TO THE TAGGED SECTORS
`
`READ AND VERIFY THAT EACH
`SECTOR IS IN ERASEO STATE
`
`SHER
`ANY SECTOR
`ERFED
`
`
`
`POINT TO SECTOR TO
`BE REMOVED FROM ERASE
`
`UNTAG SECTOR POINTED TO
`BY CLEARING THE ASSOCATED
`ERASE ENABE REGISTER
`
`
`
`
`
`
`
`ARE ALL
`SECTORS
`ERIFIED
`YES
`END ERASE SEQUENCE BY
`WTHDRAWINGENABLE ERASE COMMAND
`
`Micron Ex. 1049, p. 5
`Micron v. Vervain
`IPR2021-01550
`
`

`

`U.S. Patent
`
`Aug. 10, 1999
`
`Sheet 4 of 5
`
`5,936,971
`
`
`
`
`
`SECTOR PARTITION
`FIG-5.
`
`TO v
`
`05
`7
`
`CACHE
`BUFFER
`
`
`
`
`
`FLASH
`MEMORY
`ARRAY
`
`TIMERS
`
`FIG-8.
`
`Micron Ex. 1049, p. 6
`Micron v. Vervain
`IPR2021-01550
`
`

`

`U.S. Patent
`
`Aug. 10, 1999
`
`
`
`
`
`
`
`
`
`
`
`it
`
`COMMAND
`SEQUENCER
`
`ADDRESS
`GENERATOR
`
`Sheet 5 of 5
`5,936,971
`"CONTROLLER MEMORY ARA
`
`se--
`
`33
`
`READ DATA PATH CONTROL
`FIG.6.
`
`
`
`Jerse of
`COMPARATOR HEA;
`HEADER COMPARE
`ALTERNATE
`DEFECTS (SPARES)
`
`WRITE DAIA PATH CONTROL
`FIG-7.
`
`Micron Ex. 1049, p. 7
`Micron v. Vervain
`IPR2021-01550
`
`

`

`1
`MULTI-STATE FLASH EEPROM SYSTEM
`WITH CACHE MEMORY
`
`CROSS-REFERENCE TO RELATED
`APPLICATIONS
`This is a continuation of application Ser. No. 08/249,049,
`filed May 25, 1994, now U.S. Pat. No. 5,671,229, which is
`a continuation of application Ser. No. 07/963,837, filed Oct.
`20, 1992, now abandoned, which in turn is a division of
`application Ser. No. 07/337,566, filed Apr. 13, 1989, now
`abandoned.
`
`BACKGROUND OF THE INVENTION
`This invention relates generally to Semiconductor electri
`cally erasable programmable read only memories (EEprom),
`and Specifically to a System of integrated circuit Flash
`EEprom chips.
`Computer Systems typically use magnetic disk drives for
`mass Storage of data. However, disk drives are disadvanta
`geous in that they are bulky and in their requirement for high
`precision moving mechanical parts. Consequently they are
`not rugged and are prone to reliability problems, as well as
`consuming Significant amounts of power. Solid State
`memory devices such as DRAM's and SRAM's do not
`Suffer from these disadvantages. However, they are much
`more expensive, and require constant power to maintain
`their memory (volatile). Consequently, they are typically
`used as temporary Storage.
`EEprom's and Flash EEprom's are also solid state
`memory devices. Moreover, they are nonvolatile, and retain
`their memory even after power is shut down. However,
`conventional Flash EEprom's have a limited lifetime in
`terms of the number of write (or program)/erase cycles they
`can endure. Typically the devices are rendered unreliable
`after 10° to 10 write/erase cycles. Traditionally, they are
`typically used in applications where Semi-permanent Storage
`of data or program is required but with a limited need for
`reprogramming.
`Accordingly, it is an object of the present invention to
`provide a Flash EEprom memory system with enhanced
`performance and which remains reliable after enduring a
`large number of write/erase cycles.
`It is another object of the present invention to provide an
`improved Flash EEprom System which can Serve as non
`Volatile memory in a computer System.
`It is another object of the present invention to provide an
`improved Flash EEprom System that can replace magnetic
`disk Storage devices in computer Systems.
`It is another object of the present invention to provide a
`Flash EEprom System with improved erase operation.
`It is another object of the present invention to provide a
`Flash EEprom system with improved error correction.
`It is yet another object of the present invention to provide
`a Flash EEprom with improved write operation that mini
`mizes stress to the Flash EEprom device.
`It is still another object of the present invention to provide
`a Flash EEprom System with enhanced write operation.
`SUMMARY OF THE INVENTION
`These and additional objects are accomplished by
`improvements in the architecture of a System of EEprom
`chips, and the circuits and techniques therein.
`According to one aspect of the present invention, an array
`of Flash EEprom cells on a chip is organized into Sectors
`
`15
`
`25
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`5,936,971
`
`2
`Such that all cells within each Sector are erasable at once. A
`Flash EEprom memory System comprises one or more Flash
`EEprom chips under the control of a controller. The inven
`tion allows any combination of Sectors among the chips to
`be selected and then erased simultaneously. This is faster
`and more efficient than prior art Schemes where all the
`Sectors must be erased every time or only one Sector at a time
`can be erased. The invention further allows any combination
`of Sectors Selected for erase to be deselected and prevented
`from further erasing during the erase operation. This feature
`is important for Stopping those Sectors that are first to be
`erased correctly to the "erased State from Over erasing,
`thereby preventing unnecessary StreSS to the Flash EEprom
`device. The invention also allows a global de-select of all
`Sectors in the System So that no Sectors are Selected for erase.
`This global reset can quickly put the System back to its initial
`State ready for Selecting the next combination of Sectors for
`erase. Another feature of the invention is that the Selection
`is independent of the chip Select Signal which enables a
`particular chip for read or write operation. Therefore it is
`possible to perform an erase operation on Some of the Flash
`EEprom chips while read and write operations may be
`performed on other chips not involved in the erase operation.
`According to another aspect of the invention, improved
`error correction circuits and techniques are used to correct
`for errors arising from defective Flash EEprom memory
`cells. One feature of the invention allows defect mapping at
`cell level in which a defective cell is replaced by a substitute
`cell from the same Sector. The defect pointer which connects
`the address of the defective cell to that of the Substitute cell
`is Stored in a defect map. Every time the defective cell is
`accessed, its bad data is replaced by the good data from the
`Substitute cell.
`Another feature of the invention allows defect mapping at
`the sector level. When the number of defective cells in a
`Sector exceeds a predetermined number, the Sector contain
`ing the defective cells is replaced by a Substitute Sector.
`An important feature of the invention allows defective
`cells or defective Sectors to be remapped as Soon as they are
`detected thereby enabling error correction codes to
`adequately rectify the relatively few errors that may crop up
`in the System.
`According to yet another aspect of the present invention,
`a write cache is used to minimize the number of writes to the
`Flash EEprom memory. In this way the Flash EEprom
`memory will be Subject to fewer StreSS inducing write/erase
`cycles, thereby retarding its aging. The most active data files
`are written to the cache memory instead of the Flash
`EEprom memory. Only when the activity levels have
`reduced to a predetermined level are the data files written
`from the cache memory to the Flash EEprom memory.
`Another advantage of the invention is the increase in write
`throughput by Virtue of the faster cache memory.
`According to yet another aspect of the present invention,
`one or more printed circuit cards are provided which contain
`controller and EEprom circuit chips for use in a computer
`System memory for long term, non-volatile Storage, in place
`of a hard disk System, and which incorporate various of the
`other aspects of this invention alone and in combination.
`Additional objects, features, and advantages of the present
`invention will be understood from the following description
`of its preferred embodiments, which description should be
`taken in conjunction with the accompanying drawings.
`BRIEF DESCRIPTION OF THE DRAWINGS
`FIG. 1A is a general micrprocessor System including the
`Flash EEprom memory System of the present invention;
`
`Micron Ex. 1049, p. 8
`Micron v. Vervain
`IPR2021-01550
`
`

`

`5,936,971
`
`3
`FIG. 1B is Schematic block diagram illustrating a System
`including a number of Flash EEprom memory chips and a
`controller chip;
`FIG. 2 is a schematic illustration of a system of Flash
`EEprom chips, among which memory Sectors are Selected to
`be erased;
`FIG. 3A is a block circuit diagram in the controller for
`implementing Selective multiple Sector erase according to
`the preferred embodiment;
`FIG. 3B shows details of a typical register used to select
`a Sector for erase as shown in FIG. 2A,
`FIG. 4 is a flow diagram illustrating the erase Sequence of
`Selective multiple Sector erase,
`FIG. 5 is a Schematic illustration showing the partitioning
`of a Flash EEprom Sector into a data area and a Spare
`redundant area;
`FIG. 6 is a circuit block diagram illustrating the data path
`control during read operation using the defect mapping
`scheme of the preferred embodiment;
`FIG. 7 is a circuit block diagram illustrating the data path
`control during the write operation using the defect mapping
`scheme of the preferred embodiment;
`FIG. 8 is a block diagram illustrating the write cache
`circuit inside the controller.
`DESCRIPTION OF THE PREFERRED
`EMBODIMENTS
`
`15
`
`25
`
`40
`
`45
`
`4
`The EEprom array 33 includes a number of EEprom
`integrated circuit chips 43, 45, 47, etc. Each includes a
`respective chip select and enable line 49, 51 and 53 from
`interface circuits 40. The interface circuits 40 also act to
`interface between the serial data lines 35, 37 and a circuit 55.
`Memory location addresses and data being written into or
`read from the EEprom chips 43, 45, 47, etc. are communi
`cated from a bus 55, through logic and register circuits 57
`and thence by another bus 59 to each of the memory chips
`43, 45, 47 etc.
`The bulk storage memory 29 of FIGS. 1A and 1B can be
`implemented on a Single printed circuit card for moderate
`memory sizes. The various lines of the system buses 39 and
`41 of FIG. 1B are terminated in connecting pins of such a
`card for connection with the rest of the computer System
`through a connector. Also connected to the card and its
`components are various standard power Supply Voltages (not
`shown).
`For large amounts of memory, that which is conveniently
`provided by a single array 33 may not be enough. In Such a
`case, additional EEprom arrays can be connected to the
`serial data lines 35 and 37 of the controller chip 31, as
`indicated in FIG. 1B. This is preferably all done on a single
`printed circuit card but if Space is not Sufficient to do this,
`then one or more EEprom arrayS may be implemented on a
`Second printed circuit card that is physically mounted onto
`the first and connected to a common controller chip 31.
`Erase of Memory Structures
`In System designs that Store data in files or blocks the data
`will need to be periodically updated with revised or new
`information. It may also be desirable to overwrite Some no
`longer needed information, in order to accommodate addi
`tional information. In a Flash EEprom memory, the memory
`cells must first be erased before information is placed in
`them. That is, a write (or program) operation is always
`preceded by an erase operation.
`In conventional Flash erase memory devices, the erase
`operation is done in one of Several ways. For example, in
`Some devices such as the Intel corporation's model 27F-256
`CMOS Flash EEprom, the entire chip is erased at one time.
`If not all the information in the chip is to be erased, the
`information must first be temporarily Saved, and is usually
`written into another memory (typically RAM). The infor
`mation is then restored into the nonvolatile Flash erase
`memory by programming back into the device. This is very
`Slow and requires extra memory as holding Space.
`In other devices Such as Seeq Technology Incorporated's
`model 485 12 Flash EEprom chip, the memory is divided
`into blocks (or Sectors) that are each separately erasable, but
`only one at a time. By Selecting the desired Sector and going
`through the erase Sequence the designated area is erased.
`While, the need for temporary memory is reduced, erase in
`various areas of the memory Still requires a time consuming
`Sequential approach.
`In the present invention, the Flash EEprom memory is
`divided into Sectors where all cells within each Sector are
`erasable together. Each Sector can be addressed Separately
`and Selected for erase. One important feature is the ability to
`Select any combination of Sectors for erase together. This
`will allow for a much faster System erase than by doing each
`one independently as in prior art.
`FIG. 2 illustrates schematically selected multiple sectors
`for erase. A Flash EEprom System includes one or more
`Flash EEprom chips such as 201, 203, 205. They are in
`communication with a controller 31 through lines 209.
`Typically, the controller 31 is itself in communication with
`a microprocessor System (not shown). The memory in each
`
`EEprom System
`A computer System in which the various aspects of the
`present invention are incorporated is illustrated generally in
`FIG. 1A. A typical computer System architecture includes a
`microprocessor 21 connected to a System buS 23, along with
`random acceSS, main System memory 25, and at least one or
`more input-output devices 27, Such as a keyboard, monitor,
`modem, and the like. Another main computer System com
`35
`ponent that is connected to a typical computer System buS 23
`is a large amount of long-term, non-volatile memory 29.
`Typically, Such a memory is a disk drive with a capacity of
`tens of megabytes of data Storage. This data is retrieved into
`the System Volatile memory 25 for use in current processing,
`and can be easily Supplemented, changed or altered.
`One aspect of the present invention is the Substitution of
`a Specific type of Semiconductor memory System for the disk
`drive but without having to Sacrifice non-volatility, ease of
`erasing and rewriting data into the memory, Speed of access,
`low cost and reliability. This is accomplished by employing
`an array of electrically erasable programmable read only
`memories (EEprom's) integrated circuit chips. This type of
`memory has additional advantages of requiring less power to
`operate, and of being lighter in weight than a hard disk drive
`magnetic media memory, thereby being especially Suited for
`battery operated portable computers.
`The bulk storage memory 29 is constructed of a memory
`controller 31, connected to the computer System buS 23, and
`an array 33 of EEprom integrated circuit chips. Data and
`instructions are communicated from the controller 31 to the
`EEprom array 33 primarily over a serial data line 35.
`Similarly, data and Status Signals are communicated from the
`EEprom 33 to the controller 31 over serial data lines 37.
`Other control and status circuits between the controller 31
`and the EEprom array 33 are not shown in FIG. 1A.
`Referring to FIG. 1B, the controller 31 is preferably
`formed primarily on a single integrated circuit chip. It is
`connected to the system address and data bus 39, part of the
`System bus 33, as well as being connected to System control
`lines 41, which include interrupt, read, write and other usual
`computer System control lines.
`
`50
`
`55
`
`60
`
`65
`
`Micron Ex. 1049, p. 9
`Micron v. Vervain
`IPR2021-01550
`
`

`

`S
`Flash EEprom chip is partitioned into sectors where all
`memory cells within a Sector are erasable together. For
`example, each sector may have 512 byte (i.e. 512x8 cells)
`available to the user, and a chip may have 1024 Sectors. Each
`Sector is individually addressable, and may be Selected, Such
`as sectors 211, 213, 215, 217 in a multiple sector erase. As
`illustrated in FIG. 2, the selected sectors may be confined to
`one EEprom chip or be distributed among Several chips in a
`system. The sectors that were selected will all be erased
`together. This capability will allow the memory and System
`of the present invention to operate much faster than the prior
`art architectures.
`FIG. 3A illustrates a block diagram circuit 220 on a Flash
`EEprom chip (such as the chip 201 of FIG. 2) with which
`one or more SectorS Such as 211, 213 are selected (or
`deselected) for erase. Essentially, each Sector Such as 211,
`213 is Selected or tagged by Setting the State of an erase
`enable register Such as 221, 223 associated with the respec
`tive Sectors. The Selection and Subsequent erase operations
`are performed under the control of the controller 31 (see
`FIG. 2). The circuit 220 is in communication with the
`controller 31 through lines 209. Command information from
`the controller is captured in the circuit 220 by a command
`register 225 through a serial interface 227. It is then decoded
`by a command decoder 229 which outputs various control
`Signals. Similarly, address information is captured by an
`address register 231 and is decoded by an address decoder
`233.
`For example, in order to Select the Sector 211 for erase, the
`controller sends the address of the sector 211 to the circuit
`220. The address is decoded in line 235 and is used in
`combination with a set erase enable signal in bus 237 to set
`an output 239 of the register 221 to HIGH. This enables the
`Sector 211 in a Subsequent erase operation. Similarly, if the
`Sector 213 is also desired to be erased, its associated register
`223 may be set HIGH.
`FIG. 3B shows the structure of the register such as 221,
`223 in more detail. The erase enable register 221 is a
`SET/RESET latch. Its set input 241 is obtained from the set
`erase enable Signal in buS 237 gated by the address decode
`in line 235. Similarly, the reset input 243 is obtained from
`the clear erase enable Signal in buS 237 gated by the address
`decode in line 235. In this way, when the set erase enable
`Signal or the clear erase enable signal is issued to all the
`Sectors, the Signal is effective only on the Sector that is being
`addressed.
`After all Sectors intended for erase have been Selected, the
`controller then issues to the circuit 220, as well as all other
`chips in the System a global erase command in line 251
`along with the high voltage for erasing in line 209. The
`device will then erase all the sectors that have been selected
`(i.e. the sectors 211 and 213) at one time. In addition to
`erasing the desired Sectors within a chip, the architecture of
`the present System permits Selection of Sectors acroSS Vari
`ous chips for Simultaneous erase.
`FIGS. 4(1)–4(11) illustrate the algorithm used in conjunc
`tion with the circuit 220 of FIG. 3A. In FIG. 4(1), the
`controller will shift the address into the circuit 220 which is
`decoded in the line to the erase enable register associated
`with the sector that is to be erased. In FIG. 4(2), the
`controller Shifts in a command that is decoded to a Set erase
`enable command which is used to latch the address decode
`Signal onto the erase enable register for the addressed Sector.
`This tags the sector for subsequent erase. In FIG. 4(3), if
`more Sectors are to be tagged, the operations described
`relative to FIGS. 4(1)–4(2) are repeated until all sectors
`intended for erase have been tagged. After all Sectors
`
`15
`
`25
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`5,936,971
`
`6
`intended for erase have been tagged, the controller initiates
`an erase cycle as illustrated in FIG. 4(4).
`Optimized erase implementations have been disclosed in
`two copending U.S. patent applications. They are copending
`U.S. patent applications, Ser. No. 204,175, filed Jun. 8,
`1988, by Dr. Eliyahou Harari, now U.S. Pat. No. 5,095,344,
`and one entitled “Multi-State EEprom Read and Write
`Circuits and Techniques,” Ser. No. 07/337,579, filed Apr. 13,
`1989, now abandoned, by Sanjay Mehrotra and Dr. Eliyahou
`Harari. The disclosures of the two applications are hereby
`incorporate by reference. The Flash EEprom cells are erased
`by applying a pulse of erasing Voltage followed by a read to
`verify if the cells are erased to the "erased' state. If not,
`further pulsing and verifying are repeated until the cells are
`Verified to be erased. By erasing in this controlled manner,
`the cells are not Subject to over-erasure which tends to age
`the EEprom device prematurely as well as make the cells
`harder to program.
`AS the group of Selected SectorS is going through the erase
`cycle, Some Sectors will reach the "erase' State earlier than
`others. Another important feature of the present invention is
`the ability to remove those sectors that have been verified to
`be erased from the group of Selected Sectors, thereby pre
`venting them from over-erasing.
`Returning to FIG. 4(4), after all sectors intended for erase
`have been tagged, the controller initiates an erase cycle to
`erase the group of tagged Sectors. In FIG. 4(5), the controller
`shifts in a global command called Enable Erase into each
`Flash EEprom chip that is to perform an erase. This is
`followed in FIG. 4(5) by the controller raising of the erase
`voltage line (Ve) to a specified value for a specified duration.
`The controller will lower this voltage at the end of the erase
`duration time. In FIG. 4(6), the controller will then do a read
`Verify Sequence on the SectorS Selected for erase. In FIG.
`4(7), if none of the Sectors are verified, the sequences
`illustrated in FIGS. 4(5)–4(7) are repeated. In FIGS. 4(8)
`and 3(9), if one or more sectors are verified to be erased, they
`are taken out of the Sequence. Referring also to FIG. 3A, this
`is achieved by having the controller address each of the
`Verified Sectors and clear the associated erase enable regis
`ters back to a LOW with a clear enable command in bus 237.
`The sequences illustrated in FIGS. 4(5)-4(10) are repeated
`until all the Sectors in the group are verified to be erased in
`FIG. 4(11). At the completion of the erase cycle, the con
`troller will shift in a No Operation (NOP) command and the
`global Enable Erase command will be withdrawn as a
`protection against a false erasure.
`The ability to select which sectors to erase and which ones
`not to, as well as which ones to Stop erasing is advantageous.
`It will allow sectors that have erased before the slower
`erased Sectors to be removed from the erase Sequence So no
`further stress on the device will occur. This will increase the
`reliability of the System. Additional advantage is that if a
`Sector is bad or is not used for Some reason, that Sector can
`be skipped over with no erase occurring within that Sector.
`For example, if a Sector is defective and have shorts in it, it
`may consume much power. A significant System advantage
`is gained by the present invention which allows it to be
`skipped on erase cycles So that it may greatly reduce the
`power required to erase the chip.
`Another consideration in having the ability to pick the
`Sectors to be erased within a device is the power Savings to
`the system. The flexibility in erase configuration of the
`present invention enables the adaptation of the erase needs
`to the power capability of the system. This can be done by
`configuring the Systems to be erased differently by Software
`on a fixed basis between different systems. It also will allow
`
`Micron Ex. 1049, p. 10
`Micron v. Vervain
`IPR2021-01550
`
`

`

`7
`the controller to adaptively change the amount of erasing
`being done by monitoring the Voltage level in a System, Such
`as a laptop computer.
`An additional performance capability of the System in the
`present invention is the ability to issue a reset command to
`a Flash EEprom chip which will clear all erase enable
`latches and will prevent any further erase cycles from
`occurring. This is illustrated in FIGS. 2A and 2B by the reset
`Signal in the line 261. By doing this in a global way to all
`the chips, less time will be taken to reset all the erase enable
`registers.
`An additional performance capability is to have the ability
`to do