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`UNITED STATES PATENT AND TRADEMARK OFFICE
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`_____________
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`_____________
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`MICRON TECHNOLOGY, INC.,
`Petitioner
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`v.
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`VERVAIN, LLC,
`Patent Owner
`_____________
`
`Case: IPR2021-01550
`U.S. Patent No. 10,950,300
`_____________
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`PATENT OWNER’S RESPONSE
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`IPR2021-01550
`U.S. Patent No. 10,950,300
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`TABLE OF CONTENTS
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`I.
`
`II.
`
`INTRODUCTION ........................................................................................... 1
`
`OVERVIEW OF THE ’300 PATENT AND THE CHALLENGED
`CLAIMS .......................................................................................................... 3
`
`A.
`
`B.
`
`C.
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`SLC AND MLC FLASH ........................................................................... 3
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`ADDRESS TABLE ..................................................................................... 4
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`DATA INTEGRITY TESTS ......................................................................... 5
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`D. HOT AND COLD DATA ..........................................................................11
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`E.
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`INDEPENDENT CLAIMS 1 AND 12 ..........................................................11
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`III.
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`PERSON OF ORDINARY SKILL IN THE ART ........................................15
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`IV. OVERVIEW OF THE ALLEGED PRIOR ART ..........................................15
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`A. DUSIJA (EX. 1010) ................................................................................15
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`V.
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`CLAIM CONSTRUCTION ..........................................................................24
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`A.
`
`B.
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`“DATA INTEGRITY TEST” (CLAIMS 1 AND 12) ........................................25
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`“COMPARING THE STORED DATA TO THE RETAINED DATA IN THE
`RANDOM ACCESS VOLATILE MEMORY” (CLAIMS 1 AND 12) ..................27
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`C.
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`“PERIODICALLY” (CLAIM 10) ................................................................31
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`VI. THE CITED REFERENCES DO NOT RENDER CLAIMS 1-12
`UNPATENTABLE ........................................................................................32
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`A. DUSIJA DOES NOT RENDER OBVIOUS CLAIMS 1 AND 12 ......................33
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`
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`LIMITATION [1.E]: PETITIONER’S MAPPING OF THE CLAIMED
`“RANDOM ACCESS VOLATILE MEMORY” TO AN IMPLEMENTATION
`OF DUSIJA’S CACHE IS DEFICIENT ...............................................33
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` LIMITATION [1.G.2]: DUSIJA DOES NOT DISCLOSE OR SUGGEST
`“RETAIN[ING] SUCH STORED DATA IN THE RANDOM ACCESS
`VOLATILE MEMORY” ...................................................................47
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` LIMITATION [1.H]: DUSIJA DOES NOT DISCLOSE OR SUGGEST
`“COMPARING THE STORED DATA TO THE RETAINED DATA IN THE
`RANDOM ACCESS VOLATILE MEMORY” ........................................52
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` CLAIM 12.......................................................................................60
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`B.
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`DUSIJA DOES NOT RENDER OBVIOUS CLAIMS 2-9 AND 11 ...................60
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`DUSIJA AND SUTARDJA DO NOT RENDER OBVIOUS CLAIM 10 .............60
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`C.
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`VII. CONCLUSION ..............................................................................................61
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`TABLE OF AUTHORITIES
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` Page(s)
`
`Cases
`
`Acumed LLC v. Stryker Corp.,
`483 F.3d 800 (Fed. Cir. 2007) ............................................................................ 28
`
`Amazon Web Services, Inc. v. Saint Regis Mohawk Tribe,
`IPR2019-00103, Paper No. 22 (PTAB May 10, 2019) ................................ 58, 59
`
`Bicon, Inc. v. Straumann Co.,
`441 F.3d 945 (Fed. Cir. 2006) ............................................................................ 26
`
`Corning Incorp. v. Danjou’s DSM IP Assets B.V.,
`Case No. IPR2013-00043, Paper No. 95 (PTAB May 1, 2014) ................... 49, 59
`
`DePuy Spine, Inc. v. Medtronic Sofamor Danek, Inc.,
`469 F.3d 1005 (Fed. Cir. 2006) .......................................................................... 25
`
`Hill-Rom Servs., Inc. v. Stryker Corp.,
`755 F.3d 1367 (Fed. Cir. 2014) .................................................................... 26, 28
`
`Innova/Pure Water, Inc. v. Safari Water Filtration Sys., Inc.,
`381 F.3d 1111 (Fed. Cir. 2004) .......................................................................... 26
`
`Liberty Mutual Ins. Co. v. Progressive Casualty Ins. Co.,
`CBM2012-00003, Paper No. 8 (PTAB Oct. 25, 2012) ...................................... 35
`
`Merck & Co. v. Teva Pharm. USA, Inc.,
`395 F.3d 1364 (Fed. Cir. 2005) .......................................................................... 26
`
`Phillips v. AWH Corp.,
`415 F.3d 1303 (Fed. Circ. 2005) (en banc) ........................................................ 24
`
`In re Ratti,
`270 F.2d 810 (CCPA 1959) ................................................................................ 44
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`Sony Corp. v. Cascades Projection LLC,
`Case No. IPR2015-01846, Paper No. 32 (PTAB Jan. 11, 2017) ........................ 36
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`SynQor, Inc. v. Artesyn Techs., Inc.,
`709 F.3d 1365 (Fed. Cir. 2013) .......................................................................... 31
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`Toyota Motor Corp. v. Cellport Systems, Inc.,
`IPR2015-00633, Paper No. 11 (Aug. 14, 2015) ................................................. 25
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`TQ Delta LLC v. Cisco Systems,
`942 F.3d 1352 (Fed. Cir. 2019) .......................................................................... 42
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`
`Exhibit
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`EXHIBIT LIST
`
`
`Description
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`Ex. 2001 Declaration of Dr. Sunil Khatri
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`Ex. 2002 Chen et al., Ultra MLC Technology Introduction, Advantech
`Technical White Paper (Oct. 5, 2012) (“Chen”)
`
`Ex. 2003 Excerpts from Micheloni et al., Inside NAND Flash Memories
`(1st ed. 2010) (“Micheloni”)
`
`Ex. 2004 Intentionally omitted
`
`Ex. 2005 Microsoft Computer Dictionary definition for “data integrity”
`
`Ex. 2006 Hargrave’s Communications Dictionary definition for “data
`integrity”
`
`Ex. 2007 https://www.law360.com/articles/1381597/albright-says-he-ll-
`very-rarely-put-cases-on-hold-for-ptab
`
`Ex. 2008 Docket Sheet for Case. No. 6:21-cv-487-ADA; Vervain v.
`Micron Technology et al.; U.S. District Court, Western District
`of Texas.
`
`Ex. 2009 Exhibit D-3, Invalidity Claim Chart for the ’300 Patent based
`on U.S. Patent Application Pub. No. 2011/0099460 (“Dusija”)
`
`Ex. 2010 Exhibit D-18, Invalidity Claim Chart for the ’300 Patent based
`on U.S. Patent Application Pub. No. US 2008/0140918
`(“Sutardja”)
`
`Ex. 2011 Intentionally omitted
`
`Ex. 2012 Claim Construction Order in Vervain v. Micron Tech., Inc.,
`No. 6:21-cv-487-ADA (W.D. Tex.) and Vervain v. Western
`Digital Corp., No. 6:21-cv-488-ADA (W.D. Tex.) (Jan. 24,
`2022)
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`Previously
`Submitted
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`Ex. 2013 Micron’s Preliminary Invalidity Contentions for U.S. Patent
`Nos. 8,891,298; 9,196,385; 9,997,240; and 10,950,300; Case.
`No. 6:21-cv-487-ADA; Vervain v. Micron Technology et al.;
`U.S. District Court, Western District of Texas.
`
`Ex. 2014 Declaration of Dr. Sunil Khatri in Support of Patent Owner’s
`Response
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`Ex. 2015 Transcript of June 10, 2022 Deposition of Dr. David Liu
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`Ex. 2016 Intentionally omitted
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`Ex. 2017 U.S. Patent No. 5,721,862
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`Ex. 2018 Intentionally omitted
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`Ex. 2019 U.S. Patent No. 5,535,399
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`I.
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`INTRODUCTION
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`Vervain, LLC (“Patent Owner”) respectfully submits this Response to the
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`Board’s decision to institute inter partes review (Paper No. 11, the “Decision”) and
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`to the petition for inter partes review (Paper No. 1, the “Petition”) filed by Micron
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`Technology, Inc. (“Petitioner”). The Board instituted review of U.S Patent No.
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`10,950,300 (Ex. 1007, “the ’300 patent” or “the challenged patent”) on two grounds
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`that challenge claims 1-12 (“the challenged claims”) of the ’300 patent. Decision,
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`6, 33. Petitioner has not, however, carried its burden of proving unpatentability by
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`a preponderance of the evidence (35 U.S.C. § 316(e)), because as explained below
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`and in the accompanying declaration of Dr. Khatri, Petitioner has not established
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`that the cited prior art discloses or suggests all of the limitations of the challenged
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`claims.1 Moreover, a person of ordinary skill in the art (POSA) would not have
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`configured Dusija’s (Ex. 1010) system in the manner proposed by Petitioner.
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`In particular, as explained further below in Section VI, Petitioner’s analysis
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`for the “random access volatile memory” feature of claim 1 is faulty. For that feature
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`(initially recited in limitation [1.E] of claim 1), the Petition relies on an obviousness
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`argument relating to Dusija’s controller and cache. The “random access volatile
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`1 Patent Owner submits the declaration of Dr. Sunil Khatri (Ex. 2014), an expert in
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`the field of the ’300 patent. (Ex. 2014, ¶¶1-19.)
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`memory” is also recited in limitations [1.G.2] and [1.H]. But Petitioner ignores
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`various inconvenient aspects of Dusija’s disclosure, including that Dusija clearly
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`discloses a cache (central to Petitioner’s proposed obviousness implementation) in
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`non-volatile as opposed to volatile memory, and that Dusija explicitly cautions
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`against implementing certain functionality at its controller. The Petition’s
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`deficiencies regarding claim 1 carry through to independent claim 12 as well.
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`Additionally, Petitioner has not met its burden through cryptic mappings of
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`the claim limitations to components of Dusija’s system. Not only does the Petition
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`fail to state with sufficient clarity what aspects of Dusija it is relying on for various
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`limitations, but upon cross-examination Petitioner’s declarant Dr. Liu could not state
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`clearly basic aspects of the proposed obviousness configuration of Dusija’s system.
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`As Dr. Khatri explains, a POSA would not have been motivated to configure
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`Dusija’s system in the manner proposed by Petitioner and would not have had a
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`reasonable expectation of success regarding such a configuration. Petitioner’s lack
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`of clarity in its mapping manifests in inconsistent analysis in the Petitioner’s
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`treatment of various limitations, as explained below in Section VI. Petitioner’s lack
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`of clarity is not surprising, given that Petitioner apparently seeks to ignore aspects
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`of Dusija that are damaging to its positions, including Dusija’s teachings regarding
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`its cache being in flash memory, and the undesirability of performing cache-related
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`functionality at Dusija’s controller. But Petitioner should not be rewarded for its
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`vagueness and obfuscation. Petitioner has not met its burden in this proceeding and
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`has not established that the challenged claims are unpatentable.
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`II. OVERVIEW OF THE ’300 PATENT AND THE CHALLENGED
`CLAIMS
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`A.
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`SLC and MLC Flash
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`The ’300 patent explains that single level cell (SLC) flash memory stores 1
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`bit per cell, and multiple level cell (MLC) flash memory stores more than 1 bit per
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`cell. Ex. 1007, 2:17-20; Ex. 2014 ¶¶24-39. A person of ordinary skill in the art
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`(POSA) would have known that there are pros and cons to SLC and MLC flash. Ex.
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`2014, ¶¶20-35; see also infra Section III (discussion regarding POSA). In general,
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`SLC is faster and less prone to errors, but requires more space and power to store a
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`given amount of data. Ex. 1007, 1:57-63. The opposite is true of MLC. MLC flash
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`is slower and more prone to errors, but stores data more densely with less power
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`consumption. Id., 3:41-44.
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`SLC and MLC flash memories both use the same type of transistor called a
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`floating gate transistor. Id., 3:50-53. They both store a charge in the floating gate
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`of each transistor (cell), which changes the threshold voltage of the transistor. The
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`memory uses the threshold voltage to determine what bit, or bits, were stored in the
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`transistor. The MLC cell in the figure below illustrates threshold voltages for a 2-
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`bit MLC cell.
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`Ex. 2002, 3.
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`The primary difference between SLC and MLC is what data each threshold
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`voltage is interpreted to represent. With SLC flash, the transistor stores only a 1 or
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`0, so a wide range of threshold voltages can be allotted to a single bit. This allows
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`for faster and more reliable memory access. On the other hand, MLC flash must be
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`slowly and carefully programmed to a narrower, more precise range of threshold
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`voltages, with each threshold voltage range representing a specific pair of bits (see
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`figure above, which shows four pairs of bits—11, 10, 01, and 00—corresponding to
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`smaller ranges of threshold voltages compared to the SLC). Ex. 1007, 3:39-41.
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`B. Address Table
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`The ’300 patent discloses that in order to provide wear leveling, garbage
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`collection, and bad block management, a translation layer is used to map logical
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`addresses to actual physical addresses, which access specific physical locations in
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`the flash memory. Ex. 2003, 9-11; Ex. 1007, 3:3-35; Ex. 2014, ¶33. As part of this
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`translation layer, “tables are widely used in order to map sectors and pages from
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`logical to physical.” Ex. 2003, 9; Ex. 1007, 3:19-23. These tables map logical
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`blocks to physical blocks. Ex. 2003, 9-11; Ex. 1007, 3:19-23. Using a “block” or
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`similar granularity is important, since flash memory is arranged so that when erasing
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`and rewriting data, a whole block is “erased together.” Ex. 2003, 6; Ex. 1007, 2:59-
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`3:2. The ’300 Patent explains that “[t]he address ranges within the translation table
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`will assume some minimum quantum, such as, for example, one block…” Ex. 1007,
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`5:54-58. The ’300 Patent further explains that memory is written and mapped on
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`the granularity of a “quantum,” such as a block or page. Id., 5:54-58, FIGS. 3A-B.
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`C. Data Integrity Tests
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`As mentioned above, when data is stored in MLC memory, it is more prone
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`to errors than data stored in SLC memory. One reason for this is that the threshold
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`voltage intervals for MLC memory are smaller than the intervals for SLC memory,
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`and thus, errors can occur when writing or reading the data. Ex. 2014, ¶34. Errors
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`can also be caused by the data stored in neighboring cells. Id. A data integrity test
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`is a test that checks the integrity of the data (i.e., whether errors have occurred). This
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`test can be run immediately after data is written, or at a later time. The ’300 Patent
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`discloses that if the test reveals a problem such as corrupt data, the data can be
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`remapped to SLC (which is less error-prone), and the address table is modified
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`accordingly. Ex. 1007, 4:30-36. Alternately, MLC data can be remapped to other
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`MLC blocks, and the address table is then modified accordingly. Id., 3:13-35.
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`The ’300 Patent discloses a particular way of writing the data to the MLC and
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`performing the data integrity test. The ’300 Patent recognizes that there were
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`advantages in using a DRAM to assist with both the write access operation and data
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`integrity test. As seen in Figure 1 below, the controller (highlighted purple) controls
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`a DRAM (highlighted red).
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`Ex. 1007, FIG. 1 (annotations added2), 5:34-35.
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` The DRAM is used during a write access operation to the MLC flash
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`(highlighted blue). The data to be written to the MLC flash is maintained (or
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`2 Unless otherwise noted, Patent Owner added coloring to the Figures.
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`retained) in the DRAM. Id., 5:59-61. If time permits, the controller performs a data
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`integrity test on the data that was stored in the MLC. Id., 5:61-64. If the stored data
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`fails the data integrity test, the address range for the stored data is remapped to a new
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`location (e.g., the SLC flash). Id., 5:64-67.
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`Figures 3A and 3B of the ’300 Patent show in more detail how the DRAM is
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`used during the write access operation and data integrity test.
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`Id., FIG. 3A. The write access operation begins at step 100. Id., 6:17-20. In step
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`102, the data to be written to the MLC is read from the DRAM into the memory of
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`the device controller. Id., 6:15-22. In step 104, the controller obtains the logical and
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`physical address ranges for the data to be written to the MLC. Id., 6:22-25. In step
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`106, the controller combines the data from the DRAM with data from the MLC. Id.,
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`6:25-27. In step 108, the controller erases the physical address range where the data
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`is being written. Id., 6:27-28. Finally, in step 110, the combined data is written to
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`the MLC flash. Id., Fig. 3A (step 110), 6:28-30.
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`The data integrity test begins at the bottom of Figure 3A and continues to
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`Figure 3B. In step 112, the data that was stored in the MLC (“the stored data”) is
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`read into controller’s memory. Id., 6:30-32. In step 114, the stored data is compared
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`to the data that was retained in the DRAM (“the retained data”). Id., 6:33-38.
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`Id., FIG. 3B. If there is a match, the data was successfully stored in the MLC. Id.,
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`6:38-40. If not the retained data is written to another location (e.g., SLC). Id., 6:40-
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`44.
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`During prosecution, the Examiner acknowledge in the Reasons for Allowance
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`section of the Notice of Allowance that the use of RAM during the data integrity test
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`was patentable over the prior art. Ex. 1008, 179-180 (“This limitation requires that
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`the nonvolatile memory element ‘retain’ the stored data . . .”), 210 (referencing
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`Applicant’s Remarks § IV pp. 8-9). Furthermore, the Examiner considered prior art
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`that mentioned RAM, and determined that it did not use RAM like Dr. Rao (inventor
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`of the ’300 Patent) did and that it would not have been obvious to do so. Id., 210-
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`211 (citing U.S. 7,505,338, see 5:51-53).
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`D. Hot and Cold Data
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`One can distinguish between “hot” blocks (which receive more frequent
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`writes), and “cold” blocks (which receive less frequent writes). Ex. 1007, 6:53-59.
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`Because SLC has greater endurance, “hot” blocks can be allocated to SLC to
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`increase the lifetime of the system. Id. “Cold” blocks, on the other hand, can be
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`allocated to MLC to take advantage of its higher density storage. Ex. 2014, ¶35.
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`E.
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`Independent Claims 1 and 12
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`In claim 1, the system for storing data comprises three types of memory: (1)
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`nonvolatile MLC memory; (2) nonvolatile SLC memory; and (3) random access
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`volatile memory (highlighted red) (hereinafter, RAM). The RAM is a key feature
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`of the invention and it permeates most of the elements of the claim ([1.A], [1.E]-
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`[1.H]). As discussed above, the RAM is particularly important to the “write access
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`operation” in [1.G] and the “data integrity test” in [1.H].
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`[1.PRE] A system for storing data comprising:
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`Claim 1
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`[1.A] memory space containing volatile memory space and nonvolatile
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`memory space, wherein the nonvolatile memory space includes both
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`multilevel cell (MLC) memory space and single level cell (SLC)
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`memory space;
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`[1.B]
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`at least one controller to operate memory elements and associated
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`memory space;
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`[1.C]
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`at least one MLC nonvolatile memory element that can be mapped into
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`the MLC memory space;
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`[1.D]
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`at least one SLC nonvolatile memory element that can be mapped into
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`the SLC memory space;
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`[1.E]
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`at least one random access volatile memory;
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`[1.F]
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`an FTL flash translation layer, wherein the at least one controller, or
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`FTL, or a combination of both maintain an address table in one or more
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`of the memory elements and random access volatile memory;
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`[1.G]
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`the controller controlling access of the MLC and SLC nonvolatile
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`memory elements and the random access volatile memory for storage
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`of data therein, the controller, in at least a Write access operation to the
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`MLC nonvolatile memory element, operable to store data in the MLC
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`12
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`nonvolatile memory element and retain such stored data in the
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`random access volatile memory;
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`[1.H]
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`the controller performing a data integrity test on stored data in the
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`MLC nonvolatile memory element after at least a Write access
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`operation is performed thereon by comparing the stored data to the
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`retained data in the random access volatile memory;
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`[1.I]
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`wherein the address table maps logical and physical addresses
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`adaptable to the system, wherein the mapping is performed as
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`necessitated by the system to maximize lifetime, and wherein the
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`mapping maps blocks, pages, or bytes of data in either volatile or
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`nonvolatile, or both, memories; and
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`[1.J]
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`wherein a failure of the data integrity test performed by the controller
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`results in a remapping of the address space to a different physical range
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`of addresses and transfer of data corresponding to the stored data to
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`those remapped physical addresses from those determined to have
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`failed the data integrity test to achieve enhanced endurance.
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`During the write operation in [1.G], the controller “store[s] data in the MLC
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`nonvolatile memory element” (highlighted blue). The controller also retains a copy
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`of the “stored data” in the RAM (highlighted red). In [1.H], this copy is referred to
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`as the “retained data in the random access volatile memory.”
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`The controller performs the data integrity test in [1.H] by comparing the
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`“stored data” (highlighted blue) to the “retained data in the [RAM]” (highlighted
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`red). In the Reasons for Allowance, the Examiner indicated that using the RAM for
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`13
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`the compare operation was not taught or suggested by the prior art. Ex. 1008, 179-
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`180, 210. Like claim 1, claim 12 recites a RAM that is used for a “write access
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`operation” (see [1.G]) and a “data integrity test” (see [1.H]).
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`[12.PRE] A system for storing data comprising:
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`Claim 12
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`[12.A] memory space containing volatile memory space and nonvolatile
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`memory space, wherein the nonvolatile memory space includes both
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`multilevel cell (MLC) memory space and single level cell (SLC)
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`memory space;
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`[12.B]
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`at least one controller to operate memory elements and associated
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`memory space, and to maintain an address table in one or more of the
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`memory elements;
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`[12.C]
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`at least one MLC nonvolatile memory element that can be mapped into
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`the MLC memory space;
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`[12.D]
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`at least one SLC nonvolatile memory element that can be mapped into
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`the SLC memory space;
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`[12.E]
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`at least one random access volatile memory;
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`[12.F]
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`the controller controlling access of the MLC and SLC nonvolatile
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`memory elements and the random access volatile memory for storage
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`of data therein, the controller, in at least a Write access operation to the
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`MLC nonvolatile memory element, operable to store data in the MLC
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`nonvolatile memory element and retain such stored data in the
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`random access volatile memory;
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`[12.G]
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`the controller performing a data integrity test on stored data in the
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`MLC nonvolatile memory element after at least a Write access
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`operation is performed thereon by comparing the stored data to the
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`retained data in the random access volatile memory;
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`[12.H] wherein the address table maps logical and physical addresses
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`adaptable to the system, wherein the mapping is performed as
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`necessitated by the system to maximize lifetime, and wherein the
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`mapping maps blocks, pages, or bytes of data in either volatile or
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`nonvolatile, or both, memories; and
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`[12.I] wherein a failure of the data integrity test performed by the controller
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`results in a remapping of the address space to a different physical range
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`of addresses and transfer of data corresponding to the stored data to
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`those remapped physical addresses from those determined to have
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`failed the data integrity test to achieve enhanced endurance.
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`
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`III. PERSON OF ORDINARY SKILL IN THE ART
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`For purposes of this proceeding only, Patent Owner adopts Petitioner’s
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`definition of a person of ordinary skill in the art (POSA). Petition, 27; Ex. 2014,
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`¶20-23.
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`IV. OVERVIEW OF THE ALLEGED PRIOR ART
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`A. Dusija (Ex. 1010)
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`Dusija is a U.S. patent application that was published in 2011. Dusija
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`addresses a problem that occurs with flash memory—as it ages, its error rate
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`increases, which requires a resource intensive error correction code (ECC) to correct
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`errors. Ex. 1010, [0012-0017]; Ex. 2014, ¶¶44-60. As Dusija explains, in order to
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`ensure data integrity in such situations, a complex, computationally intensive ECC
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`is utilized which results in memory performance degradation. Ex. 1010, [0014]. To
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`address this problem, Dusija “provid[es] a mechanism to control and limit the errors
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`arising after writing to high density memory [i.e., MLC] … and a second chance to
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`rewrite data with less error if the copy in the high density memory has excessive
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`errors.” Id., [0024]. By using the disclosed mechanism the ECC complexity is
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`reduced and an “advantage is gained at the slight expense of an additional post-write
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`read and infrequent additional rewrites to a less [sic, lower] density memory portion
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`[i.e., SLC].” Id.
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`In contrast to the ’300 Patent, the SLC memory in Dusija is primarily used for
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`enhancing memory life by starting an error management process “after the memory
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`has aged to a predetermined amount.” Id., Abstract. Hence, the primary teaching of
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`Dusija is to extend memory life when the memory is aging, and not slow it down by
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`doing the “error management … when a memory is new with little or no errors.” Id.
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`Thus, Dusija teaches a MLC memory chip where a nominal amount of SLC memory
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`is deployed only late in the lifetime of the MLC memory in order to avoid ECC
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`processing at the controller ASIC. Id., [0016], [0024], [0155].
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`To reduce ECC complexity and increase memory performance, Dusija
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`describes a flash memory device 90 including a controller ASIC chip 102
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`(highlighted purple) and a memory chip 100 (highlighted blue).
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`
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`Ex. 1010, FIG. 1, [0016] (“the controller ASIC chip”), [0059] (“controller 102”),
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`[0106] (“the controller ASIC chip”). The memory chip includes an on-chip control
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`circuit 110 with state machine 112. The memory chip also includes input/output
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`(I/O) circuits, data latches (highlighted yellow), sense modules, and a memory array
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`(highlighted darker blue). Ex. 1010, [0059]. In contrast to the ’300 Patent, there is
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`no mention of DRAM (or even RAM) in the memory chip 100, controller chip 102,
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`or anywhere else in the flash memory device 90. In fact, the only time that Dusija
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`mentions RAM is in the “Background of the Invention,” when Dusija is
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`distinguishing its purported invention from RAM. Id., [0003].
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`After a write access command, the ECC Processor 62 can check an error
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`detection code (EDC) to see whether data was written correctly to the flash memory
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`array 200. Id., [0087-0088].3 Dusija teaches that performing the ECC to correct the
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`worst-case number of bits would be burdensome in terms of processing time as well
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`as chip area, and the extra circuitry for this would not be well justified on the
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`controller ASIC chip.
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`Using ECC to correct a worst-case number of error bits will
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`consume a great amount of processing time. The more bits it has
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`to correct, the more computational time is required. The memory
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`performance will be degraded. Additional dedicated hardware
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`may be implemented to perform the ECC in a reasonable amount
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`of time. Such dedicated hardware can take up a considerable
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`amount of space on the controller ASIC chip. Moreover, for
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`most of the life time of the device, the ECC is only marginally
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`3 This error detection is different from the alleged comparison in the Petition. There
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`Petitioner wrongly alleged that the comparison is between sets of data that are in the
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`same RAM, and Petitioner has not alleged that the ECC meets this requirement.
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`Petition, 25-27, 48-50.
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`utilized, resulting in its large over-heads being wasted and no real
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`benefits.
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`Ex. 1010, [0016] (emphasis added). This is why Dusija expressly teaches that any
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`error checking should be performed by conducting a comparison at the data latches
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`on the flash memory chip, not at the controller chip. Id., [0112], [0135-0136]. This
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`also eliminates the need to “toggle” the data out to the controller (a different chip)
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`and therefore “much time can be saved.” Id., [0136]. By performing the error
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`detection on the memory chip, it is possible to increase the performance of the flash
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`memory device and eliminate the need for dedicated area-intensive ECC hardware
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`on the controller chip. Id., [0016], [0136].
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`The data latches compare the data that was written to the MLC portion of the
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`memory array with a copy of the data that was cached in the SLC portion of the
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`memory array. Id., [0020-0022]. As seen in Figure 1 above, and as taught in [0022],
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`the data latches are coupled to the flash memory array and both sets of data are
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`already in the flash memory. Further, [0076] and [0088] teach that the output of the
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`sense amplifier 490, residing in sense module 480, is stored in the latches 430. This
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`streamlines the comparison process and achieves Dusija’s objectives of reducing
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`processing time and overhead.
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`The memory array 200 is shown in more detail in Figures 14A and 14B. As
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`seen below, the memory array 200 comprises a first portion 410 that is “more robust
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`but lower density storage” (i.e., SLC) and a second portion 420 that is “less robust
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`but higher density storage” (i.e., MLC) (highlighted blue).
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`
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`As indicated above, the memory chip uses its on-chip control circuitry 110 to
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`write data to the second portion (MLC). Id., [0059, 0111]. If the stored data has an
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`acceptable number of errors, then the stored copy in the MLC becomes the “valid”
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`copy. Id., [0113], [0129]. Otherwise, the data is rewritten to the first portion (SLC).
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`Id.
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`When the data is written to the MLC, the flash memory device 90 can check
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`for errors one of two ways. Id., [0112]. Either the flash memory device can use the
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`ECC Processor at the controller to check the “EDC portion of the ECC.” Id. Dusija
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`strongly recommends against this approach. Id., [0016], [0136]. Alternately, the
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`flash memory device can check for errors on the memory chip by using the data
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`latches and locally cached data. Id., [0112], [0135]. Dusija strongly recommends
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`this approach because it improves performance of the flash memory device by
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`reducing overhead and eliminating the need to toggle data out to the controller 102,
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`which is on a separate ASIC.
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`According to another preferred embodiment, the memory array
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`is provided with a set of data latches on an integrated circuit chip, the
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`checking of the error bits in the first copy is accomplished by loading
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`the first copy and the cached copy into the set of data latches and
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`making a comparison at the set of data latches.
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`By not making the comparison at the controller, the data does not
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`have to be toggled out to the controller, much time can be saved. Figure
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`1 shows the data latches 430, which is on-chip, for the data comparison
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`to take place.
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`Id., [0135-0136] (emphasis added); see also id., [0012].
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`According to Dusija, another advantage of caching the data locally in the
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`memory array is that if there is an error writing to the MLC portion of the memory
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`array, the cached copy can become the “valid” copy. Id., [0129]. Dusija uses the
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`embodiment shown in Figure 16A to further advocate for caching the data locally i