`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`_____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`_____________
`
`MICRON TECHNOLOGY, INC.,
`Petitioner
`
`v.
`
`VERVAIN, LLC,
`Patent Owner
`_____________
`
`Case: IPR2021-01550
`U.S. Patent No. 10,950,300
`_____________
`
`
`
`PATENT OWNER’S RESPONSE
`
`
`
`
`
`
`
`
`

`

`IPR2021-01550
`U.S. Patent No. 10,950,300
`
`
`TABLE OF CONTENTS
`
`I.
`
`II.
`
`INTRODUCTION ........................................................................................... 1
`
`OVERVIEW OF THE ’300 PATENT AND THE CHALLENGED
`CLAIMS .......................................................................................................... 3
`
`A.
`
`B.
`
`C.
`
`SLC AND MLC FLASH ........................................................................... 3
`
`ADDRESS TABLE ..................................................................................... 4
`
`DATA INTEGRITY TESTS ......................................................................... 5
`
`D. HOT AND COLD DATA ..........................................................................11
`
`E.
`
`INDEPENDENT CLAIMS 1 AND 12 ..........................................................11
`
`III.
`
`PERSON OF ORDINARY SKILL IN THE ART ........................................15
`
`IV. OVERVIEW OF THE ALLEGED PRIOR ART ..........................................15
`
`A. DUSIJA (EX. 1010) ................................................................................15
`
`V.
`
`CLAIM CONSTRUCTION ..........................................................................24
`
`A.
`
`B.
`
`“DATA INTEGRITY TEST” (CLAIMS 1 AND 12) ........................................25
`
`“COMPARING THE STORED DATA TO THE RETAINED DATA IN THE
`RANDOM ACCESS VOLATILE MEMORY” (CLAIMS 1 AND 12) ..................27
`
`C.
`
`“PERIODICALLY” (CLAIM 10) ................................................................31
`
`VI. THE CITED REFERENCES DO NOT RENDER CLAIMS 1-12
`UNPATENTABLE ........................................................................................32
`
`A. DUSIJA DOES NOT RENDER OBVIOUS CLAIMS 1 AND 12 ......................33
`
`
`
`LIMITATION [1.E]: PETITIONER’S MAPPING OF THE CLAIMED
`“RANDOM ACCESS VOLATILE MEMORY” TO AN IMPLEMENTATION
`OF DUSIJA’S CACHE IS DEFICIENT ...............................................33
`
` LIMITATION [1.G.2]: DUSIJA DOES NOT DISCLOSE OR SUGGEST
`“RETAIN[ING] SUCH STORED DATA IN THE RANDOM ACCESS
`VOLATILE MEMORY” ...................................................................47
`
` LIMITATION [1.H]: DUSIJA DOES NOT DISCLOSE OR SUGGEST
`“COMPARING THE STORED DATA TO THE RETAINED DATA IN THE
`RANDOM ACCESS VOLATILE MEMORY” ........................................52
`
` CLAIM 12.......................................................................................60
`
`B.
`
`DUSIJA DOES NOT RENDER OBVIOUS CLAIMS 2-9 AND 11 ...................60
`
`i
`
`

`

`IPR2021-01550
`U.S. Patent No. 10,950,300
`
`DUSIJA AND SUTARDJA DO NOT RENDER OBVIOUS CLAIM 10 .............60
`
`C.
`
`VII. CONCLUSION ..............................................................................................61
`
`
`
`
`
`
`
`
`
`
`ii
`
`

`

`IPR2021-01550
`U.S. Patent No. 10,950,300
`
`
`TABLE OF AUTHORITIES
`
` Page(s)
`
`Cases
`
`Acumed LLC v. Stryker Corp.,
`483 F.3d 800 (Fed. Cir. 2007) ............................................................................ 28
`
`Amazon Web Services, Inc. v. Saint Regis Mohawk Tribe,
`IPR2019-00103, Paper No. 22 (PTAB May 10, 2019) ................................ 58, 59
`
`Bicon, Inc. v. Straumann Co.,
`441 F.3d 945 (Fed. Cir. 2006) ............................................................................ 26
`
`Corning Incorp. v. Danjou’s DSM IP Assets B.V.,
`Case No. IPR2013-00043, Paper No. 95 (PTAB May 1, 2014) ................... 49, 59
`
`DePuy Spine, Inc. v. Medtronic Sofamor Danek, Inc.,
`469 F.3d 1005 (Fed. Cir. 2006) .......................................................................... 25
`
`Hill-Rom Servs., Inc. v. Stryker Corp.,
`755 F.3d 1367 (Fed. Cir. 2014) .................................................................... 26, 28
`
`Innova/Pure Water, Inc. v. Safari Water Filtration Sys., Inc.,
`381 F.3d 1111 (Fed. Cir. 2004) .......................................................................... 26
`
`Liberty Mutual Ins. Co. v. Progressive Casualty Ins. Co.,
`CBM2012-00003, Paper No. 8 (PTAB Oct. 25, 2012) ...................................... 35
`
`Merck & Co. v. Teva Pharm. USA, Inc.,
`395 F.3d 1364 (Fed. Cir. 2005) .......................................................................... 26
`
`Phillips v. AWH Corp.,
`415 F.3d 1303 (Fed. Circ. 2005) (en banc) ........................................................ 24
`
`In re Ratti,
`270 F.2d 810 (CCPA 1959) ................................................................................ 44
`
`Sony Corp. v. Cascades Projection LLC,
`Case No. IPR2015-01846, Paper No. 32 (PTAB Jan. 11, 2017) ........................ 36
`
`iii
`
`

`

`IPR2021-01550
`U.S. Patent No. 10,950,300
`
`
`SynQor, Inc. v. Artesyn Techs., Inc.,
`709 F.3d 1365 (Fed. Cir. 2013) .......................................................................... 31
`
`Toyota Motor Corp. v. Cellport Systems, Inc.,
`IPR2015-00633, Paper No. 11 (Aug. 14, 2015) ................................................. 25
`
`TQ Delta LLC v. Cisco Systems,
`942 F.3d 1352 (Fed. Cir. 2019) .......................................................................... 42
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`iv
`
`

`

`IPR2021-01550
`U.S. Patent No. 10,950,300
`
`
`Exhibit
`
`EXHIBIT LIST
`
`
`Description
`
`Ex. 2001 Declaration of Dr. Sunil Khatri
`
`Ex. 2002 Chen et al., Ultra MLC Technology Introduction, Advantech
`Technical White Paper (Oct. 5, 2012) (“Chen”)
`
`Ex. 2003 Excerpts from Micheloni et al., Inside NAND Flash Memories
`(1st ed. 2010) (“Micheloni”)
`
`Ex. 2004 Intentionally omitted
`
`Ex. 2005 Microsoft Computer Dictionary definition for “data integrity”
`
`Ex. 2006 Hargrave’s Communications Dictionary definition for “data
`integrity”
`
`Ex. 2007 https://www.law360.com/articles/1381597/albright-says-he-ll-
`very-rarely-put-cases-on-hold-for-ptab
`
`Ex. 2008 Docket Sheet for Case. No. 6:21-cv-487-ADA; Vervain v.
`Micron Technology et al.; U.S. District Court, Western District
`of Texas.
`
`Ex. 2009 Exhibit D-3, Invalidity Claim Chart for the ’300 Patent based
`on U.S. Patent Application Pub. No. 2011/0099460 (“Dusija”)
`
`Ex. 2010 Exhibit D-18, Invalidity Claim Chart for the ’300 Patent based
`on U.S. Patent Application Pub. No. US 2008/0140918
`(“Sutardja”)
`
`Ex. 2011 Intentionally omitted
`
`Ex. 2012 Claim Construction Order in Vervain v. Micron Tech., Inc.,
`No. 6:21-cv-487-ADA (W.D. Tex.) and Vervain v. Western
`Digital Corp., No. 6:21-cv-488-ADA (W.D. Tex.) (Jan. 24,
`2022)
`
`Previously
`Submitted
`X
`
`X
`
`X
`
`
`
`X
`
`X
`
`X
`
`X
`
`X
`
`X
`
`
`
`
`
`v
`
`

`

`IPR2021-01550
`U.S. Patent No. 10,950,300
`
`
`Ex. 2013 Micron’s Preliminary Invalidity Contentions for U.S. Patent
`Nos. 8,891,298; 9,196,385; 9,997,240; and 10,950,300; Case.
`No. 6:21-cv-487-ADA; Vervain v. Micron Technology et al.;
`U.S. District Court, Western District of Texas.
`
`Ex. 2014 Declaration of Dr. Sunil Khatri in Support of Patent Owner’s
`Response
`
`Ex. 2015 Transcript of June 10, 2022 Deposition of Dr. David Liu
`
`Ex. 2016 Intentionally omitted
`
`Ex. 2017 U.S. Patent No. 5,721,862
`
`Ex. 2018 Intentionally omitted
`
`Ex. 2019 U.S. Patent No. 5,535,399
`
`
`
`X
`
`
`
`
`
`
`
`
`
`
`
`
`
`vi
`
`

`

`IPR2021-01550
`U.S. Patent No. 10,950,300
`
`
`I.
`
`INTRODUCTION
`
`Vervain, LLC (“Patent Owner”) respectfully submits this Response to the
`
`Board’s decision to institute inter partes review (Paper No. 11, the “Decision”) and
`
`to the petition for inter partes review (Paper No. 1, the “Petition”) filed by Micron
`
`Technology, Inc. (“Petitioner”). The Board instituted review of U.S Patent No.
`
`10,950,300 (Ex. 1007, “the ’300 patent” or “the challenged patent”) on two grounds
`
`that challenge claims 1-12 (“the challenged claims”) of the ’300 patent. Decision,
`
`6, 33. Petitioner has not, however, carried its burden of proving unpatentability by
`
`a preponderance of the evidence (35 U.S.C. § 316(e)), because as explained below
`
`and in the accompanying declaration of Dr. Khatri, Petitioner has not established
`
`that the cited prior art discloses or suggests all of the limitations of the challenged
`
`claims.1 Moreover, a person of ordinary skill in the art (POSA) would not have
`
`configured Dusija’s (Ex. 1010) system in the manner proposed by Petitioner.
`
`In particular, as explained further below in Section VI, Petitioner’s analysis
`
`for the “random access volatile memory” feature of claim 1 is faulty. For that feature
`
`(initially recited in limitation [1.E] of claim 1), the Petition relies on an obviousness
`
`argument relating to Dusija’s controller and cache. The “random access volatile
`
`
`1 Patent Owner submits the declaration of Dr. Sunil Khatri (Ex. 2014), an expert in
`
`the field of the ’300 patent. (Ex. 2014, ¶¶1-19.)
`
`1
`
`

`

`IPR2021-01550
`U.S. Patent No. 10,950,300
`
`memory” is also recited in limitations [1.G.2] and [1.H]. But Petitioner ignores
`
`various inconvenient aspects of Dusija’s disclosure, including that Dusija clearly
`
`discloses a cache (central to Petitioner’s proposed obviousness implementation) in
`
`non-volatile as opposed to volatile memory, and that Dusija explicitly cautions
`
`against implementing certain functionality at its controller. The Petition’s
`
`deficiencies regarding claim 1 carry through to independent claim 12 as well.
`
`Additionally, Petitioner has not met its burden through cryptic mappings of
`
`the claim limitations to components of Dusija’s system. Not only does the Petition
`
`fail to state with sufficient clarity what aspects of Dusija it is relying on for various
`
`limitations, but upon cross-examination Petitioner’s declarant Dr. Liu could not state
`
`clearly basic aspects of the proposed obviousness configuration of Dusija’s system.
`
`As Dr. Khatri explains, a POSA would not have been motivated to configure
`
`Dusija’s system in the manner proposed by Petitioner and would not have had a
`
`reasonable expectation of success regarding such a configuration. Petitioner’s lack
`
`of clarity in its mapping manifests in inconsistent analysis in the Petitioner’s
`
`treatment of various limitations, as explained below in Section VI. Petitioner’s lack
`
`of clarity is not surprising, given that Petitioner apparently seeks to ignore aspects
`
`of Dusija that are damaging to its positions, including Dusija’s teachings regarding
`
`its cache being in flash memory, and the undesirability of performing cache-related
`
`functionality at Dusija’s controller. But Petitioner should not be rewarded for its
`
`2
`
`

`

`IPR2021-01550
`U.S. Patent No. 10,950,300
`
`vagueness and obfuscation. Petitioner has not met its burden in this proceeding and
`
`has not established that the challenged claims are unpatentable.
`
`II. OVERVIEW OF THE ’300 PATENT AND THE CHALLENGED
`CLAIMS
`
`A.
`
`SLC and MLC Flash
`
`The ’300 patent explains that single level cell (SLC) flash memory stores 1
`
`bit per cell, and multiple level cell (MLC) flash memory stores more than 1 bit per
`
`cell. Ex. 1007, 2:17-20; Ex. 2014 ¶¶24-39. A person of ordinary skill in the art
`
`(POSA) would have known that there are pros and cons to SLC and MLC flash. Ex.
`
`2014, ¶¶20-35; see also infra Section III (discussion regarding POSA). In general,
`
`SLC is faster and less prone to errors, but requires more space and power to store a
`
`given amount of data. Ex. 1007, 1:57-63. The opposite is true of MLC. MLC flash
`
`is slower and more prone to errors, but stores data more densely with less power
`
`consumption. Id., 3:41-44.
`
`SLC and MLC flash memories both use the same type of transistor called a
`
`floating gate transistor. Id., 3:50-53. They both store a charge in the floating gate
`
`of each transistor (cell), which changes the threshold voltage of the transistor. The
`
`memory uses the threshold voltage to determine what bit, or bits, were stored in the
`
`transistor. The MLC cell in the figure below illustrates threshold voltages for a 2-
`
`bit MLC cell.
`
`3
`
`

`

`IPR2021-01550
`U.S. Patent No. 10,950,300
`
`
`
`
`Ex. 2002, 3.
`
`The primary difference between SLC and MLC is what data each threshold
`
`voltage is interpreted to represent. With SLC flash, the transistor stores only a 1 or
`
`0, so a wide range of threshold voltages can be allotted to a single bit. This allows
`
`for faster and more reliable memory access. On the other hand, MLC flash must be
`
`slowly and carefully programmed to a narrower, more precise range of threshold
`
`voltages, with each threshold voltage range representing a specific pair of bits (see
`
`figure above, which shows four pairs of bits—11, 10, 01, and 00—corresponding to
`
`smaller ranges of threshold voltages compared to the SLC). Ex. 1007, 3:39-41.
`
`B. Address Table
`
`The ’300 patent discloses that in order to provide wear leveling, garbage
`
`collection, and bad block management, a translation layer is used to map logical
`
`addresses to actual physical addresses, which access specific physical locations in
`
`the flash memory. Ex. 2003, 9-11; Ex. 1007, 3:3-35; Ex. 2014, ¶33. As part of this
`
`translation layer, “tables are widely used in order to map sectors and pages from
`
`logical to physical.” Ex. 2003, 9; Ex. 1007, 3:19-23. These tables map logical
`
`4
`
`

`

`IPR2021-01550
`U.S. Patent No. 10,950,300
`
`blocks to physical blocks. Ex. 2003, 9-11; Ex. 1007, 3:19-23. Using a “block” or
`
`similar granularity is important, since flash memory is arranged so that when erasing
`
`and rewriting data, a whole block is “erased together.” Ex. 2003, 6; Ex. 1007, 2:59-
`
`3:2. The ’300 Patent explains that “[t]he address ranges within the translation table
`
`will assume some minimum quantum, such as, for example, one block…” Ex. 1007,
`
`5:54-58. The ’300 Patent further explains that memory is written and mapped on
`
`the granularity of a “quantum,” such as a block or page. Id., 5:54-58, FIGS. 3A-B.
`
`C. Data Integrity Tests
`
`As mentioned above, when data is stored in MLC memory, it is more prone
`
`to errors than data stored in SLC memory. One reason for this is that the threshold
`
`voltage intervals for MLC memory are smaller than the intervals for SLC memory,
`
`and thus, errors can occur when writing or reading the data. Ex. 2014, ¶34. Errors
`
`can also be caused by the data stored in neighboring cells. Id. A data integrity test
`
`is a test that checks the integrity of the data (i.e., whether errors have occurred). This
`
`test can be run immediately after data is written, or at a later time. The ’300 Patent
`
`discloses that if the test reveals a problem such as corrupt data, the data can be
`
`remapped to SLC (which is less error-prone), and the address table is modified
`
`accordingly. Ex. 1007, 4:30-36. Alternately, MLC data can be remapped to other
`
`MLC blocks, and the address table is then modified accordingly. Id., 3:13-35.
`
`5
`
`

`

`IPR2021-01550
`U.S. Patent No. 10,950,300
`
`The ’300 Patent discloses a particular way of writing the data to the MLC and
`
`performing the data integrity test. The ’300 Patent recognizes that there were
`
`advantages in using a DRAM to assist with both the write access operation and data
`
`integrity test. As seen in Figure 1 below, the controller (highlighted purple) controls
`
`a DRAM (highlighted red).
`
`Ex. 1007, FIG. 1 (annotations added2), 5:34-35.
`
`
`
` The DRAM is used during a write access operation to the MLC flash
`
`(highlighted blue). The data to be written to the MLC flash is maintained (or
`
`
`2 Unless otherwise noted, Patent Owner added coloring to the Figures.
`
`6
`
`

`

`IPR2021-01550
`U.S. Patent No. 10,950,300
`
`retained) in the DRAM. Id., 5:59-61. If time permits, the controller performs a data
`
`integrity test on the data that was stored in the MLC. Id., 5:61-64. If the stored data
`
`fails the data integrity test, the address range for the stored data is remapped to a new
`
`location (e.g., the SLC flash). Id., 5:64-67.
`
`Figures 3A and 3B of the ’300 Patent show in more detail how the DRAM is
`
`used during the write access operation and data integrity test.
`
`7
`
`

`

`IPR2021-01550
`U.S. Patent No. 10,950,300
`
`
`
`
`Id., FIG. 3A. The write access operation begins at step 100. Id., 6:17-20. In step
`
`102, the data to be written to the MLC is read from the DRAM into the memory of
`
`the device controller. Id., 6:15-22. In step 104, the controller obtains the logical and
`
`8
`
`

`

`IPR2021-01550
`U.S. Patent No. 10,950,300
`
`physical address ranges for the data to be written to the MLC. Id., 6:22-25. In step
`
`106, the controller combines the data from the DRAM with data from the MLC. Id.,
`
`6:25-27. In step 108, the controller erases the physical address range where the data
`
`is being written. Id., 6:27-28. Finally, in step 110, the combined data is written to
`
`the MLC flash. Id., Fig. 3A (step 110), 6:28-30.
`
`The data integrity test begins at the bottom of Figure 3A and continues to
`
`Figure 3B. In step 112, the data that was stored in the MLC (“the stored data”) is
`
`read into controller’s memory. Id., 6:30-32. In step 114, the stored data is compared
`
`to the data that was retained in the DRAM (“the retained data”). Id., 6:33-38.
`
`9
`
`

`

`IPR2021-01550
`U.S. Patent No. 10,950,300
`
`
`Id., FIG. 3B. If there is a match, the data was successfully stored in the MLC. Id.,
`
`6:38-40. If not the retained data is written to another location (e.g., SLC). Id., 6:40-
`
`
`
`44.
`
`10
`
`

`

`IPR2021-01550
`U.S. Patent No. 10,950,300
`
`During prosecution, the Examiner acknowledge in the Reasons for Allowance
`
`section of the Notice of Allowance that the use of RAM during the data integrity test
`
`was patentable over the prior art. Ex. 1008, 179-180 (“This limitation requires that
`
`the nonvolatile memory element ‘retain’ the stored data . . .”), 210 (referencing
`
`Applicant’s Remarks § IV pp. 8-9). Furthermore, the Examiner considered prior art
`
`that mentioned RAM, and determined that it did not use RAM like Dr. Rao (inventor
`
`of the ’300 Patent) did and that it would not have been obvious to do so. Id., 210-
`
`211 (citing U.S. 7,505,338, see 5:51-53).
`
`D. Hot and Cold Data
`
`One can distinguish between “hot” blocks (which receive more frequent
`
`writes), and “cold” blocks (which receive less frequent writes). Ex. 1007, 6:53-59.
`
`Because SLC has greater endurance, “hot” blocks can be allocated to SLC to
`
`increase the lifetime of the system. Id. “Cold” blocks, on the other hand, can be
`
`allocated to MLC to take advantage of its higher density storage. Ex. 2014, ¶35.
`
`E.
`
`Independent Claims 1 and 12
`
`In claim 1, the system for storing data comprises three types of memory: (1)
`
`nonvolatile MLC memory; (2) nonvolatile SLC memory; and (3) random access
`
`volatile memory (highlighted red) (hereinafter, RAM). The RAM is a key feature
`
`of the invention and it permeates most of the elements of the claim ([1.A], [1.E]-
`
`11
`
`

`

`IPR2021-01550
`U.S. Patent No. 10,950,300
`
`[1.H]). As discussed above, the RAM is particularly important to the “write access
`
`operation” in [1.G] and the “data integrity test” in [1.H].
`
`[1.PRE] A system for storing data comprising:
`
`Claim 1
`
`[1.A] memory space containing volatile memory space and nonvolatile
`
`memory space, wherein the nonvolatile memory space includes both
`
`multilevel cell (MLC) memory space and single level cell (SLC)
`
`memory space;
`
`[1.B]
`
`at least one controller to operate memory elements and associated
`
`memory space;
`
`[1.C]
`
`at least one MLC nonvolatile memory element that can be mapped into
`
`the MLC memory space;
`
`[1.D]
`
`at least one SLC nonvolatile memory element that can be mapped into
`
`the SLC memory space;
`
`[1.E]
`
`at least one random access volatile memory;
`
`[1.F]
`
`an FTL flash translation layer, wherein the at least one controller, or
`
`FTL, or a combination of both maintain an address table in one or more
`
`of the memory elements and random access volatile memory;
`
`[1.G]
`
`the controller controlling access of the MLC and SLC nonvolatile
`
`memory elements and the random access volatile memory for storage
`
`of data therein, the controller, in at least a Write access operation to the
`
`MLC nonvolatile memory element, operable to store data in the MLC
`
`12
`
`

`

`IPR2021-01550
`U.S. Patent No. 10,950,300
`
`
`nonvolatile memory element and retain such stored data in the
`
`random access volatile memory;
`
`[1.H]
`
`the controller performing a data integrity test on stored data in the
`
`MLC nonvolatile memory element after at least a Write access
`
`operation is performed thereon by comparing the stored data to the
`
`retained data in the random access volatile memory;
`
`[1.I]
`
`wherein the address table maps logical and physical addresses
`
`adaptable to the system, wherein the mapping is performed as
`
`necessitated by the system to maximize lifetime, and wherein the
`
`mapping maps blocks, pages, or bytes of data in either volatile or
`
`nonvolatile, or both, memories; and
`
`[1.J]
`
`wherein a failure of the data integrity test performed by the controller
`
`results in a remapping of the address space to a different physical range
`
`of addresses and transfer of data corresponding to the stored data to
`
`those remapped physical addresses from those determined to have
`
`failed the data integrity test to achieve enhanced endurance.
`
`During the write operation in [1.G], the controller “store[s] data in the MLC
`
`nonvolatile memory element” (highlighted blue). The controller also retains a copy
`
`of the “stored data” in the RAM (highlighted red). In [1.H], this copy is referred to
`
`as the “retained data in the random access volatile memory.”
`
`The controller performs the data integrity test in [1.H] by comparing the
`
`“stored data” (highlighted blue) to the “retained data in the [RAM]” (highlighted
`
`red). In the Reasons for Allowance, the Examiner indicated that using the RAM for
`
`13
`
`

`

`IPR2021-01550
`U.S. Patent No. 10,950,300
`
`the compare operation was not taught or suggested by the prior art. Ex. 1008, 179-
`
`180, 210. Like claim 1, claim 12 recites a RAM that is used for a “write access
`
`operation” (see [1.G]) and a “data integrity test” (see [1.H]).
`
`[12.PRE] A system for storing data comprising:
`
`Claim 12
`
`[12.A] memory space containing volatile memory space and nonvolatile
`
`memory space, wherein the nonvolatile memory space includes both
`
`multilevel cell (MLC) memory space and single level cell (SLC)
`
`memory space;
`
`[12.B]
`
`at least one controller to operate memory elements and associated
`
`memory space, and to maintain an address table in one or more of the
`
`memory elements;
`
`[12.C]
`
`at least one MLC nonvolatile memory element that can be mapped into
`
`the MLC memory space;
`
`[12.D]
`
`at least one SLC nonvolatile memory element that can be mapped into
`
`the SLC memory space;
`
`[12.E]
`
`at least one random access volatile memory;
`
`[12.F]
`
`the controller controlling access of the MLC and SLC nonvolatile
`
`memory elements and the random access volatile memory for storage
`
`of data therein, the controller, in at least a Write access operation to the
`
`MLC nonvolatile memory element, operable to store data in the MLC
`
`nonvolatile memory element and retain such stored data in the
`
`random access volatile memory;
`
`14
`
`

`

`IPR2021-01550
`U.S. Patent No. 10,950,300
`
`
`[12.G]
`
`the controller performing a data integrity test on stored data in the
`
`MLC nonvolatile memory element after at least a Write access
`
`operation is performed thereon by comparing the stored data to the
`
`retained data in the random access volatile memory;
`
`[12.H] wherein the address table maps logical and physical addresses
`
`adaptable to the system, wherein the mapping is performed as
`
`necessitated by the system to maximize lifetime, and wherein the
`
`mapping maps blocks, pages, or bytes of data in either volatile or
`
`nonvolatile, or both, memories; and
`
`[12.I] wherein a failure of the data integrity test performed by the controller
`
`results in a remapping of the address space to a different physical range
`
`of addresses and transfer of data corresponding to the stored data to
`
`those remapped physical addresses from those determined to have
`
`failed the data integrity test to achieve enhanced endurance.
`
`
`
`III. PERSON OF ORDINARY SKILL IN THE ART
`
`For purposes of this proceeding only, Patent Owner adopts Petitioner’s
`
`definition of a person of ordinary skill in the art (POSA). Petition, 27; Ex. 2014,
`
`¶20-23.
`
`IV. OVERVIEW OF THE ALLEGED PRIOR ART
`
`A. Dusija (Ex. 1010)
`
`Dusija is a U.S. patent application that was published in 2011. Dusija
`
`addresses a problem that occurs with flash memory—as it ages, its error rate
`
`15
`
`

`

`IPR2021-01550
`U.S. Patent No. 10,950,300
`
`increases, which requires a resource intensive error correction code (ECC) to correct
`
`errors. Ex. 1010, [0012-0017]; Ex. 2014, ¶¶44-60. As Dusija explains, in order to
`
`ensure data integrity in such situations, a complex, computationally intensive ECC
`
`is utilized which results in memory performance degradation. Ex. 1010, [0014]. To
`
`address this problem, Dusija “provid[es] a mechanism to control and limit the errors
`
`arising after writing to high density memory [i.e., MLC] … and a second chance to
`
`rewrite data with less error if the copy in the high density memory has excessive
`
`errors.” Id., [0024]. By using the disclosed mechanism the ECC complexity is
`
`reduced and an “advantage is gained at the slight expense of an additional post-write
`
`read and infrequent additional rewrites to a less [sic, lower] density memory portion
`
`[i.e., SLC].” Id.
`
`In contrast to the ’300 Patent, the SLC memory in Dusija is primarily used for
`
`enhancing memory life by starting an error management process “after the memory
`
`has aged to a predetermined amount.” Id., Abstract. Hence, the primary teaching of
`
`Dusija is to extend memory life when the memory is aging, and not slow it down by
`
`doing the “error management … when a memory is new with little or no errors.” Id.
`
`Thus, Dusija teaches a MLC memory chip where a nominal amount of SLC memory
`
`is deployed only late in the lifetime of the MLC memory in order to avoid ECC
`
`processing at the controller ASIC. Id., [0016], [0024], [0155].
`
`16
`
`

`

`IPR2021-01550
`U.S. Patent No. 10,950,300
`
`To reduce ECC complexity and increase memory performance, Dusija
`
`describes a flash memory device 90 including a controller ASIC chip 102
`
`(highlighted purple) and a memory chip 100 (highlighted blue).
`
`
`
`Ex. 1010, FIG. 1, [0016] (“the controller ASIC chip”), [0059] (“controller 102”),
`
`[0106] (“the controller ASIC chip”). The memory chip includes an on-chip control
`
`circuit 110 with state machine 112. The memory chip also includes input/output
`
`(I/O) circuits, data latches (highlighted yellow), sense modules, and a memory array
`
`(highlighted darker blue). Ex. 1010, [0059]. In contrast to the ’300 Patent, there is
`
`no mention of DRAM (or even RAM) in the memory chip 100, controller chip 102,
`
`or anywhere else in the flash memory device 90. In fact, the only time that Dusija
`
`17
`
`

`

`IPR2021-01550
`U.S. Patent No. 10,950,300
`
`mentions RAM is in the “Background of the Invention,” when Dusija is
`
`distinguishing its purported invention from RAM. Id., [0003].
`
`After a write access command, the ECC Processor 62 can check an error
`
`detection code (EDC) to see whether data was written correctly to the flash memory
`
`array 200. Id., [0087-0088].3 Dusija teaches that performing the ECC to correct the
`
`worst-case number of bits would be burdensome in terms of processing time as well
`
`as chip area, and the extra circuitry for this would not be well justified on the
`
`controller ASIC chip.
`
`Using ECC to correct a worst-case number of error bits will
`
`consume a great amount of processing time. The more bits it has
`
`to correct, the more computational time is required. The memory
`
`performance will be degraded. Additional dedicated hardware
`
`may be implemented to perform the ECC in a reasonable amount
`
`of time. Such dedicated hardware can take up a considerable
`
`amount of space on the controller ASIC chip. Moreover, for
`
`most of the life time of the device, the ECC is only marginally
`
`
`3 This error detection is different from the alleged comparison in the Petition. There
`
`Petitioner wrongly alleged that the comparison is between sets of data that are in the
`
`same RAM, and Petitioner has not alleged that the ECC meets this requirement.
`
`Petition, 25-27, 48-50.
`
`18
`
`

`

`IPR2021-01550
`U.S. Patent No. 10,950,300
`
`
`utilized, resulting in its large over-heads being wasted and no real
`
`benefits.
`
`Ex. 1010, [0016] (emphasis added). This is why Dusija expressly teaches that any
`
`error checking should be performed by conducting a comparison at the data latches
`
`on the flash memory chip, not at the controller chip. Id., [0112], [0135-0136]. This
`
`also eliminates the need to “toggle” the data out to the controller (a different chip)
`
`and therefore “much time can be saved.” Id., [0136]. By performing the error
`
`detection on the memory chip, it is possible to increase the performance of the flash
`
`memory device and eliminate the need for dedicated area-intensive ECC hardware
`
`on the controller chip. Id., [0016], [0136].
`
`The data latches compare the data that was written to the MLC portion of the
`
`memory array with a copy of the data that was cached in the SLC portion of the
`
`memory array. Id., [0020-0022]. As seen in Figure 1 above, and as taught in [0022],
`
`the data latches are coupled to the flash memory array and both sets of data are
`
`already in the flash memory. Further, [0076] and [0088] teach that the output of the
`
`sense amplifier 490, residing in sense module 480, is stored in the latches 430. This
`
`streamlines the comparison process and achieves Dusija’s objectives of reducing
`
`processing time and overhead.
`
`The memory array 200 is shown in more detail in Figures 14A and 14B. As
`
`seen below, the memory array 200 comprises a first portion 410 that is “more robust
`
`19
`
`

`

`IPR2021-01550
`U.S. Patent No. 10,950,300
`
`but lower density storage” (i.e., SLC) and a second portion 420 that is “less robust
`
`but higher density storage” (i.e., MLC) (highlighted blue).
`
`
`
`As indicated above, the memory chip uses its on-chip control circuitry 110 to
`
`write data to the second portion (MLC). Id., [0059, 0111]. If the stored data has an
`
`acceptable number of errors, then the stored copy in the MLC becomes the “valid”
`
`copy. Id., [0113], [0129]. Otherwise, the data is rewritten to the first portion (SLC).
`
`Id.
`
`When the data is written to the MLC, the flash memory device 90 can check
`
`for errors one of two ways. Id., [0112]. Either the flash memory device can use the
`
`20
`
`

`

`IPR2021-01550
`U.S. Patent No. 10,950,300
`
`ECC Processor at the controller to check the “EDC portion of the ECC.” Id. Dusija
`
`strongly recommends against this approach. Id., [0016], [0136]. Alternately, the
`
`flash memory device can check for errors on the memory chip by using the data
`
`latches and locally cached data. Id., [0112], [0135]. Dusija strongly recommends
`
`this approach because it improves performance of the flash memory device by
`
`reducing overhead and eliminating the need to toggle data out to the controller 102,
`
`which is on a separate ASIC.
`
`According to another preferred embodiment, the memory array
`
`is provided with a set of data latches on an integrated circuit chip, the
`
`checking of the error bits in the first copy is accomplished by loading
`
`the first copy and the cached copy into the set of data latches and
`
`making a comparison at the set of data latches.
`
`By not making the comparison at the controller, the data does not
`
`have to be toggled out to the controller, much time can be saved. Figure
`
`1 shows the data latches 430, which is on-chip, for the data comparison
`
`to take place.
`
`Id., [0135-0136] (emphasis added); see also id., [0012].
`
`According to Dusija, another advantage of caching the data locally in the
`
`memory array is that if there is an error writing to the MLC portion of the memory
`
`array, the cached copy can become the “valid” copy. Id., [0129]. Dusija uses the
`
`embodiment shown in Figure 16A to further advocate for caching the data locally i