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`UNITED STATES PATENT AND TRADEMARK OFFICE
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`MICRON TECHNOLOGY, INC.,
`Petitioner,
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`v.
`
`VERVAIN, LLC,
`Patent Owner.
`
`
`
`IPR2021-01550
`U.S. Patent No. 10,950,300
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`PATENT OWNER’S CORRECTED PRELIMINARY RESPONSE
`PURSUANT TO 35 U.S.C. § 313 AND 37 C.F.R. § 42.107
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`

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`TABLE OF CONTENTS
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`
`
`EXHIBIT LIST ......................................................................................................... vi
`I.
`INTRODUCTION ........................................................................................... 1
`II. OVERVIEW OF THE ’300 PATENT AND THE CHALLENGED
`CLAIMS .......................................................................................................... 4
`A.
`SLC and MLC Flash ............................................................................. 5
`B. Address Table ........................................................................................ 7
`C. Data Integrity Tests ............................................................................... 7
`D. Hot and Cold Data ............................................................................... 12
`E.
`Independent Claims 1 and 12 .............................................................. 12
`III. CLAIM CONSTRUCTION .......................................................................... 16
`A.
`“data integrity test” (claims 1 and 12) ................................................. 17
`B.
`“comparing the stored data to the retained data in the random
`access volatile memory” (claims 1 and 12) ......................................... 19
`“periodically” (claim 10) ..................................................................... 23
`C.
`IV. OVERVIEW OF THE CITED PRIOR ART ................................................ 24
`A. Dusija ................................................................................................... 24
`B.
`Paley .................................................................................................... 33
`REASONS FOR DENYING INSTITUTION ............................................... 36
`A.
`The Board Should Exercise its Discretion and Deny Institution ........ 36
`1.
`Factor 1: No Motion to Stay has Been Filed and the
`District Court is Unlikely to Grant a Stay ................................. 38
`Factor 2: The Board Will Issue a FWD Almost Three
`Months after the Parallel District Court Trial ........................... 38
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`V.
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`2.
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`i
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`3.
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`4.
`
`B.
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`Factor 3: The Parties and District Court Have Invested—
`and Will Continue to Invest—Significant Time into the
`District Court Litigation ............................................................ 39
`Factor 4: There is Significant Overlap Between This
`Proceeding and the Parallel District Court Case ....................... 40
`Factor 5: The Parties are the Same in Both Proceedings .......... 43
`5.
`Factor 6: The Merits of the Petition are Not Strong ................. 43
`6.
`Additional Considerations ........................................................ 43
`7.
`The Petition Does Not Establish That Independent Claims 1 and
`12 Would Have Been Obvious over Dusija (Grounds 1 and 2) .......... 44
`1.
`The Petition fails to identify even one prior art reference
`that uses RAM for the data integrity test, and Petitioner’s
`conclusory arguments are impermissible hindsight .................. 45
`The Petition fails to demonstrate motivation to modify
`Dusija to add RAM as cache, when Dusija teaches that
`the relevant data is cached in flash memory ............................. 51
`The Petition fails to demonstrate motivation to modify
`Dusija to add RAM at the controller chip for the data
`integrity test, when Dusija teaches that the alleged
`comparison is performed on the flash memory chip ................ 54
`The Petition fails to demonstrate motivation to modify
`Dusija to add RAM at the controller chip for the data
`integrity test, when it would render Dusija inoperable ............. 57
`The Petition fails to demonstrate motivation and
`reasonable expectation of success to modify Dusija to
`add RAM at the controller for the data integrity test,
`when Dusija teaches the comparison is performed on the
`flash memory chip in order to save time and avoid
`toggling data out to the controller ............................................. 58
`VI. CONCLUSION .............................................................................................. 62
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`2.
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`3.
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`4.
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`5.
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`ii
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`
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`TABLE OF AUTHORITIES
`
`Page(s)
`
`
`CASES
`Acumed LLC v. Stryker Corp.,
`483 F.3d 800 (Fed. Cir. 2007) ............................................................................ 20
`Apple Inc. v. Fintiv, Inc.,
`IPR2020-00019, Paper 11 (PTAB Mar. 20, 2020) ......................................passim
`Arendi S.A.R.L. v. Apple Inc.,
`832 F.3d 1355 (Fed. Cir. 2016) .......................................................................... 47
`AstraZeneca AB v. Mylan Pharms. Inc.,
`19 F.4th 1325 (Fed. Cir. 2021) ........................................................................... 51
`Bicon, Inc. v. Straumann Co.,
`441 F.3d 945 (Fed. Cir. 2006) ............................................................................ 18
`Broadcom Corp. v. Emulex Corp.,
`732 F.3d 1325 (Fed. Cir. 2013) .......................................................................... 47
`Cuozzo Speed Techs., LLC v. Lee,
`136 S. Ct. 2131 (2016) ........................................................................................ 36
`DePuy Spine, Inc. v. Medtronic Sofamor Danek, Inc.,
`469 F.3d 1005 (Fed. Cir. 2006) .......................................................................... 17
`E-One Inc. v. Oshkosh Corp.,
`IPR2019-00162, Paper 16 (PTAB June 5, 2019) ............................................... 43
`Harmonic Inc. v. Avid Tech., Inc.,
`815 F.3d 1356 (Fed. Cir. 2016) .......................................................................... 36
`Hill-Rom Servs., Inc. v. Stryker Corp.,
`755 F.3d 1367 (Fed. Cir. 2014) .................................................................... 17, 19
`In re Gurley,
`27 F.3d 551 (Fed. Cir. 1994) .............................................................................. 59
`In re Kotzab,
`217 F.3d 1365 (Fed. Cir. 2000) .......................................................................... 59
`
`iii
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`

`

`
`
`Innova/Pure Water, Inc. v. Safari Water Filtration Sys., Inc.,
`381 F.3d 1111 (Fed. Cir. 2004) .......................................................................... 18
`Intel Corp. v. VLSI Tech. LLC,
`IPR2019-01192, Paper 15 (PTAB Jan. 9, 2020) ................................................ 37
`KSR Int’l Co. v. Teleflex Inc.,
`550 U.S. 398 (2007) ........................................................................................ 4, 59
`MEMS Tech. Berhad v. Int'l Trade Comm’n,
`447 F. App’x 142 (Fed. Cir. 2011) ..................................................................... 54
`Merck & Co. v. Teva Pharm. USA, Inc.,
`395 F.3d 1364 (Fed. Cir. 2005) .......................................................................... 18
`Phillips v. AWH Corp.,
`415 F.3d 1303 (Fed. Circ. 2005) (en banc) .................................................. 16, 17
`Samsung Elecs. Co. Ltd., v. Clear Imaging Research, LLC
`IPR2020-01400, Paper 13 (PTAB Feb. 3, 2021) ................................................ 41
`SK Innovation Co. LTD., v. LG Chem, LTD.,
`IPR2020-01239, Paper 14 (PTAB Jan. 12, 2021) .............................................. 43
`Sotera Wireless, Inc. v. Masimo Corp.,
`IPR2020-01019, Paper 12 (PTAB Dec. 1, 2020) ............................................... 41
`Stewart-Warner Corp. v. Pontiac,
`767 F.2d 1563 (Fed. Cir. 1985) .................................................................... 49, 51
`SynQor, Inc. v. Artesyn Techs., Inc.,
`709 F.3d 1365 (Fed. Cir. 2013) .......................................................................... 22
`TQ Delta, LLC v. Cisco Sys., Inc.,
`942 F.3d 1352 (Fed. Cir. 2019) .......................................................................... 59
`STATUTES
`35 U.S.C. § 313 .......................................................................................................... 1
`35 U.S.C. § 314 .................................................................................................passim
`35 U.S.C. § 315(e)(2) ......................................................................................... 41, 42
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`iv
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`OTHER AUTHORITIES
`OTHER AUTHORITIES
`37 C.F.R. § 42.4(a) ................................................................................................... 37
`37 CLE.R. § 42.4(a)ccccccccscsssecsccssssscssucscsssssccessusscssussesssssscsssuesessnseesssecsersueeesssseeesssesees 37
`37 C.F.R. § 42.107 ..................................................................................................... 1
`37 CAFR. § 42.107 ccccccsscsssesccsssesscssucscssssccsssusscssussecssssscersuesessnssesssseseersutsersnetecssseeeten 1
`37 C.F.R. § 100(b) ................................................................................................... 16
`37 CAF.R. § 100(D)ceccsccsccssecscssssescsssesscssusecessssecessucscssnseccssssscessusessnssecsssseeatsneessaseces 16
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`v
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`EXHIBIT LIST
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`Exhibit No.
`2001
`
`Description
`Declaration of Dr. Sunil Khatri
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`2002
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`2003
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`2004
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`2005
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`2006
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`2007
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`2008
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`2009
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`2010
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`2011
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`2012
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`2013
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`
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`Chen et al., Ultra MLC Technology Introduction, Advantech
`Technical White Paper (Oct. 5, 2012) (“Chen”)
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`Excerpts from Micheloni et al., Inside NAND Flash Memories (1st ed.
`2010) (“Micheloni”)
`
`Intentionally omitted
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`Microsoft Computer Dictionary definition for “data integrity”
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`Hargrave’s Communications Dictionary definition for “data integrity”
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`https://www.law360.com/articles/1381597/albright-says-he-ll-very-
`rarely-put-cases-on-hold-for-ptab
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`Docket Sheet for Case. No. 6:21-cv-487-ADA; Vervain v. Micron
`Technology et al.; U.S. District Court, Western District of Texas.
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`Exhibit D-3, Invalidity Claim Chart for the ’300 Patent based on U.S.
`Patent Application Pub. No. 2011/0099460 (“Dusija”)
`
`Exhibit D-18, Invalidity Claim Chart for the ’300 Patent based on
`U.S. Patent Application Pub. No. US 2008/0140918 (“Sutardja”)
`
`Intentionally omitted
`
`Intentionally omitted
`
`Micron’s Preliminary Invalidity Contentions for U.S. Patent Nos.
`8,891,298; 9,196,385; 9,997,240; and 10,950,300; Case. No. 6:21-cv-
`487-ADA; Vervain v. Micron Technology et al.; U.S. District Court,
`Western District of Texas.
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`vi
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`I.
`
`INTRODUCTION
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`
`
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`U.S. Patent 10,950,300
`IPR2021-01550
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`Vervain, LLC (“Patent Owner” or “Vervain”) submits this preliminary
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`response in accordance with 35 U.S.C. § 313 and 37 C.F.R. § 42.107, responding to
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`the Petition for Inter Partes Review (“Petition”) of U.S. Patent No. 10,950,300 (the
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`“’300 Patent”) filed by Micron Technology, Inc. (“Micron” or “Petitioner”). Micron
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`petitions for inter partes review of claims 1-12 of the ’300 Patent, which is owned
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`by Vervain. Micron’s Petition includes two grounds. Both grounds rely primarily
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`on U.S. Patent App. Pub. No. 2011/0099460 (“Dusija”). The Board should decline
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`institution for the following reasons.
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`First, the Board should exercise its discretion and deny institution under 35
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`U.S.C. § 314(a). The parallel district court case, which involves four patents and not
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`just the one patent at issue here, has moved beyond its infancy and is progressing at
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`a steady clip. Before the institution decision is due in this proceeding, the district
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`court will have already issued an order on a substantive motion and held the
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`Markman. The parties will have spent three months in fact discovery—almost
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`halfway through the allotted fact discovery period. And trial in the parallel district
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`court case is scheduled for three months before the final written decision deadline
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`here. Furthermore, Micron asserts overlapping prior art in the parallel district court
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`litigation both outright and under the guise of being system art, but refuses to agree
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`to any meaningful estoppel if there is an institution here. On these facts, the
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`advanced parallel district court proceeding should proceed and this Petition should
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`U.S. Patent 10,950,300
`IPR2021-01550
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`be denied under 35 U.S.C. § 314(a).
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`Second, the Board should deny institution on both Grounds because Dusija
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`does not teach or suggest elements [G] and [H] of claim 1 (hereinafter, [1.G]/[1.H]),
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`and elements [F] and [G] of claim 12 (hereinafter, [12.F]/[12.G]). Independent
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`claims 1 and 12 require more than just random access memory (RAM). They also
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`require that RAM is used during a “write access operation” to retain a copy of the
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`data that is stored in the MLC memory. Additionally, they require that the RAM is
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`used during the “data integrity test,” when this retained data is compared to the stored
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`data. The specification confirms that using the RAM during the data integrity test is
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`a key feature of Dr. Rao’s invention, and during prosecution, the Examiner indicated
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`in his Reasons for Allowance that this feature was not taught or suggested by the
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`prior art. Therefore, it is not surprising that Petitioner has not presented even one
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`prior art reference that uses RAM during the data integrity test. To now argue that
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`this feature would have been obvious is impermissible hindsight.
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`Third, the only time that Dusija mentions RAM is in the “Background of the
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`Invention” when it distinguished its purported invention from using RAM. Dusija
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`does not teach or suggest using RAM during a write access operation or data
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`integrity test, like Dr. Rao did. In Dusija, the relevant data is cached in a flash
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`memory array on the flash memory chip, and the alleged comparison is performed
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`by data latches that are coupled with, and adjacent to, the flash memory array. In
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`U.S. Patent 10,950,300
`IPR2021-01550
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`fact, the whole point of Dusija was to streamline the operations by consolidating
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`them on the flash memory chip.
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`Fourth, the Petition acknowledges that there is no RAM on Dusija’s flash
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`memory chip. Instead the Petition asserts that Dusija’s cache could be RAM at the
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`controller. But the alleged data integrity test is performed by data latches that are
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`coupled with, and adjacent to, the flash memory array on the flash memory chip.
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`Therefore, the cache cannot be on the controller chip, as Petitioner suggests. A
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`POSA would have known that Dusija’s cache (in this case, the flash memory) needs
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`to be on the same chip physically close to where it is utilized (that is, the data latches)
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`in order to achieve Dusija’s goals of improving delay performance and reducing
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`cost. Moving the cache to RAM, as Petitioner suggests, would defeat these goals.
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`Fifth, using RAM during the write access operation and data integrity test
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`would render Dusija inoperable. In Dusija, when the data written to the MLC fails
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`the data integrity test, the copy stored in the SLC becomes the “valid” copy. If the
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`copy is stored in RAM, as Petitioner suggests, the copy cannot become the “valid”
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`copy because RAM is a volatile memory. If the power to the RAM is turned off, the
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`information is lost forever.
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`Sixth, Dusija teaches that the comparison is performed on the flash memory
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`chip in order to save time and avoid toggling data out to the controller. This confirms
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`that the data is cached on the flash memory chip, and there would have been no
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`U.S. Patent 10,950,300
`IPR2021-01550
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`motivation to modify Dusija to put it elsewhere. Dusija teaches away from using
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`RAM, and to use it would not only slow down the resulting design, but it would
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`render it inoperable. Moreover, Petitioner presents no evidence demonstrating that
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`the proposed modification would have a reasonable expectation of success (which it
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`cannot for the reasons above). Therefore, Petitioner’s obviousness arguments fall
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`far short of the Supreme Court’s requirements in KSR.
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`Accordingly, Patent Owner requests that the Board deny institution of
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`Micron’s Petition.
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`II. OVERVIEW OF THE ’300 PATENT AND THE CHALLENGED
`CLAIMS
`The ’300 Patent, entitled “Lifetime Mixed Level Non-Volatile Memory
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`System” was filed on June 12, 2018 and has an effective filing date of July 19, 2011.
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`Ex. 1007. Dr. Mohan Rao is the sole named inventor of the ’300 Patent.
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`At a high level, the ’300 Patent describes, among other things, a reliable flash
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`memory storage system combining both single-level cell (SLC) and multi-level cell
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`(MLC) non-volatile memories.1 Ex. 1007, Abstract. Prior to the ’300 Patent, Dr.
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`1 Non-volatile memories can store information even after the system is powered off.
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`Flash memory is a specific type of non-volatile memory, where data is stored in
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`“blocks” of “pages.” Ex. 1007, 2:52-59.
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`Rao recognized that “MLC NAND flash SSDs are slowly replacing and/or
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`U.S. Patent 10,950,300
`IPR2021-01550
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`coexisting with SLC NAND flash in newer SSD systems” because “MLC flash
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`memory is less expensive than SLC flash memory[] on a cost per bit basis.” Id.,
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`3:36-37, 5:51-54. However, while “MLC NAND flash enjoys greater density than
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`SLC NAND flash” it comes “at the cost of a decrease in access speed and lifetime
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`(endurance).” Id., 3:41-44. As a result, various hybrid systems combining SLC and
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`MLC (among others) are taught in the ‘300 Patent, to combine the benefits of both
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`types of non-volatile flash storage at a low cost. Id., 3:62-4:2.
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`The ’300 Patent addresses improvements and solutions for managing the
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`writing of data optimally for improved reliability and lifetime (endurance) of such
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`hybrid memory systems. Id., 3:62-4:2. Specifically, the Challenged Claims are
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`directed to specific techniques for efficiently using SLC and MLC flash to improve
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`the overall performance of the memory. Id., claim 1. For example, if data stored in
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`the MLC fails a data integrity test then it is transferred to higher-performance SLC
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`or less-used MLC. Id. By doing so, the number of errors is reduced, and overall
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`endurance of the memory is increased. Ex. 1007, 3:67-4:2.
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`A.
`SLC and MLC Flash
`Single level cell (SLC) memory stores 1 bit per cell, and multiple level cell
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`(MLC) memory stores more than 1 bit per cell. Ex. 1007, 2:17-20. As noted above,
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`there are pros and cons to SLC and MLC flash. In general, SLC is faster and less
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`prone to errors, but requires more space and power to store a given amount of data.
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`U.S. Patent 10,950,300
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`Id., 1:57-63. The opposite is true of MLC. MLC flash is slower and more prone to
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`errors, but stores data more densely with less power consumption. Id., 3:41-44.
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`SLC and MLC flash memories both use the same type of transistor called a
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`floating gate transistor. Id., 3:50-53. They both store a charge in the floating gate
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`of each transistor (cell), which changes the threshold voltage of the transistor. The
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`memory uses the threshold voltage to determine what bit, or bits, were stored in the
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`transistor. The MLC cell in the figure below illustrates threshold voltages for a 2-
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`bit MLC cell.
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`Ex. 2002, 3.
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`
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`The primary difference between SLC and MLC is what data each threshold
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`voltage represents. With SLC flash, the transistor stores only a 1 or 0, so a wide
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`range of threshold voltages can be allotted to a single bit. Ex. 1007, 3:38-39. This
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`allows for faster and more reliable memory access. On the other hand, MLC flash
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`must be slowly and carefully programmed to a narrower, more precise range of
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`threshold voltages, with each threshold voltage range representing a specific pair of
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`bits (see figure above, which shows four pairs of bits—11, 10, 01, and 00—
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`U.S. Patent 10,950,300
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`corresponding to smaller ranges of threshold voltages compared to the SLC). Ex.
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`1007, 3:39-41.
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`B. Address Table
`To provide wear leveling, garbage collection, and bad block management, a
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`translation layer is used to map logical addresses to actual physical memory
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`locations. Ex. 2003, 9-11; Ex. 1007, 3:3-35. As part of this translation layer, “tables
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`are widely used in order to map sectors and pages from logical to physical.” Ex.
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`2003, 9; Ex. 1007, 3:19-23. These tables map logical blocks to physical blocks. Ex.
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`2003, 9-11; Ex. 1007, 3:19-23. Using a “block” or similar granularity is important,
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`since flash memory is arranged so that when erasing and rewriting data, a whole
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`block is “erased together.” Ex. 2003, 6; Ex. 1007, 2:59-3:2. Dr. Rao explained that
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`“[t]he address ranges within the translation table will assume some minimum
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`quantum, such as, for example, one block…” Ex. 1007, 5:54-58. Dr. Rao further
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`explained that memory is written and mapped on the granularity of a “quantum,”
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`such as a block or page. Id., 5:54-58; Figs. 3A-B.
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`C. Data Integrity Tests
`As mentioned above, when data is stored in MLC memory, it is more prone
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`to errors, and some data is more prone to errors than other data. One reason for this
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`is that the threshold voltage intervals for MLC memory are smaller than the intervals
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`for SLC memory, and thus, errors can occur when writing or reading the data. Ex.
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`U.S. Patent 10,950,300
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`2001, ¶ 33. Errors can also be caused by the data stored in neighboring cells. Id. A
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`data integrity test is a test that checks the integrity of the data (i.e., whether errors
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`have occurred). This test can be run immediately after data is written, or at a later
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`time. If the test reveals a problem such as corrupt data, the data can be remapped to
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`SLC (which is less error-prone), and the address table is modified accordingly. Ex.
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`1007, 4:30-36. Alternately, MLC data can be remapped to other MLC blocks, and
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`the address table is then modified accordingly. Id., 3:13-35.
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`The ’300 Patent claims a particular way of writing the data to the MLC and
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`performing the data integrity test. Dr. Rao recognized that there were advantages in
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`using a DRAM to assist with the both the write access operation and data integrity
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`test. As seen in Figure 1 below, the controller (highlighted purple) controls a DRAM
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`(highlighted red).
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`U.S. Patent 10,950,300
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`Ex. 1007, Fig. 1 (annotations added2), 5:34-35. The DRAM is used during a write
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`access operation to the MLC flash (highlighted blue). The data to be written to the
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`MLC flash is maintained (or retained) in the DRAM. Id., 5:59-61. If time permits,
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`the controller performs a data integrity test on the data that was stored in the MLC.
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`Id., 5:61-64. If the stored data fails the data integrity test, the address range for the
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`stored data is remapped to a new location (e.g., the SLC flash). Id., 5:64-67.
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`2 Unless otherwise noted, Patent Owner added coloring to Figures.
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`U.S. Patent 10,950,300
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`Figures 3A and 3B show in more detail how the DRAM is used during the
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`write access operation and data integrity test.
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`
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`Id., Fig. 3A. The write access operation begins at step 100. Id., 6:17-20. In step
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`102, the data to be written to the MLC is read from the DRAM into the memory of
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`the device controller. Id., 6:15-22. In step 104, the controller obtains the logical and
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`physical address ranges for the data to be written to the MLC. Id., 6:22-25. In step
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`106, the controller combines the data from the DRAM with data from the MLC. Id.,
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`6:25-27. In step 108, the controller erases the physical address range where the data
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`is being written. Id., 6:27-28. Finally, in step 110, the combined data is written to
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`U.S. Patent 10,950,300
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`the MLC flash. Id., Fig. 3A (step 110), 6:28-30.
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`The data integrity test begins at the bottom of Figure 3A and continues to
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`Figure 3B. In step 112, the data that was stored in the MLC (“the stored data”) is
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`read into controller’s memory. Id., 6:30-32. In step 114, the stored data is compared
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`to the data that was retained in the DRAM (“the retained data”). Id., 6:33-38.
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`Id., Fig. 3B. If there is a match, the data was successfully stored in the MLC. Id.,
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`6:38-40. If not the retained data is written to another location (e.g., SLC). Id., 6:40-
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`44.
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`U.S. Patent 10,950,300
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`During prosecution, the Examiner acknowledge in his Reasons for Allowance
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`that the use of RAM during the data integrity test was patentable over the prior art.
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`Ex. 1008, 179-180 (“This limitation requires that the nonvolatile memory element
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`‘retain’ the stored data . . .”), 210 (referencing Applicant’s Remarks § IV pp. 8-9).
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`Furthermore, the Examiner considered prior art that mentioned RAM, and
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`determined that it did not use RAM like Dr. Rao did and that it would not have been
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`obvious to do so. Id., 210-211 (citing U.S. 7,505,338, see 5:51-53).
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`D. Hot and Cold Data
`One can distinguish between “hot” blocks (which receive more frequent
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`writes), and “cold” blocks (which receive less frequent writes). Ex. 1007, 6:53-59.
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`Because SLC has greater endurance, “hot” blocks can be allocated to SLC to
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`increase the lifetime of the system. Id. “Cold” blocks, on the other hand, can be
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`allocated to MLC to take advantage of its higher density storage.
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`E.
`Independent Claims 1 and 12
`In claim 1, the system for storing data comprises three types of memory: (1)
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`nonvolatile MLC memory; (2) nonvolatile SLC memory; and (3) random access
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`volatile memory (highlighted red) (hereinafter, RAM). The RAM is a key feature
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`of the invention and it permeates most of the elements of the claim ([1.A], [1.E]-
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`[1.H]). As discussed above, the RAM is particularly important to the “write access
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`operation” in [1.G] and the “data integrity test” in [1.H].
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`Claim 1
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`U.S. Patent 10,950,300
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`[1.PRE] A system for storing data comprising:
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`[1.A] memory space containing volatile memory space and nonvolatile
`memory space, wherein the nonvolatile memory space includes both
`multilevel cell (MLC) memory space and single level cell (SLC)
`memory space;
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`[1.B]
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`[1.C]
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`[1.D]
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`[1.E]
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`[1.F]
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`[1.G]
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`at least one controller to operate memory elements and associated
`memory space;
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`at least one MLC nonvolatile memory element that can be mapped into
`the MLC memory space;
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`at least one SLC nonvolatile memory element that can be mapped into
`the SLC memory space;
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`at least one random access volatile memory;
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`an FTL flash translation layer, wherein the at least one controller, or
`FTL, or a combination of both maintain an address table in one or more
`of the memory elements and random access volatile memory;
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`the controller controlling access of the MLC and SLC nonvolatile
`memory elements and the random access volatile memory for storage
`of data therein, the controller, in at least a Write access operation to the
`MLC nonvolatile memory element, operable to store data in the MLC
`nonvolatile memory element and retain such stored data in the
`random access volatile memory;
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`[1.H]
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`[1.I]
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`[1.J]
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`U.S. Patent 10,950,300
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`the controller performing a data integrity test on stored data in the
`MLC nonvolatile memory element after at least a Write access
`operation is performed thereon by comparing the stored data to the
`retained data in the random access volatile memory;
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`wherein the address table maps logical and physical addresses
`adaptable to the system, wherein the mapping is performed as
`necessitated by the system to maximize lifetime, and wherein the
`mapping maps blocks, pages, or bytes of data in either volatile or
`nonvolatile, or both, memories; and
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`wherein a failure of the data integrity test performed by the controller
`results in a remapping of the address space to a different physical range
`of addresses and transfer of data corresponding to the stored data to
`those remapped physical addresses from those determined to have
`failed the data integrity test to achieve enhanced endurance.
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`During the write operation in [1.G], the controller “store[s] data in the MLC
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`nonvolatile memory element” (highlighted blue). The controller also retains a copy
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`of the “stored data” in the RAM (highlighted red). In [1.H], this copy is referred to
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`as the “retained data in the random access volatile memory.”
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`The controller performs the data integrity test in [1.H] by comparing the
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`“stored data” (highlighted blue) to the “retained data in the [RAM]” (highlighted
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`red). In the Reasons for Allowance, the Examiner indicated that using the RAM for
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`the compare operation was not taught or suggested by the prior art. Ex. 1008, 179-
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`180, 210. Like claim 1, claim 12 recites a RAM that is used for a “write access
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`U.S. Patent 10,950,300
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`operation” (see [1.G]) and a “data integrity test” (see [1.H]).
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`[12.PRE] A system for storing data comprising:
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`Claim 12
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`[12.A] memory space containing volatile memory space and nonvolatile
`memory space, wherein the nonvolatile memory space includes both
`multilevel cell (MLC) memory space and single level cell (SLC)
`memory space;
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`[12.B]
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`[12.C]
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`[12.D]
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`at least one controller to operate memory elements and associated
`memory space, and to maintain an address table in one or more of the
`memory elements;
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`at least one MLC nonvolatile memory element that can be mapped into
`the MLC memory space;
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`at least one SLC nonvolatile memory element that can be mapped into
`the SLC memory space;
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`[12.E]
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`at least one random access volatile memory;
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`[12.F]
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`the controller controlling access of the MLC and SLC nonvolatile
`memory elements and the random access volatile memory for storage
`of data therein, the controller, in at least a Write access operation to the
`MLC nonvolatile memory element, operable to store data in the MLC
`nonvolatile memory element and retain such stored data in the
`random access volatile memory;
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`[12.G]
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`the controller performing a data integrity test on stored data in the
`MLC nonvolatile memory element after at least a Write access
`operation is performed thereon by comparing the stored data to the
`retained data in the random access volatile memory;
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`[12.H] wherein the address table maps logical and physical addresses
`adaptable to the system, wherein the mapping is performed as
`necessitated by the system to maximize lifetime, and wherein the
`mapping maps blocks, pages, or bytes of data in either volatile or
`nonvolatile, or both, memories; and
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`[12.I] wherein a failure of the data integrity test performed by the controller
`results in a remapping of the address space to a different physical range
`of addresses and transfer of data corresponding to the stored data to
`those remapped physical addresses from those determined to have
`failed the data integrity test to achieve enhanced endurance.
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`
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`III. CLAIM CONSTRUCTION
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`The claims in a post-grant review are construed using the same standard that
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`applies in district court proceedings, as set forth in Phillips v. AWH Corp., 415 F.3d
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`1303 (Fed. Circ. 2005) (en banc); 37 C.F.R. § 100(b) (2019). Claim terms are
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`afforded “their ordinary and customary meaning,” which is “the meaning that the
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`term would have to a person of ordinary skill in the art in question at the time of the
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`invention.”3 Phillips, 415 F.3d at 1312–13. “In determining the meaning of the
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`disputed claim limitation, we look principally to the intrinsic evidence of record,
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`examining the claim language itself, the written description, and the prosecution
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`history, if in evidence.” DePuy Spine, Inc. v. Medtronic Sofamor Danek, Inc., 469
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`F.3d 1005, 1014 (Fed. Cir. 2006) (citing Phillips, 415 F.3d at 1312-17).
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`A.
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`“data integrity test” (claims 1 and 12)
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`This term does not require construction, and it should be given the full scope
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`of its plain meaning. Micron’s proposed construction—“a test conducted after a
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`write to flash to ensure that the da