UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`MICRON TECHNOLOGY, INC.,
`Petitioner,
`
`v.
`
`VERVAIN, LLC,
`Patent Owner.
`
`____________________________
`
`Case No.: IPR2021-01549
`U.S. Patent No. 9,997,240
`Original Issue Date: June 12, 2018
`
`Title: LIFETIME MIXED LEVEL NON-VOLATILE MEMORY SYSTEM
`
`PETITION FOR INTER PARTES REVIEW
`OF U.S. PATENT NO. 9,997,240
`PURSUANT TO 35 U.S.C. §§ 311-319 and 37 C.F.R. § 42
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 9,997,240
`
`III.
`
`V.
`
`I.
`II.
`
` Page
`TABLE OF CONTENTS
`INTRODUCTION ..............................................................................................1
`REQUIREMENTS FOR PETITION FOR INTER PARTES REVIEW .............3
` Grounds for Standing (37 C.F.R. § 42.104(a)) ........................................3
` Notice of Lead and Backup Counsel and Service Information (37
`C.F.R. §§ 42.8(b)(3-4), 42.10(a)) .............................................................3
` Notice of Real Party-in-Interest (37 C.F.R. § 42.8(b)(1))........................5
` Notice of Related Matters (37 C.F.R. § 42.8(b)(2)) .................................5
`
`Fee for Inter Partes Review .....................................................................6
`
`Proof of Service ........................................................................................6
`IDENTIFICATION OF CLAIMS BEING CHALLENGED (37 C.F.R.
`§ 42.104(B)) ........................................................................................................6
`IV. THE BOARD SHOULD NOT EXERCISE ITS DISCRETION TO
`DENY INSTITUTION .......................................................................................7
`
`The Parallel District Court Litigation Does Not Weigh Against
`Institution ..................................................................................................7
`Petitioner’s Arguments Are Not Duplicative ........................................ 12
`
`THE 240 PATENT .......................................................................................... 12
`
`Technological Background ................................................................... 12
`1.
`Volatile, Non-volatile, and Flash Memory ................................. 12
`2.
`Programming Flash, and SLC and MLC Flash Memory
`Cells............................................................................................. 13
`Flash Architecture ....................................................................... 13
`Logical Addresses, Physical Addresses, Bad Block
`Replacement, and Wear Leveling ............................................... 14
`Speed and Wear-Leveling Considerations for MLC and
`SLC Cells .................................................................................... 15
`Operations Based On A Collective Write Count ........................ 16
`6.
`Data Integrity Tests ..................................................................... 17
`7.
`Summary of the 240 Patent’s Disclosure .............................................. 17
`
`3.
`4.
`
`5.
`
`
`
`-i-
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 9,997,240
`
`The 240 Patent’s Prosecution History ................................................... 19
`
`VI. CLAIM CONSTRUCTION ............................................................................ 21
`
`“data integrity test” (claim 1) ................................................................ 21
`
`“on a periodic basis”.............................................................................. 22
` Other Terms ........................................................................................... 22
`VII. HOW THE CHALLENGED CLAIMS ARE UNPATENTABLE ................. 23
`
`Prior Art Overview ................................................................................ 23
`1.
`Dusija .......................................................................................... 23
`2.
`Sutardja ....................................................................................... 24
`3.
`Chin ............................................................................................. 26
`Level of Ordinary Skill in the Art ......................................................... 27
`
` Ground 1: Dusija And Sutardja In View Of The Knowledge Of A
`POSA Renders Obvious Claims 1-2 And 6-7 Of The 240 Patent ........ 27
`1.
`Claim 1 ........................................................................................ 28
`a.
`[1.PRE] “A system for storing data comprising:” ...................... 28
`b.
`[1.A] “at least one MLC non-volatile memory module
`comprising a plurality of individually erasable blocks;” ............ 30
`[1.B] “at least one SLC non-volatile memory module
`comprising a plurality of individually erasable blocks; and” ..... 32
`[1.C] “a controller coupled to the at least one MLC non-
`volatile memory module and the at least one SLC non-
`volatile memory module,” .......................................................... 34
`[1.D] “[1.D.i] the controller maintaining an address map of
`at least one of the MLC and SLC non-volatile memory
`modules, the address map comprising a list of logical
`address ranges accessible by a computer system, [1.D.ii.]
`the list of logical address ranges having a minimum quanta
`of addresses, [1.D.iii.] wherein each entry in the list of
`logical address ranges maps to a similar range of physical
`addresses within either the at least one SLC non-volatile
`memory module or within the at least one MLC non-
`volatile memory module;” .......................................................... 36
`
`d.
`
`c.
`
`e.
`
`-ii-
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 9,997,240
`
`[1.E.i] “wherein the controller is adapted to determine if a
`range of addresses listed by an entry and mapped to a
`similar range of physical addresses within the at least one
`MLC non-volatile memory module, fails a data integrity
`test, and, [1.E.ii] in the event of such a failure, the
`controller remaps the entry to the next available equivalent
`range of physical addresses within the at least one SLC
`non-volatile memory module;” ................................................... 40
`[1.F] “[1.F.i] wherein the controller is further adapted to
`determine which of the blocks of the plurality of the blocks
`in the MLC and SLC non-volatile memory modules are
`accessed most frequently and [1.F.ii] wherein the controller
`segregates those blocks that receive frequent writes into the
`at least one SLC non-volatile memory module and those
`blocks that receive infrequent writes into the at least one
`MLC nonvolatile module,” ......................................................... 43
`[1.G] “[1.G.i] maintain a count value of the blocks in the
`MLC non-volatile memory module determined to have
`received frequent writes and that are accessed most
`frequently [1.G.ii] on a periodic basis when the count value
`is a predetermined count value transfer the contents of the
`counted blocks in the MLC non-volatile memory module
`determined to have received frequent writes after reaching
`the predetermined count value to the SLC non-volatile
`memory module [1.G.iii] and which determined blocks in
`the SLC are determined in accordance with the next
`equivalent range of physical addresses determined by the
`controller” ................................................................................... 46
`(1)
`Individual counts interpretation ............................. 47
`(2) Collective count interpretation ............................... 50
`(3)
`[1.G.iii] and which determined blocks in the
`SLC are determined in accordance with the
`next equivalent range of physical addresses
`determined by the controller. ................................. 55
`Claim 2: “The system of claim 1, wherein the MLC and
`SLC each comprise flash memories.” ......................................... 57
`
`f.
`
`g.
`
`h.
`
`2.
`
`-iii-
`
`

`

`3.
`a.
`b.
`
`c.
`
`d.
`
`e.
`
`f.
`
`g.
`
`Petition for Inter Partes Review of U.S. Patent No. 9,997,240
`
`Claim 6 ........................................................................................ 57
`[6.PRE] “A system for storing data comprising:” ...................... 57
`[6.A] “at least one MLC non-volatile memory module
`comprising a plurality of individually erasable blocks;” ............ 57
`[6.B] “at least one SLC non-volatile memory module
`comprising a plurality of individually erasable blocks” ............. 57
`[6.C] “a controller coupled to the at least one MLC non-
`volatile memory module and the at least one SLC non-
`volatile memory module” ........................................................... 58
`[6.D] “[6.D.i] the controller maintaining an address map of
`at least one of the MLC and SLC non-volatile memory
`modules, the address map comprising a list of logical
`address ranges accessible by a computer system, [6.D.ii] the
`list of logical address ranges having a minimum quanta of
`addresses, [6.D.iii] wherein each entry in the list of logical
`address ranges maps to a similar range of physical
`addresses within either the at least one SLC non-volatile
`memory module or within the at least one MLC non-
`volatile memory module;” .......................................................... 58
`[6.E] “wherein the controller allocates those blocks that
`receive frequent writes into the SLC non-volatile memory
`module as hot blocks and those blocks that only receive
`infrequent writes into the MLC non-volatile memory
`module as cold blocks; and” ....................................................... 58
`[6.F] “wherein the controller is adapted to determine if a
`range of addresses listed by an entry and mapped to a
`similar range of physical addresses within the at least one
`MLC non-volatile memory module, fails a data integrity
`test, and in the event of such a failure, the controller remaps
`the entry to the next available equivalent range of physical
`addresses within the at least one SLC non-volatile memory
`module;” ...................................................................................... 59
`
`-iv-
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 9,997,240
`
`h.
`
`[6.G.i] “wherein the controller is further adapted to
`maintain a count value of those blocks that are accessed
`most frequently, and [6.G.ii] and, on a periodic basis when
`the count value is a predetermined count value, transfer the
`contents of those counted blocks into the SLC non-volatile
`memory module, [6.G.iii] wherein the counted blocks
`transferred to after reaching the predetermined count value
`are determined in accordance with the next equivalent range
`of physical addresses determined by the controller.” ................. 60
`Claim 7: “The system of claim 6, wherein the MLC and
`SLC each comprise flash memories.” ......................................... 61
`5. Motivation to Combine ............................................................... 61
` Ground 2: Dusija, Sutardja, And Chin In View Of The Knowledge
`Of A POSA Renders Obvious Claims 1-2 And 6-7 Of The 240
`Patent ..................................................................................................... 63
`1.
`Claim 1 ........................................................................................ 64
`a.
`[1.G] “[1.G.i] maintain a count value of the blocks in the
`MLC non-volatile memory module determined to have
`received frequent writes and that are accessed most
`frequently [1.G.ii] on a periodic basis when the count value
`is a predetermined count value transfer the contents of the
`counted blocks in the MLC non-volatile memory module
`determined to have received frequent writes after reaching
`the predetermined count value to the SLC non-volatile
`memory module and [1.G.iii] which determined blocks in
`the SLC are determined in accordance with the next
`equivalent range of physical addresses determined by the
`controller.” .................................................................................. 64
`Claim 6 ........................................................................................ 69
`
`4.
`
`2.
`
`-v-
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 9,997,240
`
`a.
`
`[6.G.i] “wherein the controller is further adapted to
`maintain a count value of those blocks that are accessed
`most frequently, and [6.G.ii] and, on a periodic basis when
`the count value is a predetermined count value, transfer the
`contents of those counted blocks into the SLC non-volatile
`memory module, [6.G.iii] wherein the counted blocks
`transferred to after reaching the predetermined count value
`are determined in accordance with the next equivalent range
`of physical addresses determined by the controller.” ................. 69
`3. Motivations to Combine ............................................................. 70
`
`-vi-
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 9,997,240
`
`TABLE OF AUTHORITIES
`
` Page(s)
`
`Cases
`Apple Inc. v. Fintiv, Inc.,
`IPR2020-00019, Paper 11 (PTAB Mar. 20, 2020) ............................... 8, 9, 10, 12
`Apple Inc. v. Maxell, Ltd.,
`IPR2020-00204, Paper 11, 15-17 (PTAB June 19, 2020) .................................. 10
`Juniper Networks, Inc. v. WSOU Investments LLC,
`IPR2021-00538, Paper 9, 13 (PTAB Aug. 18, 2021) ................................... 10, 11
`KCJ Corp. v. Kinetic Concepts, Inc.,
`223 F.3d 1351 (Fed. Cir. 2000) .......................................................................... 47
`Nvidia Corp. v. Invensas Corp.,
`IPR2020-00603, Paper 11, 23 (PTAB Sept. 3, 2020)......................................... 11
`Phillips v. AWH Corp.,
`415 F.3d 1303 (Fed. Cir. 2005) (en banc) .......................................................... 21
`Sand Revolution II, LLC v. Continental Intermodal Grp. – Trucking
`LLC,
`IPR2019-01393, Paper 24, 11-12 (June 16, 2020) ....................................... 10, 12
`Vervain, LLC v. Micron Technology, Inc.,
`Case No. 6:21-cv-00487 (W.D. Tex., filed May 10, 2021) .............................. 5, 8
`Vervain, LLC v. Western Digital Corporation,
`Case No. 6:21-cv-00488 (W.D. Tex., filed May 10, 2021) .................................. 5
`Statutes
`35 U.S.C. §§ 102(a), (b), and (e) ............................................................................... 7
`35 U.S.C. § 314(a) ..................................................................................................... 7
`35 U.S.C. § 314(a) and 325(d) ................................................................................... 6
`
`-vii-
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 9,997,240
`
`Other Authorities
`37 C.F.R. § 42.10(b) .................................................................................................. 5
`37 C.F.R. § 42.15(a) ................................................................................................... 6
`37 C.F.R. § 42.104(a) ................................................................................................. 3
`37 C.F.R. § 42.104(B) ................................................................................................ 6
`37 C.F.R. § 42.108(a) ................................................................................................. 6
`157 Cong. Rec. S5429 (Sept. 8, 2011) ....................................................................... 9
`
`-viii-
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 9,997,240
`
`LISTING OF EXHIBITS
`
`Exhibit
`
`Description
`
`1001-1004
`
`Intentionally omitted
`
`1005
`
`1006
`
`U.S. Patent No. 9,997,240 (the “240 patent”)
`
`File History of U.S. Patent No. 9,997,240
`
`1007-1008
`
`Intentionally omitted
`
`1009
`
`1010
`
`1011
`
`1012
`
`1013
`
`1014
`
`1015
`
`1016
`
`1017
`
`1018
`
`1019
`
`Declaration of Dr. David Liu (“Liu Decl.”) – IPR2021-01549
`
`U.S. Patent Application Publication No. 2011/0099460
`(“Dusija”)
`
`U.S. Patent Application Publication No. 2008/0140918
`(“Sutardja”)
`
`U.S. Patent Application Publication No. 2009/0327591
`(“Moshayedi”)
`
`Intentionally omitted
`
`Betty Prince, Semiconductor Memories – A Handbook of
`Design, Manufacture, and Application (2d ed. 1991) (“Prince”)
`
`U.S. Patent No. 8,120,960 (“Varkony”)
`
`U.S. Patent No. 7,000,063 (“Friedman”)
`
`U.S. Patent Application Publication No. 2005/0251617
`(“Sinclair”)
`
`Jan Axelson, USB Mass Storage: Designing and Programming
`Devices and Embedded Hosts (2006) (“Axelson”)
`
`Rino Micheloni et al., Inside NAND Flash Memories (1st ed.
`2010) (“Micheloni”)
`
`-ix-
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 9,997,240
`
`Exhibit
`
`Description
`
`1020
`
`1021
`
`1022
`
`1023
`
`1024
`
`1025
`
`1026
`
`1027
`
`1028
`
`1029
`
`1030
`
`1031
`
`1032
`
`1033
`
`1034
`
`U.S. Patent Application Publication No. 2011/0115192
`(“Y. Lee”)
`
`U.S. Patent No. 7,453,712 (“Kim”)
`
`U.S. Patent Application Publication No. 2011/0096601
`(“Gavens”)
`
`U.S. Patent No. 8,078,794 (“C. Lee”)
`
`U.S. Patent No. 7,733,729 (“Boeve”)
`
`Microsoft Computer Dictionary, Fifth Edition, 2002, definition
`of read-after-write
`
`Merriam-Webster’s Collegiate Dictionary, Eleventh Edition,
`2006, definition of periodic
`
`New Oxford American Dictionary, 3rd Edition, 2010, definition
`of module
`
`U.S. Patent Application Publication No. 2010/0172180
`(“Paley”)
`
`U.S. Patent No. 7,853,749 (“Kolokowsky”)
`
`U.S. Patent Application Publication No. 2010/0017650
`(“Chin”)
`
`European Patent Specification No. EP 2,291,746 B1 (“Radke”)
`
`U.S. Patent Application Publication No. 2015/0214476
`(“Matsui”)
`
`Intentionally omitted
`
`Complaint for Patent Infringement, Dkt. No. 1, Vervain, LLC v.
`Micron Technology, Inc., Micron Semiconductor Products,
`Inc., and Micron Technology Texas, LLC, Case No. 6:21-cv-
`00487-ADA (May 10, 2021 W.D. Tex.)
`
`-x-
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 9,997,240
`
`Exhibit
`
`Description
`
`1035
`
`Agreed Scheduling Order, Dkt. No. 24, dated September 16,
`2021, in Vervain, LLC v. Micron Technology, Inc., Micron
`Semiconductor Products, Inc., and Micron Technology Texas,
`LLC, Case No. 6:21-cv-00487-ADA
`
`1036-1037
`
`Intentionally omitted
`
`1038
`
`1039
`
`1040
`
`1041
`
`1042
`
`1043
`
`Scott McKeown, “WDTX ‘Implausible Schedule’ & Cursory
`Markman Order Highlighted,” Ropes & Gray, Patents Post-
`Grant, Inside Views & News Pertaining to the Nation’s Busiest
`Patent Court, June 2, 2021
`
`Dani Kass, Judge Albright Now Oversees 20% of New U.S.
`Patent Cases, Law360, March 10, 2021
`
`Brian Dipert and Markus Levy, Designing with Flash Memory
`(1994) (“Dipert & Levy”)
`
`U.S. Patent No. 7,366,826 (“Gorobets”)
`
`U.S. Patent No. 6,901,498 (“Conley”)
`
`U.S. Patent No. 8,356,152 (“You”)
`
`1044-1046
`
`Intentionally omitted
`
`1047
`
`1048
`
`1049
`
`Ashok Sharma, Advanced Semiconductor Memories,
`Architectures, Designs, and Applications (2003) (“Sharma”)
`
`Intentionally omitted
`
`U.S. Patent No. 5,936,971 (“Harari”)
`
`1050-1054
`
`Intentionally omitted
`
`1055
`
`New Oxford American Dictionary, 3rd Edition, 2010,
`definitions of frequency and threshold
`
`-xi-
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 9,997,240
`
`I.
`
`INTRODUCTION
`Petitioner Micron Technology, Inc. (“Micron” or “Petitioner”) respectfully
`
`requests inter partes review of claims 1-2 and 6-7 (the “Challenged Claims”) of U.S.
`
`Patent No. 9,997,240 (Ex. 1005, “240 patent”) which, according to USPTO records,
`
`is assigned to Vervain, LLC (“Vervain” or “Patent Owner”). There is more than a
`
`reasonable likelihood that Petitioner will prevail with respect to at least one
`
`Challenged Claim.
`
`The 240 patent relates to flash memory devices that include both multi-level
`
`cell (MLC) and single-level cell (SLC) memory modules. Flash memory devices
`
`with both MLC and SLC were well known and understood long before the 240 patent
`
`was filed, and the 240 patent does not contend otherwise. Instead, the 240 patent
`
`purports to improve such known devices by “segregating” (or “allocating”) blocks
`
`into SLC if frequently written and into MLC if infrequently written (“segregation
`
`limitation”). Further, the 240 patent purports to improve such devices by moving
`
`data from MLC to SLC in two circumstances: (1) if a write operation to MLC fails
`
`a “data integrity test” (the “data integrity test limitation”); and (2) periodically when
`
`a count (e.g., a write count) of the MLC blocks reaches a predetermined count value
`
`(“count value limitation”). The 240 patent’s claims as initially filed, which recited
`
`just the data integrity test limitation (and other well-known limitations), were
`
`-1-
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 9,997,240
`
`rejected as anticipated. The Examiner did not allow the claims until Applicant added
`
`the count value limitation.
`
`The Applicant did not disclose to the Examiner, nor did the Examiner cite, the
`
`references relied on in this Petition. In combination, the art in Petitioner’s grounds
`
`discloses or teaches all the limitations in the Challenged Claims and is readily
`
`combinable. Specifically, Dusija teaches a “post-write” read operation in which, if
`
`too many errors are detected, data is “remapped” from MLC to SLC (data integrity
`
`limitation). Sutardja discloses a flash memory device that segregates frequently
`
`written blocks to SLC and infrequently written blocks to MLC (segregation
`
`limitation). Notably, Sutardja also discloses (1) maintaining individual counts to
`
`determine which blocks are frequently written to and transferring the frequently
`
`written MLC blocks to SLC blocks when count thresholds are surpassed, and (2)
`
`maintaining a collective count for all writes to MLC, and upon that value reaching a
`
`threshold, transferring all MLC blocks to SLC (both of which disclose the count
`
`value limitation). Finally, as the prior art in this Petition demonstrates, e.g., Chin,
`
`the Examiner was not made aware that it was well known that such transfer processes
`
`were triggered by a collective count of, e.g., all writes or erases to MLC blocks.
`
`The Challenged Claims thus represent nothing more than the expected result
`
`of combining known techniques, with a reasonable expectation of success, for
`
`improving flash memory reliability. As such, Petitioner respectfully requests that
`
`-2-
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 9,997,240
`
`the Board enter a final written decision finding that the Challenged Claims of the
`
`240 patent are not patentable.
`
`II.
`
`REQUIREMENTS FOR PETITION FOR INTER PARTES REVIEW
`Grounds for Standing (37 C.F.R. § 42.104(a))
`Petitioner certifies that the 240 patent is available for IPR and that Petitioner
`
`is not barred or estopped from requesting IPR of the Challenged Claims of the 240
`
`patent on the grounds identified herein.
`
`Notice of Lead and Backup Counsel and Service Information (37
`C.F.R. §§ 42.8(b)(3-4), 42.10(a))
`Pursuant to 37 C.F.R. §§ 42.8(b)(3-4) and 42.10(a), Petitioner provides the
`
`following designation of Lead and Back-Up counsel:
`
`-3-
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 9,997,240
`
`Lead Counsel
`Jeremy Jason Lang
`Registration No. 73,604
`(jlang@orrick.com)
`
`Back-Up Counsel
`Jared Bobrow
`Pro Hac Vice to be submitted
`(jbobrow@orrick.com)
`
`Postal & Hand-Delivery Address:
`Orrick, Herrington & Sutcliffe LLP
`1000 Marsh Road
`Menlo Park, CA 94025-1015
`T: 650-614-7400; F: 650-614-7401
`
`Postal & Hand-Delivery Address:
`Orrick, Herrington & Sutcliffe LLP
`1000 Marsh Road
`Menlo Park, CA 94025-1015
`T: 650-614-7400; F: 650-614-7401
`
`Parth Sagdeo
`Registration No. 71,275
`(psagdeo@orrick.com)
`
`Postal & Hand-Delivery Address:
`Orrick, Herrington & Sutcliffe LLP
`222 Berkeley St.
`Suite 2000
`Boston, MA 02116
`T: 617-880-1800; F: 617-880-1801
`
`Christopher Childers
`Registration No. 75,237
`(cchilders@orrick.com)
`
`Postal & Hand-Delivery Address:
`Orrick, Herrington & Sutcliffe LLP
`1152 15th St. NW
`Washington, DC 20005
`T: 202-339-8441; F: 202-339-8500
`
`Petitioner consents to service by electronic mail at the following addresses:
`
`PTABDocketJ3B3@orrick.com,
`
`PTABDocketJJL2@orrick.com,
`
`PTABDocketP2S7@orrick.com, PTABDocketC4C8@orrick.com, and Micron-
`
`Vervain_OHS@orrick.com.
`
`-4-
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 9,997,240
`
`Pursuant to 37 C.F.R. § 42.10(b), Petitioner’s Power of Attorney is attached.
`
`Notice of Real Party-in-Interest (37 C.F.R. § 42.8(b)(1))
`Petitioner Micron Technology, Inc.—along with its subsidiaries—is the real
`
`party-in-interest.
`
`Notice of Related Matters (37 C.F.R. § 42.8(b)(2))
`According to USPTO assignment records, the 240 patent is currently assigned
`
`to Vervain. Vervain has asserted the 240 patent and U.S. Patent Nos. 8,891,298,
`
`9,196,385, and 10,950,300 against Petitioner in a co-pending litigation, Vervain,
`
`LLC v. Micron Technology, Inc., Case No. 6:21-cv-00487 (W.D. Tex., filed May 10,
`
`2021) (“Co-Pending Litigation”). Vervain also has asserted the 240 patent and U.S.
`
`Patent Nos. 8,891,298, 9,196,385, and 10,950,300 against Western Digital
`
`Corporation, Western Digital Technologies, Inc., and HGST, Inc. in Vervain, LLC
`
`v. Western Digital Corporation, Case No. 6:21-cv-00488 (W.D. Tex., filed May 10,
`
`2021) (“Western Digital Litigation”).
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`In addition to this Petition, Petitioner has filed petitions for inter partes review
`
`of the three other asserted patents in the Co-Pending Litigation: Petition for Inter
`
`Partes Review of U.S. Patent No. 8,891,298, IPR2021-01547, Petition for Inter
`
`Partes Review of U.S. Patent No. 9,196,385, IPR2021-01548, and Petition for Inter
`
`Partes Review of U.S. Patent No. 10,950,300, IPR2021-01550.
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`-5-
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`

`

`Petition for Inter Partes Review of U.S. Patent No. 9,997,240
`
`The Director and the Board should allow this Petition under 35 U.S.C.
`
`§ 314(a) and 325(d) and/or 37 C.F.R. § 42.108(a). See Section IV.
`
`Fee for Inter Partes Review
`The Director is authorized to charge the fee specified by 37 C.F.R. § 42.15(a),
`
`and any other required fees, to Deposit Account No. 15-0665.
`
`Proof of Service
`Proof of service of this Petition on the Patent Owner at the correspondence
`
`addresses of record for the 240 patent is attached.
`
`III.
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`IDENTIFICATION OF CLAIMS BEING CHALLENGED (37 C.F.R.
`§ 42.104(B))
`Petitioner requests IPR of claims 1-2 and 6-7.
`
`The 240 patent was filed on November 24, 2015. The patent also makes a
`
`facial claim of priority to a July 19, 2011 Provisional Application No. 61/509,257.
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`240 patent, Cover. For purposes of this Petition only, it is assumed that the 240
`
`patent’s claims are entitled to the benefit of this July 19, 2011 date.
`
`Petitioner’s grounds rely on the following references:
`
`(1) U.S. Patent Application Publication No. 2011/0099460 (Ex. 1010,
`
`“Dusija”): Dusija was filed on December 18, 2009. Dusija is prior art to the 240
`
`patent under at least §§ 102(a) and (e).
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`-6-
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`

`

`Petition for Inter Partes Review of U.S. Patent No. 9,997,240
`
`(2) U.S. Patent Application Publication No. 2008/0140918 (Ex. 1011,
`
`“Sutardja”): Sutardja was filed on December 7, 2007, and published on June 12,
`
`2008. Sutardja is prior art to the 240 patent under at least §§ 102(a), (b), and (e).
`
`(3) U.S. Patent Application Publication No. 2010/0017650 (Ex. 1030,
`
`“Chin”); Chin was filed on May 25, 2009 and published on January 21, 2010. Chin
`
`is prior art to the 240 patent under at least 35 U.S.C. §§ 102(a), (b), and (e).
`
`Petitioner challenges the claims on the following grounds:
`
`Ground 1: Claims 1-2 and 6-7 are obvious over Dusija and Sutardja in view
`
`of the knowledge of a person of ordinary skill in the art (a “POSA”).
`
`Ground 2: Claims 1-2 and 6-7 are obvious over Dusija, Sutardja, and Chin in
`
`view of the knowledge of a POSA.
`
`None of the references on which these grounds are based was cited or
`
`discussed by the Examiner during prosecution of the 240 patent.
`
`These grounds are supported by the declaration of Dr. David Liu (Ex. 1009,
`
`“Liu Decl.”).
`
`IV. THE BOARD SHOULD NOT EXERCISE ITS DISCRETION TO
`DENY INSTITUTION
`The Parallel District Court Litigation Does Not Weigh Against
`Institution
`Petitioner respectfully requests that the Board not exercise its discretion to
`
`deny institution pursuant to 35 U.S.C. § 314(a). On May 10, 2021, Vervain sued
`
`-7-
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`

`

`Petition for Inter Partes Review of U.S. Patent No. 9,997,240
`
`Micron, Micron Semiconductor Products, Inc., and Micron Technology Texas, LLC
`
`in the Western District of Texas, asserting the 240 patent and three other patents.
`
`Ex. 1034. Micron had no pre-suit notice of the 240 patent. Nevertheless,
`
`approximately five months later, Micron filed this Petition as well as petitions on the
`
`three other asserted patents. At the time of filing this Petition, no substantial
`
`litigation activity has occurred. The parties have only exchanged preliminary
`
`infringement and preliminary invalidity contentions and they just recently
`
`exchanged terms for possible claim construction.1 Given that the Co-Pending
`
`Litigation is still in its very early stages, Petitioner’s diligence weighs heavily in
`
`favor of institution.
`
`Should Patent Owner argue that the Board should deny institution in its
`
`discretion under the factors set forth in Apple Inc. v. Fintiv, Inc., IPR2020-00019,
`
`Paper 11 (PTAB Mar. 20, 2020) (“the Fintiv factors”), and if the Board were to
`
`entertain such an argument, Petitioner respectfully requests that it be afforded an
`
`opportunity to submit a brief to address Patent Owner’s arguments and report on any
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`litigation activity.
`
`In any event, the Board should not exercise its discretion to deny this Petition.
`
`First, doing so would unfairly close the Board’s doors to Petitioner. Micron was
`
`1 On July 9, 2021, Micron filed a Rule 12(b)(6) Motion to Dismiss the Complaint.
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`-8-
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`

`

`Petition for Inter Partes Review of U.S. Patent No. 9,997,240
`
`extraordinarily diligent in analyzing the prior art and preparing this Petition (along
`
`with three others) to file as early as it did.
`
`Second, the Fintiv factors weigh in favor of institution. Under Fintiv factor
`
`three (investment in the parallel proceeding), Fintiv notes: “[i]f the evidence shows
`
`that the petitioner filed the petition expeditiously, such as promptly after becoming
`
`aware of the claims being asserted, this fact has weighed against exercising the
`
`authority to deny institution under NHK.” Apple v. Fintiv, IPR2020-00019, Paper
`
`11, 11. Here, Petitioner filed approximately five months after receipt of the
`
`complaint. Moreover, to date, no court resources have been devoted to analyzing
`
`prior art, invalidity, or any other substantive issue in this proceeding. No claim
`
`construction has occurred (only an exchange of potential terms), a motion to dismiss
`
`is pending, and there has been no meaningful fact or expert discovery. When the
`
`Board issues its institution decision on this Petition, fact discovery will be in its
`
`infancy. See Ex. 1035 (fact discovery to begin January 21, 2022 and close August
`
`12, 2022). Further, expert discovery is not to be completed until October 7, 2022.
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`Id. And any district court claim construction proceedings that occur before
`
`institution would add to the efficiency of this IPR proceeding because the parties
`
`will submit any claim construction materials from the district court to the Board. On
`
`facts nearly identical to these, the Board found this factor to weigh substantially
`
`against exercising discretion to deny institution because “while the scheduled date
`
`-9-
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`

`

`Petition for Inter Partes Review of U.S. Patent No. 9,997,240
`
`for a Markman hearing ha[d] passed, much of the invested effort [wa]s unconnected
`
`to the patentability challenges.” Juniper Networks, Inc. v. WSOU Investments LLC,
`
`IPR2021-00538, Paper 9, 13 (PTAB Aug. 18, 2021).
`
`Under Fintiv factor six (other considerations), Fintiv notes that if the merits
`
`of the Petition are strong, which is the case here, institution of a trial may “serve the
`
`interest of overall system efficiency and integrity because it allows the proceeding
`
`to continue in the event that the parallel proceeding settles or fails to resolve the
`
`patentability question presented in the PTAB proceeding.” Apple v. Fintiv,
`
`IPR2020-00019, Paper 11, 15. Vervain has already brought two patent infringement
`
`lawsuits against two memory manufacturers, and others are likely in line.
`
`The fourth Fintiv factor (overlap of issues between the district court and IPR)
`
`favors institution. Should the Board institute an IPR proceeding on the 240 patent,
`
`Micron stipulates that it will not pursue any instituted grounds as invalidity defenses
`
`in the District Court, thus eliminating any overlap in issues. The Board has found
`
`that s