I 1111111111111111 11111 lllll lllll lllll 111111111111111 111111111111111 IIII IIII
`US007453712B2
`
`c12) United States Patent
`Kim et al.
`
`(IO) Patent No.:
`(45) Date of Patent:
`
`US 7,453,712 B2
`Nov. 18, 2008
`
`(54) HYBRID FLASH MEMORY DEVICE AND
`METHOD FOR ASSIGNING RESERVED
`BLOCKS THEREOF
`
`(75)
`
`Inventors: Seon-Taek Kim, Suwon-si (KR);
`Byoung-Kook Lee, Suwon-si (KR)
`
`(73) Assignee: Samsung Electronics Co., Ltd.,
`Suwon-si, Gyeonggi-do (KR)
`
`( *) Notice:
`
`Subject to any disclaimer, the term ofthis
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 42 days.
`
`(21) Appl. No.: 11/613,366
`
`(22) Filed:
`
`Dec. 20, 2006
`
`(65)
`
`Prior Publication Data
`
`US 2008/0112238 Al
`
`May 15, 2008
`
`(30)
`
`Foreign Application Priority Data
`
`Oct. 25, 2006
`
`(KR)
`
`...................... 10-2006-0104151
`
`(51)
`
`Int. Cl.
`GllC 5106
`(2006.01)
`(52) U.S. Cl. ..................... 365/63; 365/200; 365/230.03
`(58) Field of Classification Search ................... 365/63,
`365/200, 230.03, 185.33
`See application file for complete search history.
`
`(56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`6,418,052 Bl
`7/2002 Shibata et al.
`6,947,322 B2
`9/2005 Anzai et al.
`2006/0155917 Al*
`7/2006 Di Sena et al. .............. 711/103
`2007 /02337 52 Al * 10/2007 Bangalore et al. ........... 707 /202
`FOREIGN PATENT DOCUMENTS
`11-345491
`12/1999
`
`JP
`
`JP
`JP
`JP
`KR
`KR
`KR
`KR
`KR
`
`2001-006374
`2002-208287
`2004-127481
`1020040011387
`1020050007653
`1020060012696
`1020060021548
`1020070048384
`
`12/2001
`7/2002
`4/2004
`2/2004
`1/2005
`2/2006
`3/2006
`5/2007
`
`OTHER PUBLICATIONS
`
`English Abstract for Publication No.: 2002-208287.
`English Abstract for Publication No.: 1020050007653.
`English Abstract for Publication No.: 1020060012696.
`English Abstract for Publication No.: 1020060021548.
`English Abstract for Publication No.: 1020070048384.
`
`* cited by examiner
`
`Primary Examiner-Thong Q Le
`(7 4) Attorney, Agent, or Firm-F. Chau & Associates
`
`(57)
`
`ABSTRACT
`
`A hybrid flash memory device includes an array including a
`first area and a second area having a larger number of stored
`bits per cell than the first area. The device includes a hidden
`area including a first reserved block area and a second
`reserved block area, wherein the first reserved block area
`includes a plurality of first memory blocks having the same
`number of stored bits per cell as the first area, the second
`reserved block area includes a plurality of second memory
`blocks having the same number of stored bits per cell as the
`second area, and a flash translation layer configured to replace
`a bad block generated in the first main area with the first
`memory block and replace a bad block generated in the sec(cid:173)
`ond main area with the second memory block, wherein the
`flash translation layer flexibly assigns functions of the first
`memory blocks or the second memory blocks depending on
`whether the first and second memory blocks are all used.
`
`20 Claims, 7 Drawing Sheets
`
`190
`r----------------------------------- 1~-----7
`190
`184
`160
`110
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`I
`
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`
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`
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`RAM
`
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`
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`
`Host
`
`Host
`rntcrface
`
`Controiier
`
`Flash
`J :rterface
`
`F 1 2sh Memory
`
`NLC
`Area
`
`Reserved Ar ea
`
`SLC
`P.rea
`
`j
`
`~~~-- I
`I
`:
`~
`I
`
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`
`Micron Ex. 1021, p. 1
`Micron v. Vervain
`IPR2021-01549
`
`

`

`"'""' N = N
`
`~
`UI w
`~
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`I
`
`I
`
`I
`
`Area
`MLC
`
`Flash Memory
`
`/
`1 182
`
`170
`
`Buffer
`
`RAM
`
`.---_._~ ~--......... -.
`
`L------------------------------------------~
`I:
`:1
`
`j I
`
`I 11~1 I
`
`Area
`SLC
`
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`
`Interface
`
`Flash
`
`Control /er
`
`Interface
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`Host
`
`Host
`
`I
`I
`! ___________________________________ £ -----7
`
`11 0
`
`1 60
`
`184
`
`100
`
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`I
`
`Fig. 1
`
`190
`
`500
`
`lri
`
`I
`
`I
`I
`I
`
`Micron Ex. 1021, p. 2
`Micron v. Vervain
`IPR2021-01549
`
`

`

`U.S. Patent
`
`Nov. 18, 2008
`
`Sheet 2 of 7
`
`US 7,453,712 B2
`
`Fig. 2
`
`Meta area
`(hidden)
`
`USER data area
`(divided by US~R)
`
`Logical
`
`Meta Data
`
`F i I e System Data + Nor ma I Da t c:.
`
`140
`
`Physical
`
`MLC Arna
`
`Fig. :3
`
`135
`
`SLC
`
`l
`136
`
`I
`
`Bad Block replacement for SLC
`
`Bad Block replacement for MLC
`
`MLC
`
`SLC/MLC Boundary
`- - - - - - - - - - - - - - - - · · - · · - - - - - - - - - - - -
`Reserved Area
`
`Micron Ex. 1021, p. 3
`Micron v. Vervain
`IPR2021-01549
`
`

`

`U.S. Patent
`
`Nov. 18, 2008
`
`Sheet 3 of 7
`
`US 7,453,712 B2
`
`Fig. 4
`
`SLC/MLC Boundary
`i
`
`. . .
`136 ~
`
`SLC
`1 b I ock
`
`SLC
`MLC
`SLC
`iblock 1block 1block
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`
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`. . .
`
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`
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`1block
`
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`
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`
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`SLC/MLC Boundary
`
`Fig. 5
`
`SLC/MLC Boundary
`i
`
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`
`. . .
`
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`SLC
`1block 1block
`
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`
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`
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`
`it
`
`-----
`
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`
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`
`SLC
`SLC
`MLC
`1block 1block 1block
`
`. . .
`
`--.
`
`t
`SLC/MLC Boundary
`
`Micron Ex. 1021, p. 4
`Micron v. Vervain
`IPR2021-01549
`
`

`

`"'""' N = N
`
`-....l
`"'w
`UI
`~
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`
`d r.,;_
`
`137 I
`
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`.....
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`1 I xeci .::iu.,; MLv DUUi 1Uc1f Y
`r
`n~-.,,~-.,"""L-.~a"'-!
`
`t
`
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`
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`
`~
`
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`
`1block
`
`MLC
`
`ib!ock
`ML C
`
`~iblo block Al location
`
`1 b I ock
`
`1 b I ock
`
`SLC I SLC
`
`137
`
`. . .
`
`iblock
`
`MLC
`
`1 b I ock
`
`MLC
`
`iblock
`
`SLC
`
`1block
`
`SLC
`
`1block 1block
`
`SLC
`
`SLC
`
`!
`
`Fixed SLC/MLC Boundary
`
`Fig. 6
`
`1361
`
`. . .
`
`136
`
`Micron Ex. 1021, p. 5
`Micron v. Vervain
`IPR2021-01549
`
`

`

`"'""' N = N
`
`~
`UI w
`~
`-....l
`
`d r.,;_
`
`Fixed SLC/MLC Boundary
`
`t
`
`0 ....
`Ul
`.....
`rJJ =(cid:173)
`
`('D
`('D
`
`-....J
`
`1371
`
`. . .
`
`137
`
`. . .
`
`1block
`
`MLC
`
`1block
`
`MLC
`
`1 b I ock
`
`MLC
`
`~ible block Al location
`
`1block
`
`MLC
`
`1block
`
`MLC
`
`~ ....
`z 0
`
`CIO
`0
`0
`N
`~CIO
`
`~
`~
`~
`•
`00
`~
`
`~ = ~
`
`Fige 7
`
`Fixed SLC/MLC Boundary
`
`i
`
`1 b I ock
`
`1 b I ock
`
`SLC I SLC
`
`1block 1block
`
`SLC
`
`SLC
`
`. . .
`
`1361
`
`. . .
`
`136
`
`Micron Ex. 1021, p. 6
`Micron v. Vervain
`IPR2021-01549
`
`

`

`"'""' N = N
`
`~
`UI w
`~
`-....l
`
`d r.,;_
`
`237
`
`·~ Reserved BI ocks ------
`
`240
`
`230 236
`
`220
`
`MLC Area
`
`SLC Area
`
`Physical
`
`0 ....
`O'I
`.....
`rJJ =(cid:173)
`
`('D
`('D
`
`-....J
`
`~ ....
`z 0
`
`CIO
`0
`0
`N
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`
`~
`~
`~
`•
`00
`~
`
`~ = ~
`
`Fi le System Data + Normal Data
`
`Meta Data
`
`Logical
`
`(divided by USER)
`USER data area
`
`(hidden)
`Meta area
`
`Fig. 8
`
`Micron Ex. 1021, p. 7
`Micron v. Vervain
`IPR2021-01549
`
`

`

`U.S. Patent
`
`Nov. 18, 2008
`
`Sheet 7 of 7
`
`US 7,453,712 B2
`
`Fig.
`
`~
`
`<,
`
`G
`
`SLC
`iblock
`
`SLC
`SLC
`iblock 1block
`
`SLC
`iblock
`
`T
`
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`·1 b I ock
`
`SLC
`iblock
`
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`iblock
`
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`iblock
`
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`
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`
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`
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`ML.C
`..
`"
`.,
`'----~~~,LJ..L._i _b _I o_c_k ....J.._i_b_l _oc:~
`· · '
`
`Micron Ex. 1021, p. 8
`Micron v. Vervain
`IPR2021-01549
`
`

`

`US 7,453,712 B2
`
`1
`HYBRID FLASH MEMORY DEVICE AND
`METHOD FOR ASSIGNING RESERVED
`BLOCKS THEREOF
`
`CROSS-REFERENCE TO RELATED
`APPLICATIONS
`
`This U.S. non-provisional patent application claims prior(cid:173)
`ity under 35 U.S.C § 119 of Korean Patent Application 2006-
`104151 filed on Oct. 25, 2006, the entirety of which is hereby
`incorporated by reference.
`
`BACKGROUND
`
`5
`
`2
`among mass consecutive information. Likewise characteris(cid:173)
`tics of a multi-bit flash memory device and a single-bit flash
`memory device are closely associated with frequency of bad
`blocks (hereinafter, a block in which an error occurs is
`referred to as "bad block").
`Reserved blocks are disposed inside a single-bit flash
`memory device and a multi-bit flash memory device to
`replace bad blocks, respectively. However, since the possibil(cid:173)
`ity of generating bad blocks in a multi-bit flash memory
`10 device is higher than that of bad blocks in a single-bit flash
`memory device, sizes of assigned reserved blocks should vary
`with data storage characteristics of flash memory devices. For
`example, for a hybrid flash memory device in which a single(cid:173)
`bit flash memory and a multi-bit flash memory are mixed,
`15 reserved blocks should be assigned in consideration of all
`characteristics between the mixed flash memories. This is
`because usable reserved blocks are limited in number. When
`either reserved blocks for a single-bit flash memory or
`reserved blocks for a multi-bit flash memory are all used, a
`20 chip may no longer be used.
`
`1. Technical Field
`The present invention relates to semiconductor memory
`devices and, more specifically, to a method for assigning
`reserved blocks of a hybrid flash memory device in which
`single-bit cells and multi-bit cells are arranged in the same
`array.
`2. Description of Related Art
`Semiconductor memory devices may be categorized as
`volatile memory devices or non-volatile memory devices.
`The volatile memory devices can be classified into dynamic
`random access memories (DRAMs) and static random access 25
`memories (SRAMs ). Data stored on a volatile semiconductor
`device is lost if a power supply is interrupted, while a non(cid:173)
`volatile memory device retains stored data even when the
`power supply is interrupted. Thus, the non-volatile memories
`are widely used to store retention-required data. The non- 30
`volatile memories may be categorized as mask read-only
`memories (MROMs), programmable read-only memories
`(PROMs), erasable progranmiable read-only memories
`(EPROMs), and electrically erasable progranmiable read(cid:173)
`only memories (EEPROMs).
`The MROMs, PROMs, and EPROMs have difficulty in
`rewriting stored data because read and write operations can(cid:173)
`not be freely conducted by users, unlike EEPROMs.
`EEPROMs are increasingly used in system progranmiing
`needing continuous update or auxiliary memory devices. 40
`Typically, flash EEPROMs are used as mass storage devices
`because their integration density is higher than other types of
`EEPROM. Among the flash EEPROMs, a NAND-type flash
`EEPROM has a higher integration density than a NOR-type
`or AND-type flash EEPROM.
`Single-bit data or multi-bit data ( e.g., 2-bit data, 4-bit data,
`etc.) may be stored in each flash memory cell. With the
`ever-increasing demand for higher integration density of flash
`memories, studies have been conducted for multi-bit, multi(cid:173)
`level or multi-state flash memory devices where data of mu!- 50
`tiple bits are stored in one memory cell.
`The stage-to-state window of a multi-bit flash memory
`device is narrower than the window of a single-bit flash
`memory device. In the multi-bit flash memory device, a mar(cid:173)
`gin between a voltage applied to a wordline selected during a 55
`read operation and the edge of a threshold voltage distribution
`becomes narrower with the decrease in window width. There(cid:173)
`fore, a multi-bit array has a higher possibility of invalid sens(cid:173)
`ing caused by process variation or changes in voltage level of
`a selected wordline, an operation voltage, or temperature than 60
`a single-bit flash memory device. For this reason, single-bit
`flash memory devices are typically used as storage devices of
`information, such as BIOS information or font information,
`needing a superior storage characteristic. Multi-bit flash
`memory devices are typically as storage devices of informa- 65
`tion, such as voice information, which may remain viable
`despite occurrence of storage failure of one or more bits
`
`SUMMARY OF THE INVENTION
`
`Exemplary embodiments of the present invention are
`directed to a hybrid flash memory device. In an exemplary
`embodiment, the hybrid flash memory device may include an
`array including a first area and a second area having a larger
`number of stored bits per cell than the first area; a hidden area
`including a first reserved block area and a second reserved
`block area, wherein the first reserved block area includes a
`plurality of first memory blocks having the same number of
`stored bits per cell as the first area, the second reserved block
`area includes a plurality of second memory blocks having the
`same number of stored bits per cell as the second area; and a
`35 flash translation layer configured to replace a bad block gen(cid:173)
`erated in the first main area with the first memory block and
`replace a bad block generated in the second main area with the
`second memory block, wherein the flash translation layer
`flexibly assigns functions of the first and second memory
`blocks depending on whether the first memory blocks or the
`second memory blocks are all used.
`Exemplary embodiments of the present invention are
`directed to a computer-readable media embodying instruc(cid:173)
`tions executable by a processor to perform a method for
`45 assigning reserved blocks of a hybrid flash memory device. In
`an exemplary embodiment, the method may include setting a
`boundary of a first reserved block area for replacing bad
`blocks generated in a first block and a boundary of a second
`reserved block area for replacing bad blocks generated in a
`second area having a larger number of stored bits per cell than
`the first area, and flexibly assigning functions of memory
`blocks of the first and second reserved block areas when
`memory blocks of the first reserved block or the second
`reserved block area are all used.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIG. 1 is a block diagram of a hybrid flash memory device
`according to an embodiment of the present invention.
`FIG. 2 shows an example of data storage for an SLC area,
`a reserved block area, and an MLC area illustrated in FIG. 1.
`FIG. 3 shows an example of configuration and data storage
`for the reserved block area illustrated in FIG. 2.
`FIG. 4 and FIG. 5 show a method for assigning an SLC
`reserved block area and an MLC reserved block area accord(cid:173)
`ing to an embodiment of the present invention.
`
`Micron Ex. 1021, p. 9
`Micron v. Vervain
`IPR2021-01549
`
`

`

`US 7,453,712 B2
`
`3
`FIG. 6 and FIG. 7 show a method for assigning an SLC
`reserved block area and an MLC reserved block area accord(cid:173)
`ing to another embodiment of the present invention.
`FIG. 8 shows an example of data storage for an SLC area,
`SLC and MLC reserved block areas, and an MLC area 5
`according to another embodiment of the present invention.
`FIG. 9 and FIG. 10 show a method for assigning the SLC
`reserved block area and the MLC reserved block area illus(cid:173)
`trated in FIG. 8.
`
`DETAILED DESCRIPTION OF PREFERRED
`EMBODIMENTS
`
`4
`are driven by means of a row decoder circuit (not shown), and
`columns thereof are driven by means of a page buffer circuit
`150.
`The page buffer circuit 150 is controlled by the controller
`170 and functions as a write driver or a sense amplifier
`according to operation mode. For example, the page buffer
`circuit 150 functions as a sense amplifier during a read opera(cid:173)
`tion mode and as a write drive during a program operation
`mode. The page buffer circuit 150 includes a plurality of page
`10 buffers PB corresponding to respective bitlines or bitline
`pairs.
`The ROM 182 is controlled by the controller 170. The FTL
`is stored in the ROM 182, mapping logic addresses generated
`by a file system in a program operation of a flash memory to
`15 physical addresses of a flash memory device where an erase
`operation is conducted. The FTL may be software or firm(cid:173)
`ware-type hardware. Examples of address mapping con(cid:173)
`ducted at the FTL are disclosed in U.S. Pat. No. 5,404,485
`entitled "FLASH FILE SYSTEM", U.S. Pat. No. 5,937,425
`20 entitled "FLASH FILE SYSTEM OPTIMIZED FOR PAGE(cid:173)
`MODE FLASH TECHNOLOGIES", and U.S. Pat. No.
`6,318,176 entitled "METHOD OF DRIVING REMAPPING
`IN FLASH MEMORY AND FLASH MEMORY ARCHI-
`TECTURE SUITABLE THEREFOR".
`The buffer RAM 184 is controlled by the controller 170
`and configured to temporarily store data supplied from the
`host 500 or the page buffer 150. Also the buffer RAM 184
`plays a role in loading and executing the FTL stored in the
`ROM 182 under the control of the controller 170, while the
`buffer RAM 184 may be a static random access memory
`(SRAM), the buffer RAM 184 may be implemented using
`other memory types. It will be understood by those skilled in
`the art that the buffer RAM 184 may be, for example, a
`dynamic random access memory (DRAM).
`The controller 170 controls general operations of the flash
`memory device 100. For example, when program erase or
`read operations are requested from the host 500, the controller
`170 controls the flash interface 160 and the buffer RAM 184
`to conduct these requested operations. The flash interface 160
`40 is an interface between the buffer RAM 184 and the page
`buffer circuit 150 under the control of the controller 170.
`Although described in detail below, the flash memory
`device 100 replaces a bad block with a memory block of the
`reserved block area 135 when an error occurs at the SLC area
`45 120 or the MLC area 140. Data stored in the bad block
`migrates to the replacement memory block. The data migra(cid:173)
`tion may be done through a data read operation or a copy back
`operation. Replacing the bad block with the memory block of
`the reserved block area 135 is done by means of the FTL. The
`reserved block area 135 is divided into an SLC reserved block
`area for replacing bad blocks of the SLC area 120 and an
`MLC reserved block area for replacing bad blocks of the
`MLC area 140. A boundary between the SLC reserved block
`area and the MLC reserved block area is flexibly variable.
`Alternatively, SLC memory blocks of the SLC reserved block
`area and MLC memory blocks of the MLC reserved block
`area are variable while a boundary between the SLC reserved
`block area and the MLC reserved block area is fixed. As a
`result, bad blocks of the SLC area 120 may be replaced with
`memory blocks of the MLC reserved block area, and bad
`blocks of the MLC area 140 may be replaced with memory
`blocks of the SLC reserved block area. According to the
`flexible operation for replacing bad blocks with memory
`blocks of a reserved block area, bad blocks generated in
`single-bit cells and multi-bit cells are efficiently replaced
`even with a limited reserved block area 135 to extend the
`lifespan of a chip.
`
`The present invention will now be described more fully
`hereinafter with reference to the accompanying drawings, in
`which exemplary preferred embodiments of the invention are
`shown. This invention, however, may be embodied in many
`different forms and should not be construed as limited to
`embodiments set forth herein. Rather, embodiments are pro(cid:173)
`vided so that this disclosure will be thorough and complete,
`and will fully convey the scope of the invention to those
`skilled in the art. Like numbers refer to like elements through(cid:173)
`out.
`FIG. 1 illustrates a configuration of a hybrid flash memory
`device 100 according to an embodiment of the present inven- 25
`tion. Specifically, the hybrid flash memory device 100 is a
`hybrid OneNAND flash memory device in which at least two
`memory cells differing in the number of stored bits per cell
`are formed on the same chip.
`Referring to FIG. 1, the hybrid flash memory device 100 30
`interfaces with a host 500 through a host interface 190. The
`host interface 190 between the hybrid flash memory device
`100 and the host 500 implements a NOR interface method
`that is well known in the art. Nonetheless, it will be under(cid:173)
`stood by those skilled in the art that the above-mentioned 35
`interface method is merely exemplary and may be another
`interface method such as, for example, a NAND interface
`method. While the hybrid flash memory device 100 may be an
`OneNAND flash memory device, it will be understood by
`those skilled in the art that the construction of the hybrid flash
`memory device 100 is not limited to the description herein.
`The hybrid flash memory device 100 includes a flash
`memory unit 110, a flash interface 160, a controller 170, a
`ROM 182, a buffer RAM 184, and the host interface 190.
`The flash memory unit 110 includes a memory cell array
`having a single-bit area 120 (hereinafter referred to as "SLC
`area"), a hidden area (see 130 of FIG. 2), a multi-bit area 140
`(hereinafter referred to as "MLC area") and a page buffer
`circuit 150. The memory cell array is divided into a main
`array including the SLC area 120 and the MLC area 140 and 50
`the hidden area 130 including a reserved block area 135.
`The SLC area 120 includes a plurality of SLC memory
`blocks. Although not illustrated in figures, memory cells of
`respective memory blocks included in the SLC area 120 are
`SLC memory cells and configured to have a string structure. 55
`Memory cells of respective memory blocks included in the
`MLC area 140 are MLC memory cells and configured to have
`a string structure. In the hidden area 130, user-invisible infor(cid:173)
`mation is stored, including e.g., meta data of a flash transla(cid:173)
`tion layer (hereinafter referred to as "FTL") such as address 60
`mapping information. The reserved block area 135 of the
`hidden area 130 is used to replace bad blocks. Similar to the
`SLC area 120 and the MLC area 140, the reserved block area
`135 includes a plurality of memory blocks. Memory cells of
`respective memory blocks included in the reserved block area 65
`135 are configured to have a string structure. Rows of the SLC
`area 120, the reserved block area 135, and the MLC area 140
`
`Micron Ex. 1021, p. 10
`Micron v. Vervain
`IPR2021-01549
`
`

`

`US 7,453,712 B2
`
`5
`FIG. 2 shows an example of data storage for the SLC area
`120, the reserved block area 135, and the MLC area 140
`illustrated in FIG. 1, and FIG. 3 shows an example of a
`configuration and data storage for the reserved block area 135
`illustrated in FIG. 2. FIG. 2 exemplarily illustrates a logical 5
`data structure used in a file system of a flash memory and
`physical data structure of a flash memory in which logic data
`is stored.
`Referring to FIG. 2 frequent-update-required data, such as
`file system data, is stored in the SLC area 120. Massive 10
`normal data input/output by the user is stored in the MLC area
`140. The SLC area 120 and the MLC area 140 constitute a
`main array.As illustratedinFIG.1 and FIG. 2, a flash memory
`in which an SLC area 120 and an MLC area 140 are mixed to
`constitute a main array is called a hybrid flash memory
`Meta data is stored in the hidden area 130 as data that
`camiot be randomly written/read by user, i.e., user-invisible
`added data. The meta data stored in the hidden area 130
`includes address mapping table of the FTL. Similar to the
`main array, the hidden area 130 includes an MLC area and an 20
`SLC area. Meta data is stored in the SLC area of the hidden
`area 130 to ensure an accuracy of data. As described above, if
`data are segmentally stored in the SLC area 120, MLC area
`140, and the hidden area 130 according to the characteristics
`of the data respectively, accuracy of the data as well as input/
`output speed of the data may be managed efficiently,
`SLC area and MLC area included in a hidden area 130 are
`partly assigned to a reserved block area 135. As illustrated in
`FIG. 3, a reserved block area 135 is divided into an SLC
`reserved block area 136 for replacing bad blocks of an SLC
`area 120 and an MLC reserved block area 137 for replacing
`bad blocks of an MLC area 140. Bad block replacement for
`the SLC area 120 and the MLC area 140 is done by the FTL.
`A result of the bad block replacement done by the FTL is
`stored in the foregoing hidden area 130 (e.g., SLC area of the
`hidden area 130) as meta data. Apart from the reserved block
`area 135, a hidden area in which meta data is stored maybe set
`as a data storage area. The result of the bad block replacement
`may be stored and managed with the shape of table. An initial
`value of a boundary between the SLC reserved block area 136 40
`and the MLC reserved block area 137 (SLC/MLC boundary.
`hereinafter referred to as "reserved area boundary") is set by
`the FTL. Due to cell characteristics, a possibility of generat(cid:173)
`ing a bad block in the MLC area 140 is higher than that of
`generating a bad block in the SLC area 120. Accordingly, a 45
`reserved area boundary may be defined such that category
`(i.e., size) of the MLC reserved block area 137 corresponding
`to the MLC area 140 is larger than that of the SLC block area
`136, as illustrated in FIG. 3.
`Referring to FIG. 3, the SLC reserved block area 136 and 50
`the MLC reserved block area 137 replace bad blocks in an
`arrow direction, i.e., from the outermost block of the SLC
`reserved block area 136 and the outermost block of the MLC
`reserved block area 136 to a block disposed at the reserved
`area boundary. The reserved area boundary defined by the
`FTL may have a fixed value or may vary with whether the
`SLC reserved block area 136 and the MLC reserved block
`area 137 are reserved.
`FIG. 4 and FIG. 5 exemplarily illustrate a method for
`assigning an SLC reserved block area 136 and an MLC
`reserved block area 137 in the case where the reserved area
`boundary is variable.
`Referring to FIG. 4, after memory blocks of the MLC
`reserved block area 137 corresponding to an MLC area 140
`are all used, the reserved area boundary may migrate ( or vary)
`in a direction of the SLC reserved block area 136. The migra(cid:173)
`tion of the reserved area boundary is done by means of the
`
`6
`FTL. With the migration of the reserved area boundary, a size
`of the SLC reserved block area 136' decreases while a size of
`the MLC reserved block area 137' increases. Moreover, new
`memory blocks are assigned to the MLC reserved block area
`137'. The new assigned memory blocks are memory blocks
`included in the SLC reserved block area 136 before the migra-
`tion of the reserved area boundary. Information on the
`reserved area boundary is updated and stored in the hidden
`area 130 ( e.g., a hidden information storage area including an
`SLC area of the hidden area 130) as meta data. In the case
`where the reserved area boundary migrates, two adjacent
`SLC blocks included in the SLC reserved block area 136 are
`assigned to a new MLC reserved block area 137' as one MLC
`block. The number of SLC blocks and the number of MLC
`15 blocks corresponding to the SLC blocks are variable with the
`number of bits stored in a memory cell. For example, four
`SLC blocks may correspond to one MLC block with the
`increase in the number of bits stored in each memory cell.
`Referring to FIG. 5, after memory blocks of the SLC
`reserved block area 136 corresponding to an SLC area 120 are
`all used, the reserved area boundary may migrate in direction
`of the MLC reserved block area 137. The migration of the
`reserved area boundary is done by means of the FTL. With the
`migration of the reserved area boundary, the size of the MLC
`25 reserved block area 137' decreases while the size of the SLC
`reserved block 136' increases. Information on the reserved
`area boundary is updated and stored in a hidden area 13 0 (e.g.,
`a hidden information storage area including the SLC area of
`the hidden area 130) as mete data. In the case where the
`30 reserved area boundary migrates, one MLC block included in
`the MLC reserved block area 137 is assigned in a new SLC
`reserved block area 136' as one SLC block. However, the
`above configuration is merely exemplary, and the number of
`SLC blocks and the number ofMLC blocks corresponding to
`35 the SLC blocks are variable with the number of bits stored in
`a memory cell. For example, one MLC block may be divided
`into two sub-MLC blocks and each of the sub-MLC blocks
`may be used as one SLC block.
`FIG. 6 and FIG. 7 are exemplary illustrations of a method
`for assigning memory blocks in the SLC reserved block area
`136 and the MLC reserved block area 137 in the case where
`a reserved area boundary is fixed.
`Referring to FIG. 6, after memory blocks of the MLC
`reserved block area 137 corresponding to the MLC area 140
`are all used, an area including non-replaced SLC blocks
`among the SLC reserved block area 136 may be used as the
`MLC reserved block area (see a deviant crease part). In this
`case, two adjacent SLC blocks are diverted to one MLC
`block. The diverted memory block is replaced with a bad
`block generated in an MLC area 140. An operation of divert(cid:173)
`ing SLC blocks to an MLC block and an operation of replac-
`ing a diverted memory block with a bad block are conducted
`by means of the FTL. Information on the function of a
`diverted block is stored in the hidden region 130 (e.g., a
`55 hidden information storage area including an SLC area of the
`hidden area 130) as meta data. The numberofSLC blocks and
`the number ofMLC blocks corresponding to the SLC blocks
`are variable with the number of bits stored in a memory cell,
`respectively. For example, four SLC blocks may be diverted
`60 to one MLC block with the increase in number of bits stored
`in each memory cell. The SLC blocks diverted to the MLC
`reserved block area are not limited to SLC blocks disposed at
`a specific position.
`Referring to FIG. 7, after memory blocks of the SLC
`65 reserved block area 137 corresponding to the SLC area 120
`are all used, an area including non-replaced MLC blocks
`among the MLC reserved block area 137 may be used as the
`
`Micron Ex. 1021, p. 11
`Micron v. Vervain
`IPR2021-01549
`
`

`

`US 7,453,712 B2
`
`7
`SLC reserved block area (see a deviant crease part). In this
`case, one MLC block is diverted to one SLC block. The
`diverted memory block is replaced with a bad block generated
`in the SLC area 120. An operation of diverting MLC blocks to
`the SLC block and an operation of replacing a diverted 5
`memory block with a bad block are conducted by means of
`the FTL. Information on the function of a diverted block is
`stored in a hidden region 130 (e.g., a hidden information
`storage area including an SLC area of the hidden area 130) as
`meta data. The number of SLC blocks and the number of 10
`MLC blocks corresponding to the SLC blocks are variable
`with the number of bits stored in a memory cell, respectively.
`For example, one MLC block may be divided into two sub(cid:173)
`MLC blocks and each of the sub-MLC blocks may be used as
`one SLC block. The MLC blocks diverted to an SLC reserved
`block area are not limited to MLC blocks disposed at a spe(cid:173)
`cific position.
`FIG, 8 shows an example of data storage for an SLC area
`220, SLC and MLC reserved block areas 236 and 237, and an
`MLC area 240 according to another embodiment of the
`present invention. The SLC area 220 and the MLC area 240
`constitute a main area, storing user data. A hidden informa(cid:173)
`tion storage area 230 and the SLC reserved block area 236 are
`disposed between the SLC area 220 and the MLC area 240.
`The MLC reserved block area 237 is disposed adjacent to the 25
`MLC area 240. The hidden information storage area 230, the
`SLC reserved block area 236, and the MLC reserved block
`area 237 constitute a hidden area in which user-invisible data
`is stored. In a hybrid flash memory device, a main array and a
`hidden area are formed on the same memory cell array. As 30
`illustrated in FIG. 8, the SLC reserved block area 236 and the
`MLC reserved block area 237 may be disposed on the same
`memory cell array to be physically spaced apart from each
`other.
`In the SLC area 220, the hidden information storage area
`230, and the MLC area 240 of FIG. 8 and those ofFIG. 2, their
`data storage methods are identical to each other while their
`dispositions are different from each other. Thus, the data
`storage methods based on respective data characteristics will
`not be described in further detail.
`FIG. 9 andFIG.10 are exemplary illustrations ofa method
`for assigning the SLC reserved block area 236 and the ML C
`reserved block area 237 of FIG. 8 in the case where a reserved
`area boundary is fixed.
`Referring to FIG. 9, after memory blocks of the MLC 45
`reserved block area 237 corresponding to the MLC area 240
`are all used, an area including non-replaced SLC blocks
`among the SLC reserved block area 236 may be used as the
`MLC reserved block area (see a deviant crease part). In this
`case, two adjacent SLC blocks are diverted to one MLC 50
`block. A method of diverting memory blocks illustrated in
`FIG. 9 is substantially identical to that illustrated in FIG. 6.
`The number of SLC blocks and the number of MLC blocks
`corresponding to the SLC blocks are variable with the number
`ofbits stored