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`UNITED STATES PATENT AND TRADEMARK OFFICE
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`_____________
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`_____________
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`MICRON TECHNOLOGY, INC.,
`Petitioner
`
`v.
`
`VERVAIN, LLC,
`Patent Owner
`_____________
`
`Case: IPR2021-01549
`U.S. Patent No. 9,997,240
`_____________
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`PATENT OWNER’S SUR-REPLY
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`IPR2021-01549
` U.S. Patent No. 9,997,240
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`CONTENTS
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`I.
`
`II.
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`INTRODUCTION ......................................................................................... 1
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`PO’S CONSTRUCTION OF “BLOCKS” IS CORRECT ........................ 1
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`III. THE CITED PRIOR ART DOES NOT RENDER THE
`CHALLENGED CLAIMS UNPATENTABLE .......................................... 7
`
`A.
`
`THE PETITION’S ARGUMENTS FOR CLAIM 1 BASED ON
`SUTARDJA IN GROUND 1 ARE DEFICIENT. ....................................... 7
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`
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`PETITIONER HAS NOT ESTABLISHED THAT THE CITED
`REFERENCES DISCLOSE OR SUGGEST LIMITATION [1.F] .......... 7
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`PETITIONER HAS NOT ESTABLISHED THAT THE CITED
`REFERENCES DISCLOSE OR SUGGEST LIMITATION [1.G] ........14
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`B.
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`THE PETITION’S IS DEFICIENT AS TO CLAIMS 2, 6, AND 7 IN
`GROUND 1 ...................................................................................................15
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`IV. PETITIONER’S EXPERT IS NOT CREDIBLE .....................................15
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`V. CONCLUSION ............................................................................................20
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`IPR2021-01549
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`
`TABLE OF AUTHORITIES
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` Page(s)
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`Cases
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`Amazon Web Services, Inc. v. Saint Regis Mohawk Tribe,
`IPR2019-00103, Paper No. 22 (PTAB May 10, 2019) ...................................... 10
`
`Evolusion Concepts, Inc. v. HOC Events, Inc.,
`22 F.4th 1361 (Fed. Cir. 2022) ............................................................................. 2
`
`Fantasia Trading LLC v. Cognipower, LLC,
`No. IPR2021-00071, 2022 WL 1616533 (PTAB May 11, 2022) ...................... 18
`
`Intelligent Bio-Systems, Inc. v. Illumina Cambridge, Ltd.,
`821 F.3d 1359 (Fed. Cir. 2016) ............................................................................ 9
`
`Liberty Mutual Ins. Co. v. Progressive Casualty Ins. Co.,
`CBM2012-00003, Paper No. 8 (PTAB Oct. 25, 2012) .................................. 9, 10
`
`Novo Nordisk A/S v. Eli Lilly & Co.,
`No. Civ.A.: 98-643 MMS, 1999 WL 1094213 (D. Del. Nov. 18,
`1999) ..................................................................................................................... 2
`
`Ultratec, Inc. v. CaptionCall, LLC,
`872 F.3d 1267 (Fed. Cir. 2017) .......................................................................... 18
`
`Xilinx, Inc. v. Analog Devices, Inc.,
`No. IPR2020-01564, 2022 WL 947004 (PTAB Mar. 11, 2022) ........................ 19
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`ii
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`Exhibit
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`EXHIBIT LIST
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`Description
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`Ex. 2001 Declaration of Dr. Sunil Khatri
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`IPR2021-01549
` U.S. Patent No. 9,997,240
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`
`Previously
`Submitted
`X
`
`Ex. 2002 Chen et al., Ultra MLC Technology Introduction,
`Advantech Technical White Paper (Oct. 5, 2012)
`(“Chen”)
`
`Ex. 2003 Excerpts from Micheloni et al., Inside NAND Flash
`Memories (1st ed. 2010) (“Micheloni”)
`
`Ex. 2004 U.S. Patent No. 10,950,300 to G.R. Mohan Rao (“’300
`Patent”)
`
`Ex. 2005 Microsoft Computer Dictionary definition for “data
`integrity”
`
`Ex. 2006 Hargrave’s Communications Dictionary definition for
`“data integrity”
`
`Ex. 2007 https://www.law360.com/articles/1381597/albright-says-
`he-ll-very-rarely-put-cases-on-hold-for-ptab
`
`Ex. 2008 Docket Sheet for Case. No. 6:21-cv-487-ADA; Vervain v.
`Micron Technology et al.; U.S. District Court, Western
`District of Texas.
`
`Ex. 2009 Exhibit C-3, Invalidity Claim Chart for the ’240 Patent
`based on U.S. Patent Application Pub. No. 2011/0099460
`(“Dusija”)
`
`Ex. 2010 Exhibit C-18, Invalidity Claim Chart for the ’240 Patent
`based on U.S. Patent Application Pub. No. US
`2008/0140918 (“Sutardja”)
`
`Ex. 2011 Micron’s Preliminary Invalidity Contentions for U.S.
`Patent Nos. 8,891,298; 9,196,385; 9,997,240; and
`10,950,300; Case. No. 6:21-cv-487-ADA; Vervain v.
`Micron Technology et al.; U.S. District Court, Western
`
`iii
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`X
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`X
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`X
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`IPR2021-01549
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`District of Texas.
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`Ex. 2012 Claim Construction Order in Vervain v. Micron Tech.,
`Inc., No. 6:21-cv-487-ADA (W.D. Tex.) and Vervain v.
`Western Digital Corp., No. 6:21-cv-488-ADA (W.D.
`Tex.) (Jan. 24, 2022)
`
`Ex. 2013 Intentionally Omitted
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`Ex. 2014 Declaration of Dr. Sunil Khatri in Support of Patent
`Owner’s Response
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`Ex. 2015 Transcript of June 10, 2022 Deposition of Dr. David Liu
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`Ex. 2016 U.S. Patent No. 8,285,940
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`Ex. 2017-
`2019
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`Intentionally omitted
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`Ex. 2020 Transcript of November 1, 2022 Deposition of Dr. David
`Liu
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`X
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`X
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`iv
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`IPR2021-01549
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`I.
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`INTRODUCTION
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`Pursuant to the Board’s Scheduling Order (Paper No. 11) and the parties’ joint
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`Notice of Stipulation to Change to Due Dates 2 and 3 (Paper No. 19), Patent Owner
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`Vervain, LLC (“Patent Owner” or “PO”) files this Sur-Reply. In its Reply (Paper
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`No. 23), Petitioner presents incorrect claim construction arguments and again
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`presents incorrect arguments regarding the Sutardja reference, as well as some
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`impermissible new arguments that Petitioner failed to include in the Petition.
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`Further, the deposition testimony of Petitioner’s expert Dr. Liu indicates that he is
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`not credible, and the Board should give his opinions little or no weight. When asked
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`about the portions of the specification that undermine Petitioner’s claim construction
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`(e.g., the controller determining which physical block to use), Dr. Liu’s testimony
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`was particularly evasive and he refused to fully answer the questions. Petitioner’s
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`arguments are insufficient to establish by a preponderance of the evidence that the
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`challenged claims (claims 1-2 and 6-7) are unpatentable. The Board should confirm
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`the patentability of the challenged claims.
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`II.
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`PO’S CONSTRUCTION OF “BLOCKS” IS CORRECT
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`The Board should adopt Patent Owner’s construction of “blocks.” As an
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`initial matter, whether “the Board already rejected PO’s attempt to limit ‘blocks’ to
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`‘physical blocks’” (Reply, 3) is not dispositive. The Board noted in its institution
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`decision that “[a]t this stage of the proceeding,” it was not adopting a certain
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`1
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`construction. Decision 16. The Board further noted that “Patent Owner has not
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`directed us to sufficient evidence to support its implied construction,” and “Dr.
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`Khatri’s testimony also is based on an unsupported assumption,” id., but such
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`statements by the Board were merely at the start of trial (at the institution stage), and
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`Patent Owner has subsequently explicitly presented (in its Response) claim
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`construction arguments and provided supporting evidence, including expert
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`testimony. Response, 25-29 (citing Ex. 2014).
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`Petitioner argues that because the ’240 patent includes the word “block[s]”
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`instead of “physical block[s]” in its claims, Patent Owner’s construction should
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`somehow not be adopted. Reply, 3. First, Patent Owner’s construction is not
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`“physical block[s],” but rather “in a non-volatile memory, a physical group of
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`memory cells that must be erased together,” Response, 25-26, so Patent Owner’s
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`construction clarifies the meaning of “blocks” in a manner different than the
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`examples from Novo Nordisk and Evolusion cited by Petitioner (Reply, 3). Novo
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`Nordisk A/S v. Eli Lilly & Co., No. Civ.A.: 98-643 MMS, 1999 WL 1094213 (D.
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`Del. Nov. 18, 1999); Evolusion Concepts, Inc. v. HOC Events, Inc., 22 F.4th 1361
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`(Fed. Cir. 2022). Namely, Patent Owner is not merely arguing that the construction
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`of a term X is “human X” or “new X,” or something else that itself includes the “X”
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`in the construction.
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`2
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`Moreover, here the claim language does indicate the physical nature of the
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`group of memory cells. Claim 1 recites that:
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`the controller is further adapted to determine which of the blocks
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`of the plurality of the blocks in the MLC and SLC non-volatile
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`memory modules are accessed most frequently and wherein the
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`controller segregates those blocks that receive frequent writes
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`into the at least one SLC non-volatile memory module and those
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`blocks that receive infrequent writes into the at least one MLC
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`nonvolatile module, and maintain a count value of the blocks in
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`the MLC non-volatile memory module determined to have
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`received frequent writes and that are accessed most frequently on
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`a periodic basis when the count value is a predetermined count
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`value, transfer the contents of the counted blocks in the MLC
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`non-volatile memory module determined to have received
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`frequent writes after reaching the predetermined count value to
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`the SLC non-volatile memory module…
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`Ex. 1005, 7:55-8:4; see also id., 8:37-59 (reciting “controller” performing various
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`functionality regarding “blocks”). Thus, the controller performs the foregoing
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`claimed functionality. The specification explains that the controller performs such
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`functionality on a physical group of memory cells (not a logical block).
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`For example, as Patent Owner explained in its Response, the ’240 patent
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`teaches that the controller (designated with reference numeral 14 in Figure 1)
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`“determines which physical block to use each time data is programmed,” making
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`3
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`clear the physical aspect. Response, 27 (citing Ex. 1005, 3:16-31).1 Similarly, the
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`specification explains that programming a block requires an erase (Ex. 1005, 3:47-
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`49), and that the controller erases blocks (id., 3:24-31). Since claims 1 and 6 recite
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`“erasable blocks” (id., 7:31-34, 8:21-24) and further recite the controller performing
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`functionality regarding those “blocks,” the specification thus provides context. The
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`specification explicitly states that from the controller’s point of view, “physical” is
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`the operative word, as noted above. Ex. 1005, 3:19-20.
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`Petitioner points to the surrounding claim language as allegedly supporting its
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`position, stating that “[t]his claim language, as PO’s expert confirms, ‘map[s] logical
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`blocks to physical blocks.’” Reply, 4. But the portion of Dr. Khatri’s declaration
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`cited by Petitioner merely acknowledges that there are such things as logical and
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`physical blocks, and a mapping between the two. The issue at hand, however, is the
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`meaning of the “blocks” recited in claims 1 and 6. Claims 1 and 6 do not recite
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`“logical blocks,” contrary to what Petitioner seems to be suggesting. Context
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`matters, and as noted above, the context by way of both the claim language and the
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`specification supports Patent Owner, not Petitioner.
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`Petitioner argues that “[o]ne cannot ‘segregate’ or ‘allocate’ an MLC physical
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`block into the SLC module, e.g., physically relocate that block.” Reply, 5. Petitioner
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`1 Emphasis added herein by Patent Owner unless indicated otherwise.
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`4
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`appears to be setting up and knocking down a strawman. Claim 1 and 6 do not recite
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`“physically relocat[ing]” blocks. But claim 1 recites that the “blocks” are “blocks
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`in the MLC and SLC non-volatile memory modules” (Ex. 1005, 7:56-57; see also
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`id., 7:63-64). And claims 1 and 6 both recite that the “blocks” are comprised in
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`MLC and SLC memory modules. Id., 7:31-34, 8:21-24. MLC (multiple level cell)
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`and SLC (single level cell) refer to memory cells in flash memory (Ex. 2014, ¶30),
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`e.g., implemented with transistors—and thus physical (as opposed to logical) groups
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`of memory cells. Id., ¶¶31-32. Thus, erasable “blocks” in the context of claims 1
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`and 6 are erasable physical groups of MLC or SLC memory cells that the controller
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`erases.
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`Petitioner argues that logical blocks were known to be erasable. Reply, 5-6.
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`But, Petitioner cites references such as Exhibit 1062, which disclose a host (not
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`controller) issuing a sector erase command to erase a logical sector. Id. (citing Ex.
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`1062, 2:10-34). As noted above, claims 1 and 6 recite functionality that the
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`controller performs regarding the claimed “blocks,” and the specification explains
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`that the controller deals with physical groups of memory cells. The portion of
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`Exhibit 1062 cited by Petitioner (Reply, 6) does not indicate whether a controller (as
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`required by claims 1 and 6 of the ’240 patent) is performing the functionality cited
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`by Petitioner. As explained by the ’240 patent, a host processor 12 shown in Figure
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`1 (or host, as in Exhibit 1062) deals with logical blocks (Ex. 1005, 2:15-21), i.e., is
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`5
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`aware of the blocks at a higher level of abstraction than the controller 14 is aware.
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`Ex. 1005, FIG. 1, 3:19-31, 3:46-49.
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`Claims 1 and 6 recite that the “erasable blocks” are within MLC and SLC
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`memory modules. Id., 7:31-34, 8:21-24. MLC and SLC refer to memory cells in
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`flash memory (Ex. 2014, ¶30), e.g., implemented with transistors—and thus
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`physical (as opposed to logical) groups of memory cells. Id., ¶¶31-32. Thus,
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`erasable “blocks” in the context of claims 1 and 6 are erasable physical groups of
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`MLC or SLC memory cells that the controller (as opposed to host) erases.
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`The ’240 patent discloses that physical blocks are programmed (Ex. 1001,
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`3:2-3) and that writing and programming are the same operation (id., 3:28).
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`Therefore, because writes are to erased blocks (id., 3:8), erased blocks are physical
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`groups of memory cells. Ex. 1059, 112:14-117:2.
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`In a footnote, Petitioner states that “it makes little sense to argue that the 240
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`patent would define ‘erase’ to exclude host erases because the 240 specification and
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`claims refer to host accesses.” Reply, 5-6 n.3. But Petitioner ignores that claims 1
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`and 6 recite functionality of the controller (not host), which performs erases on
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`blocks that are physical groups of memory cells. Similarly, Petitioner’s reliance on
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`the “map[]” limitation of claims 1 and 6 (id., 6) is unavailing, because the controller
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`performs that mapping, and the controller deals with blocks at a physical level. And
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`likewise, Petitioner’s statements that “[c]laims 1 and 6 later confirm that the ‘block’
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`6
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`also has a logical block form with the ‘map[]’ limitations” and “[t]his shows that
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`‘block’ includes both forms” (id.) misses the mark, as the claims make clear that the
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`mapping is performed by the controller, and the controller performs erases on blocks
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`that the controller regards as physical groups of cells.
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`III. THE CITED PRIOR ART DOES NOT RENDER THE
`CHALLENGED CLAIMS UNPATENTABLE
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`A. The Petition’s Arguments for Claim 1 Based on Sutardja in
`Ground 1 are Deficient.
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`As explained below, the Reply includes several incorrect arguments regarding
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`limitations [1.F] and [1.G].
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`
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`Petitioner Has Not Established that the Cited References
`Disclose or Suggest Limitation [1.F]
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`The Reply states that Patent Owner’s arguments for limitation [1.F] cannot be
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`correct due to the claim construction issue regarding “blocks.” Reply, 9-13. But as
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`explained above in Section II, Patent Owner’s construction is correct. Incidentally,
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`Petitioner seems unwilling to acknowledge Patent Owner’s actual construction for
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`“blocks” (i.e., “in a non-volatile memory, a physical group of memory cells that must
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`be erased together,” see Response, 25-26), instead merely mentioning “physical
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`block” numerous times. Reply, 9; see also id., 10-13. Under Patent Owner’s
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`construction, Sutardja’s disclosures cited in the Petition, and the Petition’s
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`arguments based on such disclosures, are deficient.
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`7
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`The Reply points to a statement in a footnote of the Board’s institution
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`decision. Reply, 9-10 (citing Decision (Paper No. 10), 16 n.2). That footnote
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`mentions paragraph [0111] of Sutardja and states regarding that paragraph that
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`Sutardja “teaches ‘track[ing] the number of times each block has been erased or
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`written’ and then mapping an incoming logical address ‘to the physical address’ of
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`‘the block of memory that has been written to the least.’” Decision, 16 n.2. As Patent
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`Owner noted in its Response, paragraph [0111] of Sutardja mention that the wear
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`leveling may track the number of times that each block has been erased or written,
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`and there is no mention in that paragraph regarding determining those blocks that
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`are accessed most frequently, or using that information to segregate blocks.
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`Response, 37-38. Sutardja’s paragraph [0111] discloses “select[ing] the block of
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`memory that has been written to the least from among the available blocks,” which
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`is different from determining the blocks that are accessed most frequently. Ex. 1011,
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`¶[0111]; Response, 38.
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`The Reply mentions Dusija’s disclosures. Reply, 10. But as noted in Patent
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`Owner’s Response, the Petition includes a meager discussion of Dusija for limitation
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`[1.F.i], citing a single paragraph (paragraph [0153]) of Dusija that mentions block
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`erases. Response, 35. The Petition does not allege that Dusija discloses many of the
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`features of limitation [1.F], instead relying on Sutardja for such features. The
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`Response noted problems in the Petition’s obviousness combination of Dusija and
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`8
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`Sutardja for limitation [1.F]. See, e.g., Response, 38-39. With Sutardja’s
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`deficiencies regarding limitation [1.F], it is insufficient for Petitioner to merely point
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`to Dusija without setting forth reasoned analysis regarding Petitioner’s proposed
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`obviousness combination. Moreover, Petitioner mischaracterizes Patent Owner’s
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`argument when Petitioner states that “Sutardja’s disclosures expressly contradict
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`PO’s implicit argument that some sort of modification to Sutardja is necessary.”
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`Reply, 11. That is not Patent Owner’s “implicit argument”—indeed, Petitioner
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`appears to misunderstand its own unpatentability ground, which is Dusija in view of
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`Sutardja (and not the other way around). The reasoned analysis that was called for
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`(and absent in the Petition) is analysis regarding modification to Dusija in view of
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`Dusija’s deficiencies for limitation [1.F].
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`The Reply’s arguments regarding dependent claims 8 and 13 are new
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`arguments and/or new evidence that Petitioner did not include in its Petition.
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`Intelligent Bio-Systems, Inc. v. Illumina Cambridge, Ltd., 821 F.3d 1359, 1366,
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`1369-71 (Fed. Cir. 2016); see also Liberty Mutual Ins. Co. v. Progressive Casualty
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`Ins. Co., CBM2012-00003, Paper No. 8 at 10 at 10 (PTAB Oct. 25, 2012) (Paper 8)
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`(stating that the Board is required to “address only the basis, rationale, and reasoning
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`put forth by the Petitioner in the petition”).
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`Given that Sutardja at most discloses selecting a block that has been written
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`to the least, there is simply not enough basis for Petitioner to prevail on its
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`9
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`obviousness combination. And it is not the Board’s role to fill in gaps in the
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`Petition’s analysis. See Liberty Mutual, CBM2012-00003, Paper No. 8 at 10 (stating
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`that the Board is required to “address only the basis, rationale, and reasoning put
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`forth by the Petitioner in the petition, and resolve all vagueness and ambiguity in
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`Petitioner’s arguments against the Petitioner”); Amazon Web Services, Inc. v. Saint
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`Regis Mohawk Tribe, IPR2019-00103, Paper No. 22 at 17 (PTAB May 10, 2019)
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`(“The burden is on Petitioner, not the Board, to specify with particularity how Lange
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`teaches [various claimed features].”).
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`The Reply states that “PO is arguing that Dusija in view of Sutardja does not
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`render obvious determining which blocks are frequently written because the relevant
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`disclosures are operating on a single block.” Reply, 13. But Petitioner is setting up
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`and knocking down a strawman. As Patent Owner noted in its Response, “paragraph
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`[0111], cited by the Petition, explicitly discloses a block which has been written to
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`the least.” Response, 40 (emphasis in original). The Response further explained,
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`regarding other paragraphs of Sutardja relating to wear leveling and logical
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`addresses, that “[n]one of the cited paragraphs which disclose ‘write frequencies’
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`teach or suggest determining the blocks which are accessed most frequently; rather,
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`the Petition simply states in a conclusory manner that the claim language is
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`satisfied.” Reply, 40. Patent Owner even emphasized, with bold and italics, the
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`pertinent words relating to this distinction between Sutardja’s disclosure and
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`10
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`limitation [1.F]. Id. Petitioner’s characterization of Patent Owner’s argument as a
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`“‘single block’ argument” is misleading. Reply, 15.
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`As noted in Patent Owner’s Response, Sutardja does not seek to segregate
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`contents of blocks to SLC or MLC in particular, unlike the approach claimed in
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`limitation [1.F]. Response, 43. Petitioner’s arguments to the contrary in the Reply
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`are incorrect. In its Reply, Petitioner ignores that paragraph [0108] of Sutardja
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`plainly states “[t]he first solid-state nonvolatile memory 204 may include single-
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`level cell (SLC) flash memory or multi-level cell (MLC) flash memory [and] [t]he
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`second solid-state nonvolatile memory 206 may include single-level cell (SLC) flash
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`memory or multi-level cell (MLC) flash memory.” Ex. 1011, ¶[0108]. Petitioner
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`and its expert Dr. Liu have taken the position that the second memory is SLC, but
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`that flies in the face of Sutardja paragraph [0108], which explicitly states that “[t]he
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`second solid-state nonvolatile memory 206 may include single-level cell (SLC) flash
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`memory or multi-level cell (MLC) flash memory.” At his deposition, Dr. Liu was
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`unwilling to acknowledge that Sutardja’s first memory may include SLC flash
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`memory, despite paragraph [0108] stating that “[t]he first solid-state nonvolatile
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`memory 204 may include single-level cell (SLC) flash memory” (SLC is even the
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`first of the two options mentioned at that paragraph for the first memory, making Dr.
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`Liu’s dismissal of that disclosure even less plausible). Ex. 2020, 110:15-114:6; infra
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`Section IV. And Dr. Liu testified at his deposition that it would have been obvious
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`11
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`to have the first and second memories be MLC and SLC, respectively (infra Section
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`IV), but there is no such obviousness argument or analysis in the Petition or Dr. Liu’s
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`original declaration.
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`Furthermore, Dr. Liu’s deposition testimony regarding “pick[ing]” a type of
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`memory for each of Sutardja’s first/second memories is revealing. Ex. 2020, 199:8-
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`12; see also id., 204:21-205:24. He testified that once the memory type (SLC/MLC)
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`is picked for the first memory, that immediately forces the opposite memory type
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`(MLC/SLC) to be used for the second memory. Id., 199:8-12, 205:19-24. But by
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`picking a type of memory for the first memory, clearly that means there are multiple
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`options that are capable of being picked (otherwise, there would be no picking at
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`all). As an analogy—consider a waiter handing a menu to each of two restaurant
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`patrons, where the menu indicates that the first patron’s order can include steak or
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`pasta, and the second patron’s order can include steak or pasta (mirroring the
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`situation of Sutardja paragraph [0108]). It would be absurd to conclude from such
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`a menu-related scenario that the first patron (who can pick a food type, applying the
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`logic of Dr. Liu’s deposition testimony) can only order pasta and the second patron
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`can only order steak—in that case, there would be no point in even letting the first
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`patron pick.
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`It is apparent from a plain read of Sutardja paragraph [0108] that Sutardja is
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`indifferent (or neutral) to the usage of SLC vs. MLC for each of the memories.
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`12
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`Sutardja provided a symmetrical disclosure with respect to SLC and MLC at
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`paragraph [0108], and Dr. Liu’s unwillingness to acknowledge that fact indicates
`
`how problematic that disclosure is for Petitioner’s position.
`
`In its Reply, Petitioner mentions Dr. Khatri’s deposition testimony regarding
`
`used parts. Reply, 16-17. But the Reply fails to note that in that line of questioning,
`
`Petitioner was asking Dr. Khatri about an issue regarding the lifetime of SLC and
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`MLC chips, and Dr. Khatri was simply fully answering the question in that context
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`and explaining how a POSITA would interpret this since Dusija does not disclose
`
`whether the SLC and MLC chips are new or old. Ex. 1059, 73:4-74:16. Contrary
`
`to the Reply’s characterization, such testimony regarding used parts was not Dr.
`
`Khatri's only basis for concluding that Sutardja does not necessarily require the
`
`second memory to be SLC. The above discussion regarding a plain read of Sutardja
`
`paragraph [0108] shows that it is Petitioner that is stretching the facts.
`
`The Reply states that “Sutardja’s use of ‘normalization of the wear levels’ is
`
`an optional feature, and Sutardja does not discuss it in the context of the first and
`
`second showings” (Reply, 17), but fails to note Sutardja’s disclosure that “[w]ear
`
`levels as used herein, unless otherwise noted, are normalized wear levels” (Ex. 1011,
`
`¶[0162])—despite later citing that same paragraph of Sutardja (Reply, 18, citing Ex.
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`1011, ¶[0162]). And as explained above, the Reply’s statement that “the second
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`13
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`memory is SLC” (Reply, 17-18, emphasis added) is an unreasonable position in light
`
`of paragraph [0108] of Sutardja.
`
`
`
`Petitioner Has Not Established that the Cited References
`Disclose or Suggest Limitation [1.G]
`
`Regarding limitation [1.G], the Reply initially asserts that Patent Owner’s
`
`position is incorrect due to Patent Owner’s construction of “blocks” allegedly being
`
`incorrect (Petitioner again misstates Patent Owner’s construction when making this
`
`assertion, see Reply, 18). But as explained above in Section II, Patent Owner’s
`
`construction is correct.
`
`The Reply contends that PO argues that the Petition relies on disparate
`
`portions of Sutardja relating to logical and physical blocks. Reply, 22. Petitioner is
`
`incorrect, as Patent Owner specifically showed that some disclosures that Petitioner
`
`pointed to pertain to logical blocks and other (disparate) disclosures that they pointed
`
`to relate to physical blocks (assuming, arguendo, that paragraph [0149] of Sutardja
`
`relates to “blocks” under the proper construction). Response, 38.
`
`Regarding its “individual count” argument, Petitioner’s Reply further states
`
`that “Dr. Khatri admits that if there is remapping to a new block, there must be a
`
`transfer of the data to the new block.” Reply, 20. The Reply is inaccurate, as the
`
`cited portion of Dr. Khatri’s testimony at Exhibit 1059, 60:15-63:11 does not pertain
`
`to, or mention, transfer of data to a new block. The Reply states that “[i]t is wrong”
`
`14
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`(apparently referring to Dr. Khatri’s analogy discussed in his testimony at Exhibit
`
`1059, 67:19-70:7) “because Sutardja’s ‘data shift” and “wear analysis’ relate to the
`
`same component of Sutardja.” Reply, 20. But clearly the data shift process and
`
`wear analysis processes are different processes in Sutardja (e.g., as noted by their
`
`different names and different entry points shown above in Figure 7B), and they relate
`
`to different functions and occur at different times, as explained in Patent Owner’s
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`Response. Response, 50.
`
`B.
`
`The Petition’s is Deficient as to Claims 2, 6, and 7 in Ground 1
`
`Petitioner’s Reply does not include any arguments specific to independent
`
`claim 6 or dependent claims 2 and 7. See generally Reply. Therefore, as explained
`
`in Patent Owner’s Response (Response, 52), the Petition’s analysis of these claims
`
`is flawed at least due to the deficiencies (discussed above and in the Response) of
`
`the Petition’s analysis of claim 1.
`
`IV. PETITIONER’S EXPERT IS NOT CREDIBLE
`
`The deposition testimony of Petitioner’s expert Dr. Liu shows in numerous
`
`ways that he is not credible. The Board should give his opinions little or no weight.
`
`For example,
`
`regarding Sutardja’s
`
`first and
`
`second non-volatile
`
`semiconductor (NVS) memories (discussed above in Section III.A.1), Dr. Liu
`
`initially testified with certitude that “to be quite honest, it is my opinion that the
`
`POSA will find it obvious, and that’s the only way, that the first NVS is MLC and
`
`15
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`second NVS SLC” and “to try to say otherwise ·I don’t believe is credible.” Ex.
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`2020, 99:1-17; see also id., 98:2-25. When further questioned about “the only way”
`
`that he mentioned, he was evasive (id., 99:18-101:2) but ultimately took back his
`
`testimony. Id., 101:3-16 (“Maybe I will take -- take back the ‘only.’”); see also id.,
`
`101:17-21. He even conceded that his testimony was incorrect due to him getting
`
`“carried away.” Id., 126:1-7 (“[P]erhaps I -- I misspoke. I was trying to say that the
`
`only obvious way -- that the most obvious way. I’m trying to say most obvious way,
`
`but sometimes I get carried away. Maybe I use the extreme. I guess I shouldn’t – I
`
`shouldn’t use the most extreme…”). It is apparent that Dr. Liu’s testimony is
`
`unreliable.
`
`And when questioned about his testimony regarding “credible,” he conceded
`
`that he should not have testified in that manner, either. Id., 102:12-103:14 (“Maybe
`
`I should not use the word credible. … I shouldn’t use the word ‘credible’”), 128:10-
`
`12 (“I would not use the word ‘credible.’· I should not have used the word
`
`‘credible.’”); see also id., 128:6-25. Absurdly, when asked whether another
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`implementation would be “credible,” Dr. Liu feigned ignorance regarding
`
`“credible”—even though it was he who brought up the word in the first place. Id.,
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`129:1-14 (“I don't know the definition of ‘credible’ as you state it”). It is Dr. Liu
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`that is not credible.
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`16
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`Dr. Liu refused to acknowledge clear teachings in the prior art. Despite
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`paragraph [0108] of Sutardja plainly stating that “[t]he first…memory 204 may
`
`include single-level cell (SLC) flash memory or multi-level cell (MLC) flash
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`memory” and “[t]he second…memory 206 may include single-level cell (SLC)
`
`flash memory or multi-level cell (MLC) flash memory” (Ex. 1011, ¶[0108]). Dr.
`
`Liu refused to acknowledge that the first memory may include SLC and the second
`
`memory may include MLC. Ex. 2020, 110:15-114:6 (including 113:4-8, “Sutardja
`
`never explicitly described the reverse. Sutardja say[s] ‘may,’ ‘may,’ but never
`
`explicitly, whereas Sutardja does explicitly mention that first NVS being SLC and
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`second NVS being SLC.”). Clearly, Sutardja paragraph [0108] is symmetric in its
`
`descriptions of SLC and MLC, and Dr. Liu refused to acknowledge that.
`
`Bizarrely, Dr. Liu ignored the foregoing straightforward language of
`
`paragraph [0108], yet later testified regarding the first and second memories that “if
`
`I make the first one SLC, the second one necessarily would have to be MLC” (id.,
`
`199:3-5; see also id., 198:5-199:15)—conceding that the first memory can be SLC
`
`and the second memory can be MLC. However, the disclosure of paragraph [0108]
`
`does not teach or suggest such an exclusivity. And when asked why paragraph
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`[0108] says what it says, he oddly responded “I am not Sutardja” (id., 207:10-
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`208:1)—revealing that he does not understand Sutardja’s disclosure. Thus, not only
`
`did he stick his head in the sand regarding the plain text of paragraph [0108], he also
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`17
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`IPR2021-01549
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`does not understand it and talked out of both sides of his mouth regarding it—and
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`the Board should recognize that his testimony regarding the prior art is simply not
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`credible. Fantasia Trading LLC v. Cognipower, LLC, No. IPR2021-00071, 2022
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`WL 1616533, at *8 (PTAB May 11, 2022) (“[The witness’s] inconsistent testimony,
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`coupled with [his] initial failure to identify Zhu's bias circu
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