(12) United States Patent
`Conley
`
`USOO6901498B2
`US 6,901,498 B2
`May 31, 2005
`
`(10) Patent No.:
`(45) Date of Patent:
`
`(54) ZONE BOUNDARY ADJUSTMENT FOR
`DEFECTS IN NON-VOLATILE MEMORIES
`
`(75) Inventor: Kevin M. Conley, San Jose, CA (US)
`(73) Assignee: SanDisk Corporation, Sunnyvale, CA
`(US)
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 349 days.
`
`(*) Notice:
`
`(21) Appl. No.: 10/315,451
`(22) Filed:
`Dec. 9, 2002
`(65)
`Prior Publication Data
`US 2004/0111553 A1 Jun. 10, 2004
`(51) Int. Cl................................................. G06F 12/10
`(52) U.S. Cl. ....................................................... 711/173
`(58) Field of Search ................................. 711/103, 173,
`711/201; 714/7, 8; 365/230.01
`
`(56)
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`5,172,338 A 12/1992 Mehrotra et al.
`5,200,959 A
`4/1993 Gross et al.
`5,270,979 A 12/1993 Harari et al.
`5,315,541 A 5/1994 Harari et al.
`5,428,621 A 6/1995 Mehrotra et al.
`5,430,859 A 7/1995 Norman et al.
`5.532.962 A 7/1996 Auclair et al.
`5,602987 A 2/1997 Harari et al.
`5,663,901 A 9/1997 Wallace et al.
`5,677,872 A 10/1997 Samachisa et al.
`5,712,179 A
`1/1998 Yuan
`5,712,180 A
`1/1998 Guterman et al.
`
`5,724,284
`3/1998 Bill et al.
`5,890,192
`3/1999 Lee et al.
`5,930,167 A
`7/1999 Lee et al.
`3/2001 Blodgett ........................ 714/7
`6,199,177 B1 *
`6.252,800 B1
`6/2001 Chida
`6,275,436 B1
`8/2001 Tobita et al.
`6,377,500 B1 * 4/2002 Fujimoto et al. ...... 365/230.01
`6,426,893 B1
`7/2002 Conley et al.
`6,687,784 B2 * 2/2004 Douniwa et al. ........... 711/103
`OTHER PUBLICATIONS
`International Search Report mailed Jun. 14, 2004.
`International Search Report mailed Aug. 2, 2004.
`* cited by examiner
`Primary Examiner Kevin L. Ellis
`(74) Attorney, Agent, or Firm-Parsons Hsue & de Runtz
`LLP
`ABSTRACT
`(57)
`A non-volatile memory is divided into logical Zones by the
`card controller in order reduce the Size of the data Structures
`it uses for address translation. Zone boundaries are adjusted
`to accommodate defects allowed by memory test to improve
`card yields and to adjust boundaries in the field to extend the
`uSable lifetime of the card. Firmware Scans for the presence
`of defective blocks on the card. Once the locations of these
`blocks are known, the firmware calculates the Zone bound
`aries in Such a way that good blocks are equally distributed
`among the Zones. Since the number of goodblockS meets the
`card test criteria by the memory test criteria, defects will
`reduce card yield fallout. The controller can perform
`dynamic boundary adjustments. When defects occur, the
`controller can perform the analysis again and, if needed,
`redistributes the Zone boundaries, moving any user data.
`
`52 Claims, 6 Drawing Sheets
`
`80
`
`EXTERNAL
`NUt
`
`82
`
`BABLOCK
`NDICATION
`
`CONTROLLER
`EVALUATION MEMORY
`
`805
`
`EterMAN
`ZONEABLE
`
`
`
`807
`
`MOVE DATA
`
`809
`
`AUST
`BOJNARY
`
`8.
`
`
`
`DESIRE
`BOUNdARES
`STABLISHEp
`
`MO
`
`YE S 8
`13
`
`ACCSSMEMORY
`BASE ONZONE TABLE
`
`815
`
`STORE TABLE IN
`NON-WOLALE
`MEMORY
`
`Micron Ex. 1042, p. 1
`Micron v. Vervain
`IPR2021-01549
`
`

`

`U.S. Patent
`
`May 31, 2005
`
`Sheet 1 of 6
`
`US 6,901,498 B2
`
`Memory
`Control
`
`412
`CS
`WS
`AS
`
`
`
`
`
`AD 7:O)
`
`YDEC
`
`SA/ Prog
`
`Data Register
`
`402
`
`454
`
`404
`
`(PRIOR ART)
`
`
`
`
`
`Host
`OS
`Interface
`
`
`
`Controller
`1
`301
`ECC
`
`
`
`Flash
`Memory
`Device
`
`Flash
`Memory
`Device
`
`3O2
`
`Flash
`Media
`Interface
`
`Flash
`Memory
`Device
`
`FIG.2
`(PRIOR ART)
`
`Micron Ex. 1042, p. 2
`Micron v. Vervain
`IPR2021-01549
`
`

`

`U.S. Patent
`
`May 31, 2005
`
`Sheet 2 of 6
`
`US 6,901.498 B2
`
`
`
`ECC
`GENERATOR
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`CONTROLLER
`RAM
`
`
`
`MICRO
`CONTROLLER
`
`BCP
`EXECUTION
`
`25
`
`CONTROLLER
`INTERFACE
`
`FLASH
`INTERFACE
`& CONTROL
`
`PROGRAM
`MEMORY
`
`
`
`DATA
`BUFFER
`MEMORY
`
`
`
`301 CONTROLLER CHIP
`
`TO / FROM
`HOST
`
`FIG. 3A
`
`
`
`MEMORY
`CHIP 1
`
`-21
`
`MEMORY
`CHIPN
`
`Micron Ex. 1042, p. 3
`Micron v. Vervain
`IPR2021-01549
`
`

`

`U.S. Patent
`
`May 31, 2005
`
`Sheet 3 of 6
`
`US 6,901,498 B2
`
`:
`
`
`
`
`
`
`
`MASTER
`REGISTER
`
`MASTER
`REGISTER
`
`MASTER
`REGISTER
`
`MASTER
`REGISTER
`
`
`
`
`
`SLAVE
`REGISTER
`
`SLAVE
`REGISTER
`
`SLAVE
`REGISTER
`
`SLAVE
`REGISTER
`
`PROG. &
`VERIFY
`& READ
`
`PROG. &
`VERIFY
`& READ
`
`PROG. &
`VERIFY
`& READ
`
`PROG. &
`VERIFY
`& READ
`
`39
`
`Eiu
`Se Ci ?
`
`Hill
`2
`OZ
`CD
`
`41
`
`CONTROL
`
`45
`
`|
`
`|
`
`CAD
`
`LI
`
`r
`HE ARRAY
`ARRAY
`ÜNif 83 UNT
`S
`1 55 2
`S
`51---55 52-
`56
`53
`9
`l 23 RRAY
`ARRAY
`ARRAY
`SR
`UNIT
`UNIT
`UNIT
`25 g
`4
`5
`6
`CC
`X-DECODE X-DECODE
`X-DECODE X-DECODE
`61 -
`62
`
`X-DECODE
`
`
`
`
`
`PROG. &
`VERIFY
`& READ
`
`
`
`PROG. &
`VERIFY
`& READ
`
`PROG. &
`VERIFY
`& READ
`
`
`
`PROG. &
`VERIFY
`& READ
`
`
`
`C
`
`i
`CO
`
`MASTER
`REGISTER
`
`FIG.3B
`
`Micron Ex. 1042, p. 4
`Micron v. Vervain
`IPR2021-01549
`
`

`

`U.S. Patent
`
`May 31, 2005
`
`Sheet 4 of 6
`
`US 6,901.498 B2
`
`
`
`51 i
`
`513
`
`515
`5f 7 519
`521
`523
`
`SYSTEM
`BLOCKS
`
`ZONE O
`
`ZONE 1
`
`ZONE 2
`
`ZONE 3
`
`ZONE 4
`
`ZONE 5
`
`ZONE 7
`
`B
`
`ZONE 8
`
`C
`B
`A
`
`ZONE 9
`
`721
`
`711
`712
`
`705
`704
`703
`702
`7Of
`
`FIG.6
`
`Micron Ex. 1042, p. 5
`Micron v. Vervain
`IPR2021-01549
`
`

`

`U.S. Patent
`
`May 31, 2005
`
`Sheet 5 of 6
`
`US 6,901,498 B2
`
`
`
`Z ENW/Tlc3
`
`O ENVT1c]
`
`WE|| SÅS
`
`SXAOOTE
`
`0 ENOZ
`
`| ENOZ
`
`Z ENOZ
`
`9 ENOZ
`
`9 ENOZ
`
`9 ENOZ
`
`/ ENOZ
`
`8 ENOZ
`
`6 ENOZ
`
`Micron Ex. 1042, p. 6
`Micron v. Vervain
`IPR2021-01549
`
`

`

`U.S. Patent
`
`May 31, 2005
`
`Sheet 6 of 6
`
`US 6,901.498 B2
`
`-8Of
`
`EXTERNAL
`INPUT
`
`802
`
`BAD BLOCK
`INDICATION
`
`
`
`
`
`
`
`CONTROLLER
`EVALUATION MEMORY
`
`
`
`
`
`805
`
`DETERMINE
`ZONE TABLE
`
`
`
`MOVE DATA
`
`809
`
`ADJUST
`BOUNDARY
`
`811
`
`DES RED
`BOUNDARES
`ESTABLISHED
`
`ACCESS MEMORY
`BASED ONZONE TABLE
`
`
`
`STORE TABLE IN
`NON-VOLATLE
`MEMORY
`
`FIG.7
`
`
`
`
`
`
`
`
`
`
`
`Micron Ex. 1042, p. 7
`Micron v. Vervain
`IPR2021-01549
`
`

`

`1
`ZONE BOUNDARY ADJUSTMENT FOR
`DEFECTS IN NON-VOLATILE MEMORIES
`
`US 6,901,498 B2
`
`2
`400 of flash EEPROM cells are included, each array having
`its own row decoder (XDEC) 401 and column decoder
`(YDEC) 402, a group of sense amplifiers and program
`control circuitry (SA/PROG) 454 and a data register 404.
`Presently, the memory cells usually include one or more
`conductive floating gates as Storage elements but other long
`term electron charge Storage elements may be used instead.
`The memory cell array may be operated with two levels of
`charge defined for each Storage element to therefore Store
`one bit of data with each element. Alternatively, more than
`two storage States may be defined for each Storage element,
`in which case more than one bit of data is Stored in each
`element.
`If desired, a plurality of arrays 400, together with related
`X decoders, Y decoders, program/verified circuitry, data
`registers, and the like are provided, for example as taught by
`U.S. Pat. No. 5,890,192, issued Mar. 30, 1999, and assigned
`to SanDisk Corporation, the assignee of this application,
`which is hereby incorporated by this reference. Related
`memory System features are described in co-pending patent
`application Ser. No. 09/505,555, filed Feb. 17, 2000 by
`Kevin Conley et al., which application is expressly incor
`porated herein by this reference.
`The external interface I/O bus 411 and control signals 412
`can include the following:
`CS-Chip Select. Used to activate flash memory inter
`face.
`RS-Read Strobe. Used to indicate the I/O bus is being
`used to transfer data from the memory array.
`WS-Write Strobe. Used to indicate the I/O bus is being
`used to transfer data to the memory array.
`AS-Address Strobe. Indicates that the I/O bus is being
`used to transfer address information.
`AD7:0-Address/Data Bus This I/O bus is used to
`transfer data between controller and the flash memory
`command, address and data registers of the memory
`control 450.
`In addition to these Signals, it is also typical that the
`memory has a means by which the Storage Subsystem
`controller may determine that the memory is busy perform
`ing Some task. Such means could include a dedicated Signal
`or a status bit in an internal memory register that is acces
`sible while the memory is busy.
`This interface is given only as an example as other Signal
`configurations can be used to give the same functionality.
`FIG. 1 shows only one flash memory array 400 with its
`related components, but a multiplicity of Such arrayS can
`exist on a Single flash memory chip that share a common
`interface and memory control circuitry but have Separate
`XDEC, YDEC, SA/PROG and DATAREG circuitry in order
`to allow parallel read and program operations.
`Data is transferred from the memory array through the
`data register 404 to an external controller via the data
`registers coupling to the I/O bus AD7:0 411. The data
`register 404 is also coupled the Sense amplifier/
`programming circuit 454. The number of elements of the
`data register coupled to each Sense amplifier/programming
`circuit element may depend on the number of bits Stored in
`each storage element of the memory cells, flash EEPROM
`cells each containing one or more floating gates as the
`Storage elements. Each Storage element may store a plurality
`of bits, Such as 2 or 4, if the memory cells are operated in
`a multi-state mode. Alternatively, the memory cells may be
`operated in a binary mode to Store one bit of data per Storage
`element.
`The row decoder 401 decodes row addresses for the array
`400 in order to select the physical page to be accessed. The
`
`15
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`
`45
`
`BACKGROUND OF THE INVENTION
`This invention pertains to the field of semiconductor
`non-volatile data Storage System architectures and their
`methods of operation, and has application to data Storage
`Systems based on flash electrically erasable and program
`mable read-only memories (EEPROMs).
`A common application of flash EEPROM devices is as a
`mass data Storage Subsystem for electronic devices. Such
`Subsystems are commonly implemented as either removable
`memory cards that can be inserted into multiple host Systems
`or as non-removable embedded Storage within the host
`System. In both implementations, the Subsystem includes
`one or more flash devices and often a Subsystem controller.
`Flash EEPROM devices are composed of one or more
`arrays of transistor cells, each cell capable of non-volatile
`Storage of one or more bits of data. Thus flash memory does
`not require power to retain the data programmed therein.
`Once programmed however, a cell must be erased before it
`can be reprogrammed with a new data value. These arrays of
`cells are partitioned into groups to provide for efficient
`25
`implementation of read, program and erase functions. A
`typical flash memory architecture for mass Storage arranges
`large groups of cells into erasable blocks, wherein a block
`contains the Smallest number of cells (unit of erase) that are
`erasable at one time.
`In one commercial form, each block contains enough cells
`to Store one Sector of user data plus Some overhead data
`related to the user data and/or to the block in which it is
`Stored. The amount of user data included in a Sector is the
`Standard 512 bytes in one class of Such memory Systems but
`can be of Some other size. Because the isolation of indi
`vidual blocks of cells from one another that is required to
`make them individually erasable takes Space on the inte
`grated circuit chip, another class of flash memories makes
`the blockS Significantly larger So there is leSS Space required
`for Such isolation. But Since it is also desired to handle user
`data in much Smaller Sectors, each large block is often
`further partitioned into individually addressable pages that
`are the basic unit for reading and programming user data.
`Each page usually Stores one Sector of user data, but a page
`may store a partial Sector or multiple Sectors. A “Sector” is
`used herein to refer to an amount of user data that is
`transferred to and from the host as a unit.
`The Subsystem controller in a large block System per
`forms a number of functions including the translation
`between logical addresses (LBAS) received by the memory
`sub-system from a host, and physical block numbers (PBNs)
`and page addresses within the memory cell array. This
`translation often involves use of intermediate terms for a
`logical block number (LBN) and logical page. The controller
`also manages the low level flash circuit operation through a
`Series of commands that it issues to the flash memory
`devices via an interface bus. Another function the controller
`performs is to maintain the integrity of data Stored to the
`Subsystem through various means, Such as by using an error
`correction code (ECC).
`FIG. 1 shows a typical internal architecture for a flash
`memory device 131. The primary features include an input/
`output (I/O) bus 411 and control signals 412 to interface to
`an external controller, a memory control circuit 450 to
`control internal memory operations with registers for
`command, address and Status Signals. One or more arrayS
`
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`Micron Ex. 1042, p. 8
`Micron v. Vervain
`IPR2021-01549
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`

`

`3
`row decoder 401 receives row addresses via internal row
`address lines 419 from the memory control logic 450. A
`column decoder 402 receives column addresses via internal
`column address lines 429 from the memory control logic
`450.
`FIG.2 shows an architecture of a typical non-volatile data
`Storage System, in this case employing flash memory cells as
`the Storage media. In one form, this System is encapsulated
`within a removable card having an electrical connector
`extending along one side to provide the host interface when
`inserted into a receptacle of a host. Alternatively, the System
`of FIG.2 may be embedded into a host system in the form
`of a permanently installed embedded circuit or otherwise.
`The system utilizes a single controller 101 that performs
`high-level host and memory control functions. The flash
`memory media is composed of one or more flash memory
`devices, each Such device often formed on its own integrated
`circuit chip. The System controller and the flash memory are
`connected by a bus 121 that allows the controller 101 to load
`command, address, and transfer data to and from the flash
`memory array. (The bus 121 includes 412 and 411 of FIG.
`1.) The controller 101 interfaces with a host system (not
`shown) with which user data is transferred to and from the
`flash memory array. In the case where the system of FIG. 2
`is included in a card, the host interface includes a mating
`plug and Socket assembly (not shown) on the card and host
`equipment.
`The controller 101 receives a command from the host to
`read or write one or more Sectors of user data Starting at a
`particular logical address. This address may or may not align
`with the first physical page in a block of memory cells.
`In Some prior art Systems having large capacity memory
`cell blocks that are divided into multiple pages, the data
`from a block that is not being updated needs to be copied
`from the original block to a new block that also contains the
`new, updated data being written by the host. In other prior
`art Systems, flags are recorded with the user data in pages
`and are used to indicate that pages of data in the original
`block that are being Superceded by the newly written data
`are invalid. A mechanism by which data that partially
`Supercedes data Stored in an existing block can be written
`without either copying unchanged data from the existing
`block or programming flags to pages that have been previ
`ously programmed is described in co-pending patent appli
`cation “Partial Block Data Programming and Reading
`Operations in a Non-Volatile Memory”, Ser. No. 09/766,
`436, filed Jan. 19, 2001 by Kevin Conley, which application
`is expressly incorporated herein by this reference.
`Non-volatile memory Systems of this type are being
`applied to a number of applications, particularly when
`packaged in an enclosed card that is removable connected
`with a host System. Current commercial memory card for
`mats include that of the Personal Computer Memory Card
`International Association (PCMCIA), CompactFlash (CF),
`MultiMediaCard (MMC) and Secure Digital (SD). One
`Supplier of these cards is SanDisk Corporation, assignee of
`this application. Host Systems with which Such cards are
`used include personal computers, notebook computers,
`hand-held computing devices, cameras, audio reproducing
`devices, and the like. Flash EEPROM systems are also
`utilized as bulk mass Storage embedded in host Systems.
`Such non-volatile memory Systems include one or more
`arrays of floating-gate memory cells and a System controller.
`The controller manages communication with the host System
`and operation of the memory cell array to Store and retrieve
`user data. The memory cells are grouped together into
`blocks of cells, a block of cells being the Smallest grouping
`
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`US 6,901,498 B2
`
`15
`
`25
`
`4
`of cells that are Simultaneously erasable. Prior to writing
`data into one or more blocks of cells, those blocks of cells
`are erased. User data are typically transferred between the
`host and memory array in Sectors. A Sector of user data can
`be any amount that is convenient to handle, preferably leSS
`than the capacity of the memory block, often being equal to
`the standard disk drive sector size, 512 bytes. In one
`commercial architecture, the memory System block is sized
`to Store one Sector of user data plus overhead data, the
`overhead data including information Such as an error cor
`rection code (ECC) for the user data stored in the block, a
`history of use of the block, defects and other physical
`information of the memory cell block. Various implemen
`tations of this type of non-volatile memory System are
`described in the following U.S. patents and pending appli
`cations assigned to SanDisk Corporation, each of which is
`incorporated herein in its entirety by this reference: U.S. Pat.
`Nos. 5,172,338, 5,602,987, 5,315,541, 5,200,959, 5,270,
`979, 5,428,621, 5,663,901, 5,532,962, 5,430,859 and 5,712,
`180, and application Ser. No. 08/910,947, filed Aug. 7, 1997,
`and 09/343,328, filed Jun. 30, 1999. Another type of non
`Volatile memory System utilizes a larger memory cell block
`Size that Stores multiple Sectors of user data.
`One architecture of the memory cell array conveniently
`forms a block from one or two rows of memory cells that are
`within a Sub-array or other unit of cells and which share a
`common erase gate. U.S. Pat. Nos. 5,677,872 and 5,712,179
`of SanDisk Corporation, which are incorporated herein in
`their entirety, give examples of this architecture. Although it
`is currently most common to Store one bit of data in each
`floating gate cell by defining only two programmed thresh
`old levels, the trend is to store more than one bit of data in
`each cell by establishing more than two floating-gate tran
`Sistor threshold ranges. A memory System that Stores two
`bits of data per floating gate (four threshold level ranges or
`States) is currently available, with three bits per cell (eight
`threshold level ranges or States) and four bits per cell
`(sixteen threshold level ranges) being contemplated for
`future Systems. Of course, the number of memory cells
`required to Store a Sector of data goes down as the number
`of bits Stored in each cell goes up. This trend, combined with
`a Scaling of the array resulting from improvements in cell
`Structure and general Semiconductor processing, makes it
`practical to form a memory cell block in a Segmented portion
`of a row of cells. The block structure can also be formed to
`enable Selection of operation of each of the memory cells in
`two states (one data bit per cell) or in Some multiple Such as
`four states (two data bits per cell), as described in SanDisk
`Corporation U.S. Pat. No. 5,930,167, which is incorporated
`herein in its entirety by this reference.
`Since the programming of data into floating-gate memory
`cells can take Significant amounts of time, a large number of
`memory cells in a row are typically programmed at the same
`time. But increases in this parallelism cause increased power
`requirements and potential disturbances of charges of adja
`cent cells or interaction between them. U.S. Pat. No. 5,890,
`192 of SanDisk Corporation, which is incorporated above,
`describes a System that minimizes these effects by Simulta
`neously programming multiple pages (referred to as chunks
`in that patent) of data into different blocks of cells located in
`different operational memory cell units (Sub-arrays).
`Memory Systems capable of programming multiple pages in
`parallel into multiple Sub-array units are described in
`co-pending patent applications Ser. No. 09/505,555, filed
`Feb. 17, 2000 by Kevin Conley et al., which is incorporated
`by reference above, and Ser. No. 09/759,835, filed Jan. 10,
`2001, by John Mangan et al., which application is expressly
`incorporated herein by this reference.
`
`Micron Ex. 1042, p. 9
`Micron v. Vervain
`IPR2021-01549
`
`

`

`S
`More detail on a specific embodiment of FIG. 2 is shown
`in FIG. 3. This particular embodiment divides the memory
`array 400 into a number of “planes', where a plane is a
`Subdivision of the memory on a Single die. Only the more
`relevant portions of FIG. 3 will be described here. More
`detail can be found U.S. patent application Ser. No. 09/759,
`835 that was incorporated by reference in the previous
`paragraph.
`The non-volatile memory chip 17 includes a logic circuit
`39 for interfacing with the controller through the lines 302.
`Additional components of the memory chip are not shown
`for Simplicity in explanation. The purpose of the logic circuit
`39 is to generate Signals in Separate buses and control lines.
`Various control Signals are provided in lines 41 and a power
`Supply 43 to the memory array circuits is also controlled
`through the interface 39. A data bus 45 carries user data
`being programmed into or read from the non-volatile
`memory, and an address buS 47 carries the addresses of the
`portion of the memory being accessed for reading user data,
`Writing user data, or erasing blocks of memory cells.
`The floating gate memory cell array of a single non
`volatile memory chip is itself divided into a number of units
`that each have its own Set of Supporting circuits for
`addressing, decoding, reading and the like. In this example,
`eight Such array units 0–7, denoted by reference numbers
`51-58, are illustrated. Physically, as an example, the
`memory array on a Single chip is divided into quadrants, or
`“planes', each quadrant including two units that are in part
`connected together and share a common word line decoding
`circuits (y-decode), Such as the y-decoders 61 and 62 on
`either side of memory cell units 4 (55) and 5 (56). The
`common word lines run across both memory cell units 4 (55)
`and 5 (56), with half connected to the y-decoder 61 on one
`Side and half connected to y-decoder 62 on the other Side, as
`described further below, with respect to FIG. 3. This
`memory architecture is similar to that described in U.S. Pat.
`No. 5,890,192 incorporated by reference above, except there
`are eight units, or "planes', instead of the four units (quads)
`illustrated in that patent.
`A number of architectures are used for non-volatile
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`memories arrays, such as 400 (FIG. 1) or 51–58 (FIG. 3). A
`NOR array of one design has its memory cells connected
`between adjacent bit (column) lines and control gates con
`nected to word (row) lines. The individual cells contain
`either one floating gate transistor, with or without a Select
`transistor formed in Series with it, or two floating gate
`transistorS Separated by a single Select transistor. Examples,
`of Such arrays and their use in Storage Systems are given in
`the following U.S. patents and pending applications of
`SanDisk Corporation that are incorporated herein in their
`entirety by this reference or which have been previously
`incorporated above: U.S. Pat. Nos. 5,095,344, 5,172,338,
`5,602,987, 5,663,901, 5,430,859, 5,657,332, 5,712,180,
`5,890,192, and 6,151,248, and Ser. Nos. 09/505,555, filed
`Feb. 17, 2000, and 09/667,344, filed Sep. 22, 2000.
`A NAND array of one design has a number of memory
`cells, Such as 8, 16 or even 32, connected in Series String
`between a bit line and a reference potential through Select
`transistors at either end. Word lines are connected with
`control gates of cells in different Series Strings. Relevant
`examples of Such arrayS and their operation are given in the
`following U.S. patent application Ser. No. 09/893,277, filed
`Jun. 27, 2001, that is also hereby incorporated by reference,
`and references contained therein.
`A memory will often have defective portions, either from
`the manufacturing process or that arise during the operation
`of the device. A number of techniques exist for managing
`
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`these defects, Such as with error correction code or by
`remapping portions of the memory, Such as described in U.S.
`Pat. No. 5,602,987, that was incorporated by reference
`above, or U.S. Pat. Nos. 5,315,541, 5,200,959, and 5,428,
`621, that are hereby incorporated by reference. For instance,
`a device is generally thoroughly tested before being Shipped.
`The testing may find a defective portion of the memory that
`needs to be eliminated. Before shipping the device, the
`information on these defects can be Stored on the device, for
`example in a ROM area of the memory array or Separate
`ROM, and at power up it is read by controller and then used
`So that the controller can Substitute a good portion of the
`memory for the bad. When reading or writing, the controller
`will then need to refer to a pointer structure in controller for
`this re-mapping.
`Memories are often designed with a number of redundant
`blocks to replace defective blockS. These are generally
`distributed between the logical Structure areas of the
`memory. However, if the number of bad blocks is too large,
`or too unevenly distributed, this results in yield loses or
`downgrades the capacity of the card.
`
`SUMMARY OF THE INVENTION
`According to one principal aspect of the present
`invention, briefly and generally, a non-volatile memory,
`Such as a flash memory, is divided into logical Zones by the
`card controller in order reduce the Size of the data Structures
`it uses for address translation. The present invention presents
`methods to adjust the Zone boundaries to accommodate
`defects allowed by memory test to improve card yields and
`to adjust boundaries in the field to extend the usable lifetime
`of the card. At the time of card production, an operation is
`performed that Sets Zone boundaries. During this process,
`the firmware Scans for the presence of defective blocks on
`the card. Once the locations of all the blocks are known, the
`firmware calculates the Zone boundaries in Such a way that
`good blocks are equally distributed among the Zones. Since
`the number of good blocks meets the card test criteria by the
`memory test criteria, defects will reduce card yield fallout.
`In another aspect of the present invention, the controller
`can perform dynamic boundary adjustments. When defects
`occur, the controller performs the analysis again and, if the
`number of good blockS becomes unbalanced, redistributes
`the Zone boundaries, moving any user data. The process can
`be reformed based on a timing mechanism, Such as the
`number of program or erase cycles, in response to an error
`correction code (ECC) result, or an indication of program
`ming or erase difficulties, Such as verification failure.
`Additional aspects, features and advantages of the present
`invention are included in the following description of exem
`plary embodiments, which description should be read in
`conjunction with the accompanying drawings.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`FIG. 1 is a block diagram of a typical prior art flash
`EEPROM memory array with memory control logic, data
`and address registers.
`FIG. 2 illustrates an architecture utilizing memories of
`FIG. 1 with a system controller.
`FIG 3
`illustrates Some elements of a non-volatile
`memory.
`FIG. 4 illustrates an arrangement of bad blockS in a single
`plane embodiment.
`FIG. 5 shows an example of boundary adjustment in a
`four plane, ten Zone embodiment.
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`FIG. 6 is a schematic illustration of how boundaries can
`be realigned.
`FIG. 7 is a flow chart illustrating an exemplary embodi
`ment.
`
`DESCRIPTION OF EXEMPLARY
`EMBODIMENTS OF THE INVENTION
`The various aspects of the present invention are appli
`cable to non-volatile memory Systems in general. Although
`the description below, as well as that in the Background, is
`given mainly in terms of an EEPROM Flash memory
`embodiment, the particular type of Storage unit used in the
`memory array is not particularly important in the present
`invention. The particulars of how the Storage elements are
`read, are written, and Store data do not enter in to the main
`aspects of the present invention and can be those of any of
`the various non-volatile Systems.
`In the following, as in the Background Section, the
`following terminology is used: a block contains the Smallest
`number of cells (unit of erase) that are erasable at one time,
`a Sector used herein to refer to an amount of user data that
`is transferred to and from the host as a unit, a page is the
`basic unit for reading and programming user data, and a
`plane is physical Subdivision of the memory on a single die.
`Although in Some embodiments, Some of these structures
`correspond, either directly or through a logical to physical
`correspondence, to one another, they are conceptually dis
`tinct. Additionally, in the more general case, a read page and
`a write page may be distinct. In the present discussion, the
`additional term a “Zone” is used for a logical Subdivision of
`the total capacity of the die. In a main aspect of the current
`invention, logically an address is distributed over the planes
`but the physical boundaries of a Zone within a plane are
`independent and are optimized for the location of defects.
`In the exemplary embodiment of the present invention, a
`flash or other memory device, such as 17 in FIG. 3, is
`divided into logical Zones by the card controller 301 in order
`reduce the size of the data Structures it uses for address
`translation. Within a Zone, a certain number of physical
`blocks are often included beyond the logical capacity of the
`Zone in order to provide an erase pool used for write
`operations. Since the logical Zones and their defect toler
`ances may not align to the number of defects in each Zone
`found during memory testing, it is possible to Suffer yield
`loSS due to having excessive defects in a Zone. In addition,
`defects can occur during operation of the card that can cause
`a Zone to be unusable thus limiting the lifetime of the card.
`A principle aspect of the present invention is to adjust the
`Zone boundaries to accommodate defects allowed by
`memory test to improve card yields and to adjust boundaries
`in the field to extend the usable lifetime of the card.
`The situation is illustrated schematically in FIG. 4 for a
`memory array 400 having a single plan that is logically
`divided into Six Zones, indicated by broken lines, plus a
`number of system blocks devoted to overhead and other
`non-user data. A number of bad blocks, 511-523, are illus
`trated by a blackened strip. For example, bad block 511 in
`ZONE0 and badblock 513 in ZONE3 can be a pair of blocks
`that were acceptable when the device was initially tested, but
`which failed as the device was used; while bad blocks 515,
`517,519, and 521 in ZONE4 and bad block 523 in ZONE5
`can be blocks that were bad at initial testing due to, Say,
`processing errors during manufacture. If each Zone is allot
`ted three spare blocks, ZONE4 will not have enough good
`blocks to correspond to its logical assignments.
`One approach to this problem is to provide more spare
`blocks, but this is a trade off between wasted Space (and
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`consequently cost) versus reliability. Although it is standard
`practice to include a number of Spare or redundant blockS in
`an array, there is usually a limit beyond where this becomes
`counterproductive. Furthermore, when an array is logically
`divided into Sub-units, Such as the Zone structure described
`here, the Spare blocks are typically distributed uniformly
`across the sub-units.