(12) United States Patent
`B0eve
`
`(10) Patent No.:
`(45) Date of Patent:
`
`US 7,733,729 B2
`Jun. 8, 2010
`
`USOO7733729B2
`
`(54) THERMALLY STABLE REFERENCE
`VOLTAGE GENERATOR FOR MIRAM
`
`(75) Inventor: Hans Marc Bert Boeve, Eindhoven
`NL
`(NL)
`(73) Assignee: NXP B.V., Eindhoven (NL)
`
`(*) Notice:
`
`(21) Appl. No.:
`
`Subject to any disclaimer, the term of this
`atent is extended or adiusted under 35
`p
`U.S.C. 154(b) by 662 days.
`111547,336
`
`(22) PCT Filed:
`(86). PCT No.:
`
`Mar. 29, 2005
`PCT/B2005/051051
`
`S371 (c)(1),
`(2), (4) Date:
`
`Oct. 2, 2006
`
`(87) PCT Pub. No.: WO2005/096315
`
`(65)
`
`PCT Pub. Date: Oct. 13, 2005
`O
`O
`Prior Publication Data
`US 2008/0279.027 A1
`Nov. 13, 2008
`• - s
`Foreign Application Priority Data
`(30)
`Apr. 1, 2004
`(EP) .................................. O41O1352
`
`(51) Int. Cl.
`(2006.01)
`GITC 702
`(2006.01)
`GIC II/34
`(2006.01)
`GIC I6/04
`(2006.01)
`GIC II/4
`(52) U.S. Cl. ................. 365/210.1; 385/209; 3.85/185.2:
`38.5/171
`
`(56)
`
`(58) Field of Classification Search ................. 365/171,
`365/185.2, 210.1
`See application file for complete search history.
`References Cited
`U.S. PATENT DOCUMENTS
`4,524,431 A
`6, 1985 Haken et al.
`5,022,031 A
`6/1991 Baggen
`5,719,808 A
`2f1998 Hararietal.
`5.999.439 A * 12/1999 Seyyedy ..................... 365,145
`6,445,612 B1
`9/2002 Naji
`6,600,690 B1
`7/2003 Nahas et al.
`(Continued)
`FOREIGN PATENT DOCUMENTS
`2004/049.343 A1
`6, 2004
`OTHER PUBLICATIONS
`"Magnetoresistive Random Access Memory Using Magnetic Tunnel
`Junctions” by Tehrani, et al. IEEE, vol. 91, No. 5, May 2003, pp.
`TO3-714.
`Primary Examiner Ly D Pham
`
`WO
`
`ABSTRACT
`(57)
`A non Volatile memory device comprises memory cells Such
`as MRAM cells, reading circuits and a reference cell for
`generating a reference for use by the reading circuits, and can
`determine if the reference is degraded by thermal instability.
`This can help reduce a data error rate. Detecting Such degra
`dation can prove to be more effective than trying to design in
`enough margins for the lifetime of the device. The reference
`cell can be less susceptible to degradation than other cells by
`using different shape of cells and different write currents.
`Where each reference cell is used by many memory cells, the
`reference cell tends to be used more often than any particular
`memory cell and so can be more Susceptible to degradation.
`Another way of ensuring against longer term degradation of
`the reference is periodically rewriting the reference cell.
`
`5 Claims, 5 Drawing Sheets
`
`TRIGGER
`
`170
`
`REF REWRITE
`CIRCUITRY
`
`
`
`PERIODICREWRITE TRIGGER
`
`REWRE TRIGGER
`
`REF TEST
`CELL
`READ
`CIRCUIT
`
`REFTEST
`CEL
`ERROR
`DETEC
`
`
`
`
`
`
`
`
`
`REF
`ES
`CELLS
`(MORE
`SUSCESPTBE
`TO DEGRADE)
`
`
`
`REF
`SIGNA
`
`READ DATA
`ERRORS
`
`DETECTOR OF ABNORMA
`LEVEL OF DATAERRORS
`
`Micron Ex. 1024, p. 1
`Micron v. Vervain
`IPR2021-01549
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`

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`US 7,733,729 B2
`Page 2
`
`U.S. PATENT DOCUMENTS
`
`9, 2003
`6,621,729 B1
`3, 2004
`6,704,230 B1
`7,038,950 B1* 5/2006
`2002fOOO8987 A1
`1, 2002
`2002fO1593O8 A1
`10, 2002
`2003, OO86314 A1
`5/2003
`
`Garni et al.
`DeBrosse et al.
`Hamilton et al. .......
`Numata et al.
`Fournel et al.
`Okazawa et al.
`
`365, 18528
`
`2004.0017718 A1*
`2004/O233716 A1*
`2006/00926.99 A1*
`2006/0114738 A1*
`2006/0274576 A1*
`2007/0113150 A1*
`* cited by examiner
`
`1, 2004
`11, 2004
`5/2006
`6, 2006
`12, 2006
`5/2007
`
`Ooishi ........................ 365,210
`Tran et al. .
`365,185.09
`Higashi et al. .............. 365,177
`Lee et al. ............... 365,230.03
`Redaelli et al. .
`365, 1852
`Resnicket al. .............. T14f763
`
`
`
`Micron Ex. 1024, p. 2
`Micron v. Vervain
`IPR2021-01549
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`U.S. Patent
`
`Jun. 8, 2010
`
`Sheet 1 of 5
`
`US 7,733,729 B2
`
`
`
`r
`
`HE
`
`L
`
`L
`
`FIG. 1 PRIOR ART
`
`Micron Ex. 1024, p. 3
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`IPR2021-01549
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`

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`U.S. Patent
`
`Jun. 8, 2010
`
`Sheet 2 of 5
`
`US 7,733,729 B2
`
`O
`
`NVM
`
`
`
`20
`
`MEM
`
`REF DEGRADE
`DETECTOR
`
`50
`
`20
`
`REF
`CELL
`
`a- - -
`
`30
`
`RAW
`DATA
`
`REF SIGNAL
`
`RAW
`DATA
`
`
`
`READ CIRCUITRY
`
`DATA
`VALUES
`
`DATA ERRORDETECTION
`AND CORRECTION
`
`40
`
`60
`
`
`
`
`
`
`
`
`
`PROCESSOR AND OTHER
`PARTS OF SYSTEM
`
`70
`
`FIG. 2
`
`POWER
`SOURCE
`
`80
`
`Micron Ex. 1024, p. 4
`Micron v. Vervain
`IPR2021-01549
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`U.S. Patent
`
`Jun. 8, 2010
`
`Sheet 3 of 5
`
`US 7,733,729 B2
`
`170
`
`REF REWRITE
`CIRCUITRY
`
`TRIGGER
`
`PERIODIC REWRITE TRIGGER
`
`130
`
`140
`
`150
`
`REWRE TRIGGER
`
`REF
`CELLS
`
`REF
`TEST
`CELLS
`(MORE
`SUSCESPTIBLE
`TO DEGRADE)
`
`REF TEST
`CELL
`READ
`CIRCUIT
`
`REF TEST
`CELL
`ERROR
`DETECT
`
`160
`
`18O
`
`REF
`SIGNAL
`
`READ DATA
`ERRORS
`
`DETECTOR OF ABNORMAL
`LEVEL OF DATA ERRORS
`
`
`
`FIG. 3
`
`Micron Ex. 1024, p. 5
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`U.S. Patent
`
`Jun. 8, 2010
`
`Sheet 4 of 5
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`US 7,733,729 B2
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`Midpoint reference integrity test
`
`N
`
`Y
`
`Re-write midpoint reference
`
`Data integrity test
`
`N
`
`Y
`
`Data read-Out
`
`Error COrrection
`Partial re-Write of data
`
`FIG. 4
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`Micron Ex. 1024, p. 6
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`U.S. Patent
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`Jun. 8, 2010
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`Sheet 5 of 5
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`US 7,733,729 B2
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`210
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`210
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`220
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`Micron Ex. 1024, p. 7
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`

`

`1.
`THERMALLY STABLE REFERENCE
`VOLTAGE GENERATOR FOR MIRAM
`
`US 7,733,729 B2
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`5
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`parison to the target cells along the same row to determine the
`resistance state of a given target cell. In this case, the refer
`ence column 41 has reference cells each consisting of a series
`parallel combination of four devices, where two elements are
`programmed high and two are programmed low. From here,
`the read circuitry determines whether the target cell is above
`or below the midpoint to determine the memory state.
`In FIG. 1, the reference column 41 is embedded in a plu
`rality of data columns, each designated 40, forming a single
`data block. Each data column 40 includes a bitline 42 having
`pairs of non-volatile magnetoresistive memory elements 44
`and 45, and 46 and 47 connected thereto by means of control
`or activating transistors 48 through 51, respectively. Elements
`44 through 47 are MTJ memory cells represented as resis
`tances. Each element 44 through 47 is programmable to one
`ofan Rimax and an Rimin State, in a manner well known in the
`art, to operate as a memory. Bitline 42 is connected through a
`column select transistor (or switch) 52 to one input of a
`read-out circuit, which includes a current conveyor circuit 55,
`which feeds a differential amplifier.
`Current conveyor circuit 55 includes individual compo
`nents that have a very low input impedance, isolating bitlines
`42 from any high output impedance of current sources. The
`low input impedance combined with the clamping of bitlines
`42 to V,
`limits the Voltage Swing of bitlines 42 to achieve
`high speed readout for very high density MTJ arrays. Current
`conveyor circuit 55 provides and maintains a constant bias
`across bitlines 42 regardless of operating temperatures,
`changes in the Supply Voltage, and process conditions. Also,
`current conveyor circuit 55 provides a small swing in the
`voltage on bitlines 42 to allow for high speed operation. The
`term “current conveyor is intended to include any other
`device that performs the described functions. e.g., current
`sensors, current sense amplifiers, pre-amplifiers, etc.
`Reference column 41 includes two midpoint generator
`cells 58 and 59 coupled to a reference bitline 60. Reference
`bitline 60 is connected through a column select transistor (or
`switch) 62 to a second input of current conveyor circuit 55.
`Midpoint generator cell 58 includes a plurality of non-volatile
`magnetoresistive elements 64 through 67 each having an
`Rimax State and an Rimin state and each being set to one of
`Rimax and Rimin. Magnetoresistive elements 64 and 66 are set
`to Rimax and magnetoresistive elements 65 and 67 are set to
`Rimin. Further, magnetoresistive elements 64 and 65 are con
`nected in a first series circuit between the input terminal
`(bitline 60) and the output terminal (line 63) of cell 58 and
`magnetoresistive elements 66 and 67 are connected in a sec
`ond series circuit between the input terminal (bitline 60) and
`the output terminal (line 63) of cell 58. Magnetoresistive
`elements 64 through 67 are connected together to provide a
`total resistance of a midpoint resistance between Rimax and
`Rimin. Similarly, midpoint generator cell 59 includes a plu
`rality (in this embodiment four) of non-volatile magnetore
`sistive elements connected together to provide a total resis
`tance of a midpoint resistance between Rimax and Rimin. Two
`control transistors 68 and 69 are connected to direct current
`flow through cell 58.
`Having the reference cells in close proximity and identical
`to the array devices solves several potential problems. The
`close proximity ensures that the reference will track any
`variations in the resistance over the wafer, Such as those due
`to Small changes in the tunnel barrier thickness or patterned
`magnetic element area. Since the reference elements are iden
`tical to the memory elements, variations in resistance due to
`
`This invention relates to non-volatile memory devices,
`MRAMs, to systems containing such memory devices, and
`methods of operating Such devices.
`Thin film Magnetoresistive Random Access Memory
`(MRAM) is one example of a number of NVM (non volatile
`memory) technologies. MRAMs can be fabricated in a vari
`ety of memory cell embodiments, including a Magnetic Tun
`neling Junction (MTJ) element. The MTJ element essentially
`consists of a pair of magnetic layers with an insulating layer
`sandwiched in between. One of the magnetic layers has a
`fixed magnetic vector and the other magnetic layer has a
`changeable magnetic vector that is either aligned with or
`opposed to the fixed magnetic vector. When the magnetic
`vectors are aligned, the resistance of the MTJ element, i.e. the
`resistance to current flow between the magnetic layers, is a
`minimum and when the magnetic vectors are opposed or
`misaligned the resistance of the MTJ element is a maximum.
`Data is stored in the MTJ element by applying a magnetic
`field to the MTJ element directed so as to move the change
`able magnetic vector to a selected orientation. Generally, the
`aligned orientation can be designated a logic 1 or 0 and the
`misaligned orientation is the opposite, i.e., a logic 0 or 1.
`Stored data is read or sensed by passing a current through the
`MTJ element from one magnetic layer to the other. The
`amount of current passing through the MTJ element, or the
`Voltage drop across the MTJ element, will vary according to
`the orientation of the changeable magnetic vector.
`The scaling of MRAM and other NVM technology is an
`important aspect for its future success as a unified memory
`technology, combining speed, density, and non-volatility.
`Two key problems relate to the Scaling issue:
`1. current densities in the current lines used for writing are
`limited, hence a maximum write current level should not be
`exceeded for a given CMOS technology, and
`2. a thermal stability problem occurs when the stored data in
`magnetic memory cells become unstable over time due to
`thermal relaxation.
`The magnetic anisotropy-magnetic Volume product K.V.
`is the important figure-of-merit in the thermal stability analy
`sis. However, when scaling MRAM technology, for a fixed
`free layer thickness, the magnetic Volume scales along with
`the device area, i.e. by a power(-2) or 1/S, with S the scaling
`factor of the semiconductor technology, and the anisotropy
`needs to be constant or Smaller to keep the required write
`fields within the available current density. The latter con
`straint has been met So far by reducing the aspect ratio of the
`memory elements. For the memory cells, different measures
`can be taken to overcome or at least cope with weaker cells
`Such as error correction schemes, in combination with redun
`dancy, or rewriting data tracks at regular time intervals, or a
`combination of these.
`During a read operation, the data signal of a memory cell is
`compared to a signal provided by a reference Voltage genera
`tor. When read out, the reference voltage generator yields a
`Voltage half-way between the output Voltages corresponding
`to the logical 0 and 1. An example of an MRAM device with
`a midpoint generator reference is shown in U.S. Pat. No.
`6,445,612 by P. Naji (Motorola) and in, “Magnetoresistive
`Random Access Memory. Using Magnetic Tunnel Junctions.”
`Proceedings of the IEEE, Vol. 91, No. 5, May 2003, pp.
`703-14 by Tebrani etal, and is illustrated here in FIG. 1. FIG.
`1 schematically represents a 1T1 MTJ circuit comprising a
`reference column 41 and nearby memory array blocks. The
`reference column 41 is used by the read circuitry for com
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`US 7,733,729 B2
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`15
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`3
`operating temperature or other external factors will closely
`track the active elements. The resulting resistance is
`(R,+Rain) (Raat Rain)2(R,natrain),
`
`4
`each of a data cell, a reference cell programmed to a high state
`and a reference cell programmed to a low state. Currents are
`developed from the bias Voltages and Summed to create the
`midpoint reference current. A current differential amplifier
`senses whether the bit input has a high or low resistive state
`which is the midpoint between R and R.
`and outputs a Voltage indicative of the sensed memory state.
`The read operation for the MRAM circuit of FIG. 1 is as
`U.S. Pat. No. 6,600,690 shows an MRAM in which a
`follows. A memory cell is selected by driving the word line
`sensing system detects bit states using one data and two
`Voltage high, selecting a column (bitline), and turning on all
`reference inputs, to sense a difference in conductance of a
`ground Switches. A current conveyor is shared by a block of 1
`O Selected memory cell and a midpoint reference conductance.
`bitlines and every reference bitline has its own current con
`Reference conductance is generated as the average conduc
`veyor. Once the current conveyors are turned on, they clamp
`tance of a memory cell in the high conductance state and a
`the target bitlines and reference bitlines to the respective
`memory cell in the low conductance state. The data input is
`Voltages, take the resulting target and reference bitline cur
`coupled to the selected memory cell. The two reference inputs
`rents, and convert them to a Voltage signal with Substantial
`are respectively coupled to memory cells in high and low
`boost. The target and reference current conveyors form a
`conductance memory states. The sense amplifiers use either
`differential pair and their outputs are fed into a differential
`current biasing or Voltage biasing to apply a sensing Voltage
`comparator followed by a regenerator, which again boosts the
`within a predetermined Voltage range across the memory
`signal. The read circuitry has been designed to achieve high
`cells. Capacitance coupled to complementary outputs of the
`bandwidth, maintain offset insensitivity, and consume mini
`sense amplifiers is balanced by the circuit designs. In one
`mal silicon area.
`form, the two reference inputs are internally connected. One
`U.S. Pat. No. 6,445,612 also shows a differential read-out
`of several gain stages amplifies the sense amplifier output
`circuit is coupled to the data column and to the reference
`without injecting parasitic errors.
`column for differentially comparing a data Voltage to a refer
`However, there still remains a need for improved error rates
`ence Voltage. The magnetoresistive elements of the plurality
`particularly for memory technologies with long term stability
`of data columns and the magnetoresistive elements of the
`issues.
`plurality of reference columns are generally similar. The ref
`It is an object of the present invention to provide improved
`erence column including midpoint generators is capacitively
`devices and methods.
`very close to the adjacent data columns. As a result, all time
`The above objective is accomplished by methods and
`varying signals in the data and reference columns track very
`devices according to the present invention.
`closely, resulting in high speed read processing. Because of
`According to a first aspect, the invention provides a non
`the improved reference columns with midpoint generators,
`volatile memory device comprising a number of memory
`circuit operation is faster and more reliable. Because of the
`cells, which may comprise at least one memory element, for
`improved reference columns with midpoint generators, read
`providing data signals representative of stored data values, at
`access is fast and the architecture is robust and reliable to
`least one dedicated reference cell, which may comprise at
`match that of SRAM performance.
`least one reference element, for generating a reference signal
`In U.S. Pat. No. 6,445,612 a change of state of one of the
`and a reading means or circuitry for determining data values
`four elements involved in the reference design will lead to a
`from the signals read from the memory cells and from the at
`shift away from the reference level from ~50% (compared to
`least one reference cell, the device further comprising a ref
`a logic 1, e.g. low state (0%) and logic 0 high state (100%)),
`erence degrade detector means for determining if the refer
`to result in new reference states close to 25% or 75%. This
`ence signal is degraded. Degradation can be determined by
`bit-flip can be induced by thermal instability, e.g. during
`reference to a timer, i.e. a certain elapsed time, or by com
`normal operations or, alternatively, induced by a brief expo
`parison with a further reference signal, or if there is more than
`Sure to a very moderate magnetic field. For a permanent,
`one reference cell, then the reference signals from all the
`non-volatile change in the reference level, a dramatic
`reference cells can be compared and degraded cells deter
`decrease in the readout margin is anticipated, probably
`mined as differing by a threshold value from other reference
`beyond available margins in advanced non-volatile semicon
`cells or the average of the reference signals. Another detection
`ductor technologies.
`of degradation may be based on e.g. the data. When an exces
`It is known from US patent application 2003/0086314A1
`sive amount of errors is detected in the data that may be
`to reduce the effect of variation of electrical performance at
`encoded, it may be concluded that the reference signal may be
`different places on an MRAM or an FRAM (Ferroelectric
`degraded. Hence, degradation may be detected by determin
`random access memory) device by using an electrical state of
`ing abnormal levels of data errors by means of for example a
`a memory cell as a reference where that memory cell is nearer
`data error detection and correction system of a non-volatile
`memory device.
`than the reference cell.
`Data values are determined by the comparison of the raw
`Furthermore, it is known from U.S. Pat. No. 6,621,729 that
`there is a need for a sensing circuit for MRAM using a
`data with the reference signal.
`midpoint reference using a minimum of area, providing a true
`In an aspect of the present invention the means for deter
`nearby midpoint reference, with symmetry in the circuit path
`mining if the reference is degraded may comprise a reference
`for balanced loading including parasitic capacitances and
`test structure. This can provide a more direct determination,
`resistances. The document Suggests a sense amplifier which
`and can be used in combination with other techniques.
`develops internally a midpoint reference current from two
`In an embodiment of the present invention, the reference
`may comprise a midpoint reference. This is appropriate for
`reference elements. The midpoint reference current is used to
`binary logic and so is commercially the most significant type
`sense the state of a memory cell having at least two distinct
`of reference, since most systems currently use binary logic.
`resistance States (Hand L) by determining whether the sense
`memory cell develops a larger or Smaller current. The mid
`In one embodiment, the reference test structure may com
`prise a test cell which is more susceptible to degradation than
`point reference current is developed within a single sense
`amplifier. Predetermined bias voltages are developed from
`the reference celland a means for indicating that the reference
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`signal is degraded based on detecting a degradation in the test
`cell. This may enable the degradation to be detected more
`readily, and in some cases before it has an effect on read data
`errors. Hence, it may enable remedial action to be taken
`before data errors occur. Optionally, this may enable other
`design parameters or margins to be relaxed, with less risk of
`data errors over the lifetime of the device. As before, this may
`be combined with other techniques.
`Since reliable memory operation depends on correctness of
`the reference, the bit error rate can be kept low if any degra
`dation including potential stability problems of the reference
`is detected. There are a number of ways of reacting once a
`problem is detected; and some are described below. Detecting
`Such degradation may prove to be more effective than trying
`to anticipate every degradation and design in enough margin
`for the entire lifetime of the device.
`The device according to the present invention may further
`more comprise a reference rewrite means or circuit for rewrit
`ing the reference cell if it is determined to be degraded.
`Hence, the device may comprise means for regenerating the
`reference before reading the data values from the memory
`cells if the reference is found to be degraded. This is particu
`larly useful for addressing degradation such as long term
`instability of the reference cell. For some NVM technologies
`at least this may lead to better scalability and contribute
`towards the ideal of a unified memory technology, combining
`speed, density, and non-volatility. It may help address degra
`dations such as thermal instability within limitations of cur
`rent densities in current lines used for writing.
`In another embodiment, the device may furthermore com
`30
`prise a data error detection and correction means for detecting
`and correcting errors in the read data values. The device
`according to this embodiment may help to further reduce
`errors and in particular embodiments the amount of read data
`errors detected may be used to detect degradation in the
`reference. Moreover, if regenerating the reference does not
`change the amount of read data errors, it may be deduced that
`the reference is not the source of the errors.
`In another embodiment, the reference degrade detector
`means for determining if the reference is degraded may com
`40
`prise a detector means for detecting errors in the read data
`values. This is a less direct technique since there may be other
`causes of data errors. Nevertheless, this may be useful since
`data errors are one of the most important parameters and
`relatively easy to measure.
`In yet another embodiment, the reference cell may be
`arranged to be less Susceptible to the degradation than the
`memory cells. This may further reduce the risk of data errors.
`It may however involve a cost in terms of chip area or other
`parameters, but nevertheless may be worthwhile especially
`where each reference cell is used by more than one memory
`cell.
`A second aspect of the invention provides a non Volatile
`memory device comprising a number of memory cells for
`providing data signals representative for stored data value, at
`least one reference cell for generating a reference signal and
`reading means or circuitry for determining the data values
`from the signals read from the memory cells and from the at
`least one reference cell, the reference cell being arranged to
`be less Susceptible to degradation than are the memory cells.
`This may however also involve a cost in terms of chip area
`or other parameters, but may nevertheless be worthwhile,
`especially where each reference cell is used by many memory
`cells. In such cases the reference cell may tend to be used
`more often than any particular memory cell and so may be
`more Susceptible to degradation. It may be used as an alter
`native to providing a reference degrade detector means for
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`determining when the reference is degraded, to save chip area
`or other resources, or may be used in combination with Such
`techniques to further improve data error rates.
`A memory cell and a reference cell may comprise at least
`one memory element resp. reference element. Theat least one
`reference element in the reference cell may have a larger size
`than the at least one memory element in the memory cell. This
`is one way to achieve less Susceptibility to degradation.
`Another way to achieve less Susceptibility to degradation may
`be a different shape and a different shape anisotropy for the at
`least one reference element in the reference cell compared
`with the at least one memory element in the memory cell. This
`can be another way to achieve less Susceptibility to degrada
`tion. Hence, to decrease Susceptibility to degradation it is
`preferable to increase the product K.V. By increasing the size
`of a reference element, V is increased. A larger V is hence
`achieved for the same value of K, and thus the product K.V
`is increased as well. On the other hand, when changing the
`shape and shape anisotropy of a reference element, a larger
`value for K may be achieved for the same volume V. In that
`way, the product KV may be increased as well.
`Less Susceptibility to degradation may also be achieved
`when the write current used for generating a local magnetic
`field required for performing a programming operation on the
`reference cell is made larger than the corresponding write
`current for performing a programming operation on the
`memory cells.
`In a further embodiment of the invention, a write current
`may be used for generating a local magnetic field required for
`performing a programming operation on the reference cell.
`The magnetic field may comprise a component which is
`shared with the memory cells and a component which is not
`shared with the memory cells, the shared component being
`Smaller than the non-shared component. This is a way to
`achieve less susceptibility to degradation for the reference
`cells with less impact on the memory cells and their design
`and operating parameters. Another Such additional feature is
`the degradation comprising thermal instability. This is one
`long term source of data errors which tends to become more
`significant as the size of the devices is scaled down. Hence, it
`is important to address this to ensure scalability.
`A third aspect of the invention provides a non-volatile
`memory device comprising a number of memory cells for
`providing data signals representative for stored data values, at
`least one reference cell for generating a reference signal,
`reading means for determining the data values from the sig
`nals read from the memory cells and means for periodically
`rewriting the reference cell.
`This may be another way of ensuring against longer term
`degradation of the reference. It may be carried out as an
`alternative to the other techniques, or in combination with any
`of them.
`In a further embodiment of the invention, the device may
`comprise an MRAM. This is one of the commercially more
`significant NVM technologies.
`Another aspect of the invention provides a system having a
`power source, a processor and a number of memory devices
`according to any of the aspects set out above in accordance
`with the present invention. This reflects that the memory
`devices set out above may affect speed and power consump
`tion for example, so the benefits may be seen at the system
`level. The increased value of such systems and of applications
`running on Such systems may be far greater than the sales
`value of the memory devices.
`Another aspect of the present invention provides a method
`of operating a memory device having a number of memory
`cells for providing data signals representative for stored data
`
`Micron Ex. 1024, p. 10
`Micron v. Vervain
`IPR2021-01549
`
`

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`7
`values, and reading circuitry for reading the memory cells
`using a reference signal to determine data values of the
`memory cells, the method comprising the steps of determin
`ing if the reference signal is degraded, and if so, then regen
`erating the reference before reading the data values from the
`memory cells.
`In another embodiment, the method may furthermore com
`prise detecting errors in the read data values. In yet another
`embodiment, the method may furthermore comprise deter
`mining if the reference is degraded by using a built in test
`Structure.
`The additional features may be combined with each other
`and with any of the aspects as would be apparent to those
`skilled in the art. Other advantages to those set out above will
`be apparent, especially in relation to other prior art not known
`to the inventors. How the present invention may be put into
`effect will now be described with reference to the appended
`schematic drawings. Obviously, numerous variations and
`modifications can be made without departing from the spirit
`of the present invention. Therefore, it should be clearly under
`stood that the form of the present invention is illustrative only
`and is not intended to limit the scope of the present invention.
`These and other characteristics, features and advantages of
`the present invention will become apparent from the follow
`ing detailed description, taken in conjunction with the accom
`panying drawings, which illustrate, by way of example, the
`principles of the invention. This description is given for the
`sake of example only, without limiting the scope of the inven
`tion. The reference figures quoted below refer to the attached
`drawings.
`FIG. 1 shows a prior art MRAM device,
`FIG. 2 shows in schematic form some elements of a system
`including an NVM according to an embodiment of the inven
`tion,
`FIG. 3 shows some of the principal elements of another
`embodiment,
`FIG. 4 shows in schematic form some of the functions of
`another embodiment,
`FIG. 5 shows in schematic form an embodiment of an
`MRAM having reference elements which are larger than the
`memory elements, according to another embodiment, and
`FIG. 6 shows a graph of writing current components for the
`embodiment of FIG. 5.
`In the different figures, the same reference signs refer to the
`same or analogous elements.
`The present invention will be described with respect to
`particular embodiments and with reference to certain draw
`ings but the invention is not limited thereto but only by the
`claims. The drawings described are only schematic and are
`non-limiting. In the drawings, the size of Some of the ele
`ments may be exaggerated and not drawn on Scale for illus
`trative purposes. Where the term “comprising is used in the
`present description and claims, it does not exclude other
`elements or steps. Where an indefinite or definite article is
`used when referring to a singular noun e.g. “a” or “an”, “the'.
`this includes a plural of that noun unless something else is
`specifically stated. Hence, the term “comprising, used in the
`claims, should not be interpreted as being restricted to the
`means listed thereafter; it does not exclude other elements or
`steps. Thus, the scope of the expression "a device comprising
`means A and B should not be limited to devices consisting
`only of components A and B. It means that with respect to the
`present invention, the only relevant components of the device
`are A and B.
`Furthermore, the terms first, second, third and the like in
`the description and in the claims, are used for distinguishing
`between similar elements and not necessarily for describing a
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`sequential or chronological order. It is to be understood that
`the terms so used are interchangeable under appropriate cir
`cumstances and that the embodiments of the invention
`described herein are capable of operation in other sequences
`than described or illustrated herein.
`In the following description and in the claims, the term bit
`refers to data in the memory cell. The term 'cell refers to a
`memory cell or a reference cell. Furthermore, a memory cell