UNITED STATES PATENT AND TRADEMARK OFFICE
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`MICRON TECHNOLOGY, INC.,
`Petitioner,
`
`v.
`
`VERVAIN, LLC,
`Patent Owner.
`
`____________________________
`
`Case No.: IPR2021-01549
`U.S. Patent No. 9,997,240
`Original Issue Date: June 12, 2018
`
`Title: LIFETIME MIXED LEVEL NON-VOLATILE MEMORY SYSTEM
`_________________________________________________________________
`
`PETITIONER’S REPLY
`_________________________________________________________________
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`MICRON TECHNOLOGY, INC.,
`Petitioner,
`
`v.
`
`VERVAIN, LLC,
`Patent Owner.
`
`____________________________
`
`Case No.: IPR2021-01549
`U.S. Patent No. 9,997,240
`Original Issue Date: June 12, 2018
`
`Title: LIFETIME MIXED LEVEL NON-VOLATILE MEMORY SYSTEM
`_________________________________________________________________
`
`PETITIONER’S REPLY
`_________________________________________________________________
`
`
`
`TABLE OF CONTENTS
`
`I.
`II.
`
`Introduction ................................................................................................................ 1
`The Board Should Again Reject PO’s Attempt to Construe “Blocks”
`to Mean “Physical Blocks” ..................................................................................... 2
`The Dusija in View of Sutardja Ground Renders Obvious Limitations
`[1.F]-[1.G] .................................................................................................................. 7
`Dusija and Sutardja Teach Counting and Segregating Blocks
`Based On Write Frequency (Limitation [1.F]) ........................................ 7
`1.
`PO’s “Block” Argument Fails Because It Relies on an
`Incorrect Construction of “Block” ................................................... 9
`PO’s Apparent Single-Block Argument Strains Credibility ......... 13
`2.
`PO’s “Second NVS” Argument Ignores the Record ................... 15
`3.
`Dusija in View of Sutardja Renders Obvious Limitation [1.G] ......... 18
`1.
`Sutardja Renders Obvious Limitation [1.G] Under the
`Individual Count Interpretation ...................................................... 19
`Sutardja Renders Obvious Limitation [1.G] Under the
`Collective Count Interpretation ...................................................... 21
`IV. Dusija in View of Sutardja and Chin Renders Obvious Claims 1-2 and
`6-7 .............................................................................................................................. 23
`Conclusion ............................................................................................................... 24
`
`III.
`
`V.
`
`2.
`
`-i-
`
`
`
`TABLE OF AUTHORITIES
`
` Page(s)
`
`Cases
`Acceleration Bay, LLC v. Activision Blizzard Inc.,
`908 F.3d 765 (Fed. Cir. 2018) .............................................................................. 7
`Evolusion Concepts, Inc. v. HOC Events, Inc.,
`22 F.4th 1361 (Fed. Cir. 2022) ............................................................................. 3
`Microprocessor Enhancement Corp. v. Texas Instruments Inc.,
`520 F.3d 1367 (Fed. Cir. 2008) ............................................................................ 6
`Microsoft Corp. v. FG SRC, LLC,
`860 Fed. App’x. 708 ........................................................................................... 15
`Novo Nordisk A/S v. Eli Lilly & Co.,
`1999 WL 1094213 (D. Del. Nov. 18, 1999) ......................................................... 3
`
`-ii-
`
`
`
`LISTING OF EXHIBITS
`
`Exhibit
`
`Description
`
`1001
`
`U.S. Patent No. 8,891,298 (the “298 patent”)
`
`1002-1004
`
`Intentionally omitted
`
`1005
`
`1006
`
`U.S. Patent No. 9,997,240 (the “240 patent”)
`
`File History of U.S. Patent No. 9,997,240
`
`1007-1008
`
`Intentionally omitted
`
`1009
`
`1010
`
`1011
`
`1012
`
`1013
`
`1014
`
`1015
`
`1016
`
`1017
`
`1018
`
`1019
`
`Declaration of Dr. David Liu (“Liu Decl.”) – IPR2021-01549
`
`U.S. Patent Application Publication No. 2011/0099460
`(“Dusija”)
`
`U.S. Patent Application Publication No. 2008/0140918
`(“Sutardja”)
`
`U.S. Patent Application Publication No. 2009/0327591
`(“Moshayedi”)
`
`Intentionally omitted
`
`Betty Prince, Semiconductor Memories – A Handbook of
`Design, Manufacture, and Application (2d ed. 1991) (“Prince”)
`
`U.S. Patent No. 8,120,960 (“Varkony”)
`
`U.S. Patent No. 7,000,063 (“Friedman”)
`
`U.S. Patent Application Publication No. 2005/0251617
`(“Sinclair”)
`
`Jan Axelson, USB Mass Storage: Designing and Programming
`Devices and Embedded Hosts (2006) (“Axelson”)
`
`Rino Micheloni et al., Inside NAND Flash Memories (1st ed.
`2010) (“Micheloni”)
`
`-iii-
`
`
`
`Exhibit
`
`Description
`
`1020
`
`1021
`
`1022
`
`1023
`
`1024
`
`1025
`
`1026
`
`1027
`
`1028
`
`1029
`
`1030
`
`1031
`
`1032
`
`1033
`
`1034
`
`U.S. Patent Application Publication No. 2011/0115192
`(“Y. Lee”)
`
`U.S. Patent No. 7,453,712 (“Kim”)
`
`U.S. Patent Application Publication No. 2011/0096601
`(“Gavens”)
`
`U.S. Patent No. 8,078,794 (“C. Lee”)
`
`U.S. Patent No. 7,733,729 (“Boeve”)
`
`Microsoft Computer Dictionary, Fifth Edition, 2002, definition
`of read-after-write
`
`Merriam-Webster’s Collegiate Dictionary, Eleventh Edition,
`2006, definition of periodic
`
`New Oxford American Dictionary, 3rd Edition, 2010, definition
`of module
`
`U.S. Patent Application Publication No. 2010/0172180
`(“Paley”)
`
`U.S. Patent No. 7,853,749 (“Kolokowsky”)
`
`U.S. Patent Application Publication No. 2010/0017650
`(“Chin”)
`
`European Patent Specification No. EP 2,291,746 B1 (“Radke”)
`
`U.S. Patent Application Publication No. 2015/0214476
`(“Matsui”)
`
`Intentionally omitted
`
`Complaint for Patent Infringement, Dkt. No. 1, Vervain, LLC v.
`Micron Technology, Inc., Micron Semiconductor Products,
`Inc., and Micron Technology Texas, LLC, Case No. 6:21-cv-
`00487-ADA (May 10, 2021 W.D. Tex.)
`
`-iv-
`
`
`
`Exhibit
`
`Description
`
`1035
`
`Agreed Scheduling Order, Dkt. No. 24, dated September 16,
`2021, in Vervain, LLC v. Micron Technology, Inc., Micron
`Semiconductor Products, Inc., and Micron Technology Texas,
`LLC, Case No. 6:21-cv-00487-ADA
`
`1036-1037
`
`Intentionally omitted
`
`1038
`
`1039
`
`1040
`
`1041
`
`1042
`
`1043
`
`Scott McKeown, “WDTX ‘Implausible Schedule’ & Cursory
`Markman Order Highlighted,” Ropes & Gray, Patents Post-
`Grant, Inside Views & News Pertaining to the Nation’s Busiest
`Patent Court, June 2, 2021
`
`Dani Kass, Judge Albright Now Oversees 20% of New U.S.
`Patent Cases, Law360, March 10, 2021
`
`Brian Dipert and Markus Levy, Designing with Flash Memory
`(1994) (“Dipert & Levy”)
`
`U.S. Patent No. 7,366,826 (“Gorobets”)
`
`U.S. Patent No. 6,901,498 (“Conley”)
`
`U.S. Patent No. 8,356,152 (“You”)
`
`1044-1046
`
`Intentionally omitted
`
`1047
`
`1048
`
`1049
`
`Ashok Sharma, Advanced Semiconductor Memories,
`Architectures, Designs, and Applications (2003) (“Sharma”)
`
`Intentionally omitted
`
`U.S. Patent No. 5,936,971 (“Harari”)
`
`1050-1054
`
`Intentionally omitted
`
`1055
`
`1056
`
`New Oxford American Dictionary, 3rd Edition, 2010,
`definitions of frequency and threshold
`
`Declaration of Jared Bobrow In Support Of Petitioner’s Motion
`for Admission Pro Hac Vice
`
`-v-
`
`
`
`Exhibit
`
`Description
`
`1057
`
`1058
`
`1059
`
`1060
`
`1061
`
`1062
`
`1063
`
`1064
`
`1065
`
`1066
`
`1067
`
`Reply Declaration of Dr. David Liu (“Liu Reply”) – IPR2021-
`01549
`
`Curriculum vitae of Dr. David Liu
`
`Deposition Transcript of Sunil Khatri (September 1, 2022)
`[IPR2021-01547, -01548 and -01549]
`
`Intentionally omitted
`
`U.S. Patent No. 8,130,554 (“Linnell”)
`
`U.S. Patent No. 7,917,709 (“Gorobets III”)
`
`Intentionally omitted
`
`Byung-Woo Nam, Gap-Joo Na, and Sang-Won Lee, “A Hybrid
`Flash Memory SSD Scheme for Enterprise Database
`Applications”
`
`Yuan-Hao Chang, Jen-Wei Hsieh, Tei-Wei Kuo, “Improving
`Flash Wear-Leveling by Proactively Moving Static Data”
`
`Muthukumar Murugan, “Rejuvinator: A Static Wear Leveling
`Algorithm for NAND Flash Memory with Minimized
`Overhead”
`
`Vervain’s Sur-reply Claim Construction Brief, Dkt. 33, dated
`January 3, 2022 in Vervain, LLC v. Micron Technology, Inc.,
`Micron Semiconductor Products, Inc., and Micron Technology
`Texas, LLC, Case No. 6:21-cv-00487-ADA (W.D. Tex.)
`
`1068
`
`Intentionally omitted
`
`-vi-
`
`
`
`I.
`
`Introduction
`PO argues that only two limitations are not rendered obvious by the prior art:
`
`[1.F] and [1.G]. None of PO’s arguments raise a serious challenge to the Petition’s
`
`showings.
`
`As to limitation [1.F], PO’s first argument relies entirely on construing
`
`“block” to mean “physical block,” ignoring the context of the claims and the
`
`specification. What’s more, during deposition, PO’s expert admitted that its basis
`
`for this erroneous construction—that a logical block cannot be erased—is
`
`incorrect. Regardless, PO ignores that the prior art renders the limitation obvious
`
`under its erroneous construction as well. PO then makes the absurd argument that
`
`the Sutardja reference discloses only operating on a single block (e.g., only
`
`determining if a single block, out of all the memory’s blocks, is frequently
`
`written), even though Sutardja expressly discloses maintaining write and erase
`
`counts for all blocks and transferring each block when the count is above a
`
`threshold. Finally, PO goes so far as to argue that Sutardja’s first and second NVS
`
`memories in its “hybrid” flash memory system may not be MLC and SLC,
`
`respectively. But PO does not deny that the characteristics of Sutardja’s first and
`
`second NVS memories are hallmarks of MLC and SLC. Rather, PO’s argument
`
`relies on its expert’s speculation that perhaps Sutardja was built with used parts,
`
`and thus one cannot tell if these hallmarks apply.
`
`-1-
`
`
`
`As to limitation [1.G], PO does not raise any arguments on the merits.
`
`Instead, PO first takes issue with the Petition citing paragraph [0167] of Sutardja as
`
`support for what occurs as part of Sutardja’s remapping of a logical address in
`
`paragraph [0147] (namely, a transfer of valid data), because that support allegedly
`
`appears in an unrelated context. This argument misses the point. Paragraph [0167]
`
`confirms that as part of any remapping of a logical address to a different block,
`
`there must be a transfer of valid data to that different block too. And this argument
`
`is wrong because both paragraphs refer to how Sutardja’s wear leveling module
`
`works. PO then objects to the Petition’s explanation of why a collective count falls
`
`within the claim scope. This argument should be ignored because PO has agreed
`
`in the related district court case that a collective count falls within the claim scope.
`
`The Board should find that claims 1-2 and 6-7 are unpatentable.
`
`II.
`
`The Board Should Again Reject PO’s Attempt to Construe “Blocks” to
`Mean “Physical Blocks”1
`PO’s proposed construction of “blocks,” i.e., “in a non-volatile memory, a
`
`physical group of memory cells that must be erased together,” is just another way
`
`of saying “physical blocks.” POR, 25-26 (characterizing dispute as “blocks” must
`
`1 Petitioner agrees with PO that no constructions of “data integrity test” and “on a
`
`periodic basis” are necessary to resolve this proceeding. POR, 29-32.
`
`-2-
`
`
`
`“be physical as opposed to logical blocks”). For good reason, the Board already
`
`rejected PO’s attempt to limit “blocks” to “physical blocks.” ID, 15-16.
`
`As to the claim language, first, because patentee chose the broader claim
`
`term, “block,” as opposed to the narrower term, “physical block,” the claim scope
`
`must reflect this “choice of words.” Novo Nordisk A/S v. Eli Lilly & Co., No.
`
`CIV.A.: 98-643 MMS, 1999 WL 1094213, at *17 (D. Del. Nov. 18, 1999) (“[I]f
`
`Lilly had desired to limit the claims to ‘human patients,’ it could have used that
`
`language instead of ‘patient.’ Since Lilly chose to use the broader term[ ] . . .
`
`‘patient,’ the scope of the claims should reflect its choice of words.”); see also
`
`Evolusion Concepts, Inc. v. HOC Events, Inc., 22 F.4th 1361, 1366-67 (Fed. Cir.
`
`2022) (ruling that the district court erred in limiting the term “magazine catch bar”
`
`where “[t]he inventors … did not choose to claim a device with a ‘new’ or
`
`‘different’ magazine catch bar, but instead a device with ‘a magazine catch bar,’
`
`which, by its ordinary meaning, could be either the removed catch bar or a new or
`
`different catch bar”) (emphasis in original). Here, the specification references
`
`“logical block,” “physical block,” and “block” (Ex. 1005, 2:26-44, 3:9-31, 6:46-
`
`58), and patentee deliberately chose to use the broad claim term “block.” Thus, the
`
`claim scope of “block” must “reflect [patentee’s] choice of words” and include
`
`within its scope both logical and physical blocks. Novo Nordisk A/S, 1999 WL
`
`1094213, at *17.
`
`-3-
`
`
`
`Second, the surrounding claim language confirms that the claim term
`
`“blocks” includes logical blocks within its scope. Claims 1 and 6 start with “one
`
`MLC non-volatile memory module comprising a plurality of individually erasable
`
`blocks.” The claims then recite “maintain[ing] an address map of … the MLC …
`
`non-volatile memory module[].” That map includes (1) “logical address ranges
`
`having a minimum quanta of addresses” that (2) each “maps” to (3) “a similar
`
`range of physical addresses.” This claim language, as PO’s expert confirms,
`
`“map[s] logical blocks to physical blocks.”2 Ex. 2014, ¶ 33. Thus, this “map[]”
`
`limitation expressly requires that the claimed “blocks” exist as both logical and
`
`physical blocks. Indeed, claim 2 of the related 298 patent, which depends from
`
`claim 1 with the same limitation, specifies that “the minimum quanta of [logical]
`
`addresses is equal to one block,” expressly incorporating in the claim language
`
`logical and physical blocks. Ex. 1001, 8:10-11; Ex. 1057 (“Liu Reply”), ¶ 14.
`
`Third, the claim language would be nonsensical if “block” meant only a
`
`“physical block.” Claim 1 recites that the controller “segregates those blocks [e.g.,
`
`blocks in MLC] that receive frequent writes into the at least one SLC non-volatile
`
`2 A “block” in flash memory may exist in two corresponding forms: the physical
`
`form (“physical block”) and a corresponding logical form (“logical block”).
`
`Ex. 1005, 3:9-31; Liu Reply, ¶ 13.
`
`-4-
`
`
`
`memory module” and Claim 6 recites that the controller “allocates those blocks …
`
`to the at least one SLC non-volatile memory module.” Here, there can be no
`
`dispute that “those blocks” (which refers back to “the blocks”) means “logical
`
`blocks.” One cannot “segregate” or “allocate” an MLC physical block into the
`
`SLC module, e.g., physically relocate that block. Rather, as both parties’ experts
`
`agree, this limitation refers to segregating or allocating the logical blocks into the
`
`SLC module by remapping the logical block from MLC to SLC. Ex. 1059, 80:1-
`
`84:1, 102:21-105:16; Liu Reply, ¶ 15.
`
`In the face of all this, PO argues that “the blocks” must mean “physical
`
`blocks” because the claim recites “a plurality of individually erasable blocks,” and
`
`“only physical (and not logical) blocks can be erased.” POR, 26-29. This
`
`argument fails for three independent reasons.
`
`First, it is wrong. As Dr. Khatri conceded in his deposition, logical blocks
`
`were (and are) erasable. Dr. Khatri, for example, admits that Moshayedi
`
`(Ex. 1012) discloses “the erase count of a logical block.” Ex. 1059, 168:19-169:8.3
`
`3 Although Dr. Khatri now admits that logical blocks are erasable by the host, he
`
`suggests that the 240 patent defines “erasable” as physical erasure, contrary to its
`
`plain and ordinary meaning. Ex. 1059, 48:6-21. As discussed below, there is no
`
`-5-
`
`
`
`It was well known in the art that logical blocks are erasable. E.g., Ex. 1061, 3:54-
`
`4:2 (“delet[ing]” a “logical block”), 6:63-7:5 (“logical block level erasure”);
`
`Ex. 1062, 2:10-34 (“The host can issue a sector erase command to erase the logical
`
`sector in the memory.”); Ex. 1012, Claim 2 (“the one or more metrics associated
`
`with erasing data blocks comprise an erase count of a logical block address
`
`(LBA)”). Liu Reply, ¶¶ 16-17.
`
`Second, even if this erase language references the physical block form of a
`
`“block” (it doesn’t), Claims 1 and 6 later confirm that the “block” also has a
`
`logical block form with the “map[]” limitations. This shows that “block” includes
`
`both forms.
`
`Third, even if this erase language specifies a physical block (it doesn’t),
`
`“the patentee’s mere use of a term with an antecedent does not require that both
`
`terms have the same meaning” where a uniform reading is “nonsensical.”
`
`Microprocessor Enhancement Corp. v. Texas Instruments Inc., 520 F.3d 1367,
`
`1375 (Fed. Cir. 2008). Both parties’ experts agree that it would be nonsensical to
`
`lexicography or disclaimer here. Also, it makes little sense to argue that the 240
`
`patent would define “erase” to exclude host erases because the 240 specification
`
`and claims refer to host accesses. Ex. 1005, 2:34-44, 2:66-3:19, 5:20-22, Claims 1,
`
`6 (“maps” limitation).
`
`-6-
`
`
`
`actually “allocate” or “segregate” physical blocks. Ex. 1059, 80:1-84:1, 102:21-
`
`105:16; Liu Reply, ¶ 15.
`
`As to the specification and file history, there is no disclaimer or
`
`lexicography that limits “blocks” to “physical blocks.” Acceleration Bay, LLC v.
`
`Activision Blizzard Inc., 908 F.3d 765, 770-71 (Fed. Cir. 2018) (requiring “precise
`
`and clear language” to read in limitation). To the contrary, the only relevant
`
`embodiment (describing “blocks” that are “accessed” and “allocate[d]”) uses the
`
`generic term “blocks” in describing these actions. Ex. 1005, 6:46-58. And as
`
`noted above, both parties’ experts agree that logical blocks are being allocated.
`
`III. The Dusija in View of Sutardja Ground Renders Obvious Limitations
`[1.F]-[1.G]
`For the Dusija in view of Sutardja ground, PO only argues that the ground
`
`fails to render obvious limitations [1.F]-[1.G]. PO makes a series of scattershot
`
`arguments that boil down to: (1) asking the Board to improperly import a limitation
`
`into the claims, and (2) asking the Board to ignore express disclosures in the prior
`
`art.
`
`Dusija and Sutardja Teach Counting and Segregating Blocks
`Based On Write Frequency (Limitation [1.F])
`PO argues that Dusija and Sutardja’s showings do not render obvious
`
`limitation [1.F] (“wherein the controller is further adapted to determine which of
`
`the blocks of the plurality of the blocks in the MLC and SLC non-volatile memory
`
`-7-
`
`
`
`modules are accessed most frequently and wherein the controller segregates those
`
`blocks that receive frequent writes into the at least one SLC non-volatile memory
`
`module and those blocks that receive infrequent writes into the at least one MLC
`
`nonvolatile module”) for three reasons: (1) the combination does not disclose (a)
`
`“which of the blocks…are accessed most frequently” and (b) “segregat[ing] those
`
`blocks,” because the claimed “block” should be construed to mean “physical
`
`block,” (POR, 34-39), even though claim language and specification contradict
`
`importing such a limitation into the claims; (2) the combination does not determine
`
`which “blocks” “are accessed most frequently” (POR, 39-40), even though
`
`Sutardja discloses “map[ping] the logical addresses [i.e., logical blocks] having
`
`high write frequencies (e.g., having write frequencies greater than a
`
`predetermined threshold) to the second NVS memory in step 508” (Ex. 1011
`
`(“Sutardja”), [0146]);4 and (3) Sutardja’s first and second memories are not MLC
`
`and SLC, respectively (POR, 41-45), even though they are part of a “hybrid”
`
`memory (SLC and MLC memory) and each have all the hallmarks of MLC and
`
`SLC in a hybrid memory—namely, the second memory has a higher write cycle
`
`lifetime, is more expensive, and is faster than the first memory. PO’s arguments
`
`do not a raise a serious challenge to the Petition’s showing.
`
`4 Emphasis added throughout unless otherwise noted.
`
`-8-
`
`
`
`1. PO’s “Block” Argument Fails Because It Relies on an Incorrect
`Construction of “Block”
`PO argues that the Petition relies on Sutardja’s “measurements of logical
`
`address write frequencies” for this limitation. POR, 34. PO then argues that these
`
`disclosures cannot disclose limitation [1.F] because this limitation requires
`
`counting accesses to physical blocks, not logical addresses (logical blocks). POR,
`
`35-39. The Board already rejected this argument because PO did not identify any
`
`specific evidence suggesting that the claimed “block” should be limited to only a
`
`“physical block.” ID, 15-16. Indeed, the full record demonstrates that it would be
`
`legal error to limit “block” to a “physical block.” Section II. Accordingly, PO’s
`
`logical block count argument fails because it relies entirely on an erroneous
`
`construction of “block.” Id. If “blocks” are construed to include both logical and
`
`physical blocks, there is no dispute that this limitation is met. Ex. 1059, 135:17-
`
`21. Indeed, Sutardja determines which logical addresses (i.e., logical blocks) are
`
`most frequently written by maintaining counts of writes to each logical address
`
`range. Petition, 44; Sutardja, [0146]-[0147] (describing steps 506-510 of Fig. 7
`
`that measures logical writes and maps frequently written logical blocks to SLC);
`
`Ex. 1057 (“Liu Reply”), ¶ 18.
`
`PO attempts to sidestep the fact that the Petition also demonstrated that both
`
`Sutardja and Dusija disclose physical block counting. Petition, 44. As to Sutardja,
`
`the ID states: “Petitioner identifies portions of Sutardja that teach determining
`
`-9-
`
`
`
`which physical addresses are accessed most frequently.” ID, 16, n.2. Indeed, the
`
`Petition demonstrated that Sutardja’s “wear leveling module” counts both physical
`
`and logical block accesses. Petition, 44. For example, the Petition cites Sutardja at
`
`paragraph [0111], which discloses that “the wear leveling module may track the
`
`number of times that each block has been erased or written.”5 Sutardja, [0111]. Dr.
`
`Khatri admits that this discloses tracking accesses to physical blocks. Ex. 1059,
`
`112:20-115:6; Liu Reply, ¶ 19. As to Dusija, the Petition cites to Dusija for its
`
`“hot count,” which is a count of the erase/program cycles on “each erase block of
`
`memory cells.” Petition, 44 (citing Ex. 1010 (“Dusija”), [0153]). And Dusija’s
`
`“erase blocks” are physical blocks. Dusija, [0153] (discussing “erase and program
`
`operations” that tracks the “endurance” of the block), [0077]-[0079] (detailing
`
`addition and removal of charge during programming and erasure of “erase
`
`blocks”); Liu Reply, ¶ 20. PO does not dispute that Dusija’s “hot count” is a count
`
`of accesses to physical blocks.
`
`PO effectively ignores these clear and undisputed disclosures and argues that
`
`“[t]he Petition presents no evidence for why a system that determines how
`
`5 The Petition also cites Sutardja at paragraph [0121], which likewise discloses the
`
`“wear leveling module” tracking physical erases and write counts for each block.
`
`Sutardja, [0121]; Liu Reply, ¶ 19.
`
`-10-
`
`
`
`frequently data is written to each of the logical addresses can meet a limitation that
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`requires determining which blocks are accessed most frequently. Furthermore, the
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`Petition presents no evidence for why it would have been obvious to modify
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`Sutardja to do so.” POR, 36-37. This misses the point. Sutardja already discloses
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`tracking physical counts, as does Dusija, and thus no modification is necessary to
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`track physical block accesses. Indeed, Sutardja’s disclosures expressly contradict
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`PO’s implicit argument that some sort of modification to Sutardja is necessary.
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`Sutardja makes clear that its techniques that use a count may use either a physical
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`or a logical access count. For example, Sutardja discloses that its wear leveling
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`module, which tracks accesses to both physical and logical blocks, may either use
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`the physical or logical count to move (“bias”) frequently written blocks to SLC.
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`Sutardja, [0128] (using physical count), [0129]-[0130] (using logical count). By
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`way of another example, in claim 1, Sutardja discloses “map[ping] logical
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`addresses to physical addresses of one of said first and second NVS memories.”
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`Dependent claim 8, which depends on claim 1, adds that the system may track
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`accesses to logical addresses and bias frequently written logical addresses (logical
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`blocks) to SLC. Dependent claim 13, which depends on claim 1, adds that the
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`system may track accesses to physical addresses and perform the same biasing.
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`Liu Reply, ¶ 21.
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`-11-
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`
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`Unable to meaningfully dispute that both Sutardja and Dusija disclose
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`tracking accesses to physical blocks (limitation [1.F.i]), PO appears to argue that
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`this is not enough because the same exact disclosures do not also disclose
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`“segregat[ing] those blocks that receive frequent writes” to SLC (limitation
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`[1.F.ii]).6 POR, 35-38. Putting aside that Sutardja expressly discloses that its
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`techniques are appliable to physical and logical access counts (see above), this
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`argument also ignores that the Petition’s ground is an obviousness ground, not an
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`anticipation ground. The Petition relies on Sutardja’s use of a count (“measures
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`actual write frequencies”) to, for example, redirect the incoming data for a write
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`command from MLC to SLC if the count is above a threshold. Petition, 45.
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`Sutardja and Dusija disclose both logical and physical counts (see above),
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`providing either as a possible input for Sutardja’s write redirection. Thus, the
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`Petition demonstrated that it would have been obvious to use either a physical or
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`6 It is unclear whether PO contends that Dusija only discloses an “erase count” for
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`a single block. POR, 35. If so, the argument is both illogical and incorrect. It
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`would be illogical to track the erases of only a single block. Liu Reply, ¶ 23. It
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`would be incorrect because Dusija discloses maintaining “a hot count maintained
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`with each erase block of memory cells.” Dusija, [0153].
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`-12-
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`
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`logical count with Sutardja’s write redirection to arrive at limitation [1.F.i-ii.].
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`Petition, 44-45.
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`2. PO’s Apparent Single-Block Argument Strains Credibility
`PO asserts: “[n]one of the cited paragraphs which disclose ‘write
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`frequencies’ teach or suggest determining the blocks which are accessed most
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`frequently.” POR, 40. While hard to discern, it appears that PO is arguing that
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`Dusija in view of Sutardja does not render obvious determining which blocks are
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`frequently written because the relevant disclosures are operating on a single block.7
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`POR, 39-40. This argument is nonsense.
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`PO fails to address the Petition’s citation to Sutardja at paragraph [0112]
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`which states that the “the wear leveling module determines how frequently data is
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`written to each of the logical addresses.” Petition, 44 (citing Sutardja, [0112]-
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`[0113]). That is, the counting and frequency determination occurs on multiple
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`blocks (LBAs). And the Petition cites to Sutardja at paragraphs [0146]-[0147],
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`which explain write-redirection using logical access counts. Id. Specifically,
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`Sutardja discloses that the “[c]ontrol measures actual write frequencies at which
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`data is in fact written to the logical addresses,” i.e., tracks the write counts to
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`7 In passing, PO also argues that Sutardja discloses only logical block counting.
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`POR, 39-40. This fails for the reasons set forth in Section II.A.1.
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`-13-
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`
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`multiple logical addresses (“each of” the logical blocks). Sutardja, [0147].
`
`Sutardja further discloses that the “[c]ontrol maps the logical addresses having
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`high write frequencies (e.g., having write frequencies greater than a predetermined
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`threshold) to the second NVS memory in step 508,” i.e., to SLC. Id., [0146].
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`There is no legitimate dispute here: Sutardja is operating on multiple blocks and,
`
`for those multiple blocks, is determining which of the blocks are frequently
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`written. Liu Reply, ¶ 22
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`PO continues this nonsense in arguing that Sutardja at paragraph [0111]
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`discloses counting accesses to a “block” that “has been written to the least.”
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`POR, 40. But this same paragraph discloses that Sutardja “track[s] the number of
`
`times that each block has been erased or written,” i.e., a count for each block.
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`Sutardja, [0111]. Here, Sutardja is tracking the erases and writes to physical
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`blocks (see above, Section III.A.1). PO makes a similar argument that Dusija’s
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`“hot count” is a “one-time decision to turn on the ‘error management’ for a single
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`block.” POR, 39. But that very same paragraph of Dusija discloses that its “hot
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`count” is a count of the erase-program cycles on “each erase block of memory
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`cells.” Dusija, [0153]. Liu Reply, ¶ 23
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`Realizing it has no legitimate arguments on the merits, PO alleges that the
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`Petition has a “defect” because it “states in a conclusory manner that the claim
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`language is satisfied.” POR, 40. It appears that PO is arguing that it is unclear that
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`-14-
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`
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`the Petition relies on Sutardja at paragraphs [0146]-[0147] for its disclosure of
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`determining frequently written blocks. This, too, is groundless. The Petition
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`details how Sutardja and Dusija disclose counting accesses, and how Sutardja uses
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`a count to direct frequently written blocks to SLC. Petition, 44-45 (citing Sutardja,
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`[0146]-[0147]). The POR acknowledges this showing. Indeed, PO refers to the
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`Petition’s “repeated references [] made to … [0146] and [0147],” and attempts to
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`distinguish this disclosure because it relates to logical block counting. POR, 34.
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`For its “single block” argument, PO cites paragraphs [0146]-[0147] of Sutardja and
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`argues that they “relate to logical addresses that do not meet the correct
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`construction of ‘blocks.’” Id., 39. PO’s repeated attempts to distinguish
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`paragraphs [0146]-[0147] of Sutardja undermines any notion that PO was not
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`aware of the Petition’s mapping of these disclosures to the claims. Microsoft Corp.
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`v. FG SRC, LLC, 860 Fed. App’x. 708, 713 (noting that the “understanding of an
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`opposing party may be relevant to whether a petitioner’s argument was fairly
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`raised”).
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`3. PO’s “Second NVS” Argument Ignores the Record
`PO argues that Sutardja’s “first NVS memory” is not MLC and its “second
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`NVS memory” is not SLC. POR, 41-45. The Board previously rejected this
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`argument, and with good reason. ID, 18-19. To start, Sutardja discloses a
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`“hybrid” memory in which the second NVS memory has a greater write cycle
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`-15-
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`
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`lifetime, is more expensive, and is faster than the first NVS memory. Petition, 24-
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`25; Sutardja, [0106], [0114], [0145]. As was well known, such a “hybrid” memory
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`includes MLC and SLC and each of these characteristics of the second NVS
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`memory are hallmarks of SLC while the characteristics of the first NVS memory
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`are hallmarks of MLC. Ex. 1009 (“Liu Decl.”), ¶¶ 79-80 (citing seven supporting
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`references).8 What’s more, Sutardja’s claims describe that the second memory has
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`a greater lifetime than the first memory, and then specifies that it “includes” SLC,
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`further confirming it is the SLC portion of the hybrid memory while the first
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`memory “includes” MLC which confirms it is the MLC portion of the memory.
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`Sutardja, [0106], [0108], claims 1, 37; Liu Reply, ¶¶ 24-25.
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`Despite all this, PO argues that Sutardja is indifferent to whether second
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`memory is SLC and the first memory is MLC. POR, 42. This makes no sense.
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`The entire point of transferring frequently written blocks from MLC to SLC is that
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`SLC can be written faster and is more durable while MLC is denser and cheaper.
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`Liu Decl., ¶ 79 (citing Ex. 1020), ¶ 210 (citing five supporting references). Dr.
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`Khatri’s only basis for asserting that Sutardja’s statements do not mean that the
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`second memory is SLC and the first memory is MLC is absurd: that perhaps
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`8 Dr. Liu supports his opinion with a plethora of citations to the prior art, and thus
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`he does not use hindsight. POR, 45.
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`-16-
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`
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`Sutardja’s hybrid memory is built with used parts, and the used MLC and SLC
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`parts already had usage counts before manufacture. Ex. 1059, 119:1-120:16. This
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`illogical speculation should be rejected. Sutardja also provides an exemplary
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`embodiment where the first NVS memory has a 10,000 write cycle lifetime, which
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`matches that of MLC, and the second NVS memory has a 100,000 write cycle
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`lifetime, which matches that of SLC. Ex. 1009, ¶ 82; Sutardja, [0161]. When
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`accompanied by Claim 37’s disclosure that the first memory “includes” MLC, a
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`POSA would have understood Sutardja to disclose (or at least suggest) that the first
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`memory is MLC and the second memory is SLC. Sutardja, [0019], [0108], Claim
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`37. Indeed, a POSA would have understood Sutardja to disclose such a hybrid,
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`homogenous system with MLC and SLC memory because it would allow Sutardja
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`to simultaneously reduce costs while maximizing lifetime as compared to a
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`memory with only one of MLC or SLC. Sutardja, [0006], [0009]; Liu Decl.,
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`¶¶ 79-80; Liu Reply, ¶¶ 24-25.
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`Next, PO contends that Sutardja’s disclosure relating
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