Case 6:21-cv-00487-ADA Document 33 Filed 01/03/22 Page 1 of 23
`
`UNITED STATES DISTRICT COURT
`WESTERN DISTRICT OF TEXAS
`WACO DIVISION
`
`Civil Action No. 6:21-cv-487-ADA
`
`Vervain, LLC
`
`Plaintiff,
`
`v.
`Micron Technology, Inc.;
`Micron Semiconductor Products, Inc.; and
`Micron Technology Texas, LLC
`Defendants.
`
`Vervain, LLC
`
`
`
`
`
`Plaintiff,
`
`Civil Action No. 6:21-cv-488-ADA
`
`v.
`Western Digital Corporation;
`Western Digital Technologies Inc.; and
`HGST, Inc.
`
`Defendants.
`
`VERVAIN’S SUR-REPLY CLAIM CONSTRUCTION BRIEF
`
`
`
`
`
`
`
`
`
`
`
`Micron Ex. 1067, p. 1
`Micron v. Vervain
`IPR2021-01549
`
`

`

`Case 6:21-cv-00487-ADA Document 33 Filed 01/03/22 Page 2 of 23
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`
`
`TABLE OF CONTENTS
`
`TABLE OF AUTHORITIES .......................................................................................................... ii 
`
`TABLE OF EXHIBITS ................................................................................................................. iii 
`
`DISPUTED CLAIM CONSTRUCTIONS (PLAIN MEANING TERMS)................................... iv 
`
`DISPUTED CLAIM CONSTRUCTIONS (NOT INDEFINITE TERMS) .....................................v 
`
` 
`
` 
`
`INTRODUCTION ...............................................................................................................1 
`
`THE PLAIN MEANING TERMS .......................................................................................1 
`
`A. 
`
`B. 
`
`C. 
`
`D. 
`
`E. 
`
`“SLC non-volatile memory” (298:1, 5; 385:1, 5; 240:1, 6;
`300:1, 3, 4, 7, 12) .....................................................................................................1 
`
`“MLC non-volatile memory” (298:1, 4; 385:1, 4; 240:1, 6;
`300:1, 3, 4, 12) .........................................................................................................1 
`
`“data integrity test” (298:1; 385:1; 240:1, 6; 300:1, 12) ..........................................3 
`
`“comparing the stored data to the retained data in the random
`access volatile memory” (300:1, 12) .......................................................................6 
`
`“to achieve enhanced endurance” (300:1, 12) .........................................................8 
`
` 
`
`THE NOT INDEFINITE TERMS .....................................................................................10 
`
`A. 
`
`B. 
`
`C. 
`
`D. 
`
`E. 
`
`“the list of logical address ranges having a minimum quanta
`of addresses” (298:1; 385:1; 240:1, 6) ...................................................................10 
`
`The wherein clause in 240:1 ..................................................................................11 
`
`The wherein clause in 240:6 ..................................................................................12 
`
`“wherein the mapping is performed as necessitated by the
`system to maximize lifetime” (300:1, 12)..............................................................12 
`
`“wherein a failure of the data integrity test performed by the
`controller results in a remapping of the address space to a
`different physical range of addresses and transfer of data
`corresponding to the stored data to those remapped physical
`addresses” (300:1, 12) ............................................................................................14 
`
` 
`
`CONCLUSION ..................................................................................................................15 
`
`
`
`
`
`i
`
`Micron Ex. 1067, p. 2
`Micron v. Vervain
`IPR2021-01549
`
`

`

`Case 6:21-cv-00487-ADA Document 33 Filed 01/03/22 Page 3 of 23
`
`TABLE OF AUTHORITIES
`
`Page(s)
`
`
`
`
`CASES
`
`Berkheimer v. HP Inc.,
`881 F.3d 1360 (Fed. Cir. 2018)................................................................................................11
`
`Curtiss-Wright Flow Control Corp. v. Velan, Inc.,
`438 F.3d 1374 (2006) .................................................................................................................9
`
`Datamize, LLC v. Plumtree Software, Inc.,
`417 F.3d 1342 (Fed. Cir. 2005)................................................................................................12
`
`Mastermine Software v. Microsoft Corp.,
`874 F.3d 1307 (Fed. Cir. 2017)................................................................................................15
`
`Nautilus, Inc. v. Biosig Instruments, Inc.,
`572 U.S. 898 (2014) .................................................................................................................14
`
`PPC Broadband, Inc. v. Corning Optical Commc’s RF, LLC,
`815 F.3d 747 (Fed. Cir. 2016)....................................................................................................5
`
`
`
`
`
`
`ii
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`Micron Ex. 1067, p. 3
`Micron v. Vervain
`IPR2021-01549
`
`

`

`Case 6:21-cv-00487-ADA Document 33 Filed 01/03/22 Page 4 of 23
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`
`
`TABLE OF EXHIBITS
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`Exhibit Description
`25
`U.S. Patent Application Publication No. 2009/0172267 (“Oribe”)
`26
`U.S. Patent Application Publication No. 2010/0172179 (“Gorobets”)
`27
`U.S. Patent Application Publication No. 2008/0181000 (“Lasser”)
`28
`U.S. Patent Application Publication No. 2009/0268513 (“De Ambroggi”)
`29
`U.S. Patent Application Publication No. 2011/0271043 (“Segal”)
`30
`Arpaci-Dusseau, Operating Systems: Three Easy Pieces, chapter 43 (2013),
`available at:
`http://web.archive.org/web/20131013025741/https://pages.cs.wisc.edu/~remzi/OST
`EP/file-integrity.pdf
`
`
`
`iii
`
`Micron Ex. 1067, p. 4
`Micron v. Vervain
`IPR2021-01549
`
`

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`Case 6:21-cv-00487-ADA Document 33 Filed 01/03/22 Page 5 of 23
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`
`
`DISPUTED CLAIM CONSTRUCTIONS (PLAIN MEANING TERMS)
`
`Terms
`SLC non-volatile
`memory
`
`
`SLC nonvolatile
`memory
`MLC non-volatile
`memory
`
`
`MLC nonvolatile
`memory
`data integrity test
`
`2
`
`# Claim(s)
`1
`298:1, 5
`385:1, 5
`240:1, 6
`
`300:1, 3,
`4, 7, 12
`298:1, 4
`385:1, 4
`240:1, 6
`
`300:1, 3,
`4, 12
`298:1
`385:1
`240:1, 6
`300:1, 7,
`12
`
`3
`
`4 300:1, 12 comparing the
`stored data to the
`retained data in
`the random access
`volatile memory
`to achieve
`enhanced
`endurance
`
`5 300:1, 12
`
`
`
`
`
`Plain and ordinary meaning
`
`Micron
`
`WD1
`non-volatile
`memory where
`each cell is capable
`of storing no more
`than one bit of
`information per cell
`non-volatile
`memory where
`each cell is capable
`of storing multiple
`bits of information
`per cell
`
`
`Vervain
`Plain and ordinary
`meaning, where the plain
`and ordinary meaning is
`“nonvolatile memory that
`stores one bit of
`information per cell”
`Plain and ordinary
`meaning, where the plain
`and ordinary meaning is
`“nonvolatile memory that
`stores multiple bits of
`information per cell”
`Plain and ordinary meaning Current proposal:
`“testing data for
`errors after the data
`has been written to
`flash”
`Former proposal:
`Plain and ordinary
`meaning, which is “a
`test conducted on
`data after it has been
`written to flash to
`ensure that the data
`was written
`correctly”
`comparing the data obtained by reading the
`nonvolatile memory space to the data
`retained as part of a Write access operation,
`wherein both sets of the data are in the same
`random access volatile memory
`Plain and ordinary meaning Plain and ordinary
`
`meaning, which is “to
`achieve endurance
`(i.e., lifetime)
`superior to that of the
`MLC nonvolatile
`memory element
`
`
`
`
`1 All 10 terms were identified by Defendants. Terms 1-2, 6, and 9 were identified by Western
`Digital (WD), and Micron takes no position. Terms 3, 5, and 10 were identified by Micron, and
`WD takes no position. Terms 4 and 7-8 were identified by Micron and WD.
`
`iv
`
`Micron Ex. 1067, p. 5
`Micron v. Vervain
`IPR2021-01549
`
`

`

`Case 6:21-cv-00487-ADA Document 33 Filed 01/03/22 Page 6 of 23
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`
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`DISPUTED CLAIM CONSTRUCTIONS (NOT INDEFINITE TERMS)
`
`Terms
`the list of logical address ranges having a
`minimum quanta of addresses
`
`wherein the controller is further adapted to
`determine which of the blocks of the plurality of
`the blocks in the MLC and SLC non-volatile
`memory modules are accessed most frequently
`and wherein the controller segregates those
`blocks that receive frequent writes into the at
`least one SLC non-volatile memory module and
`those blocks that receive infrequent writes into
`the at least one MLC nonvolatile module, and
`maintain a count value of the blocks in the MLC
`non-volatile memory module determined to have
`received frequent writes and that are accessed
`most frequently on a periodic basis when the
`count value is a predetermined count value,
`transfer the contents of the counted blocks in the
`MLC non-volatile memory module determined
`to have received frequent writes after reaching
`the predetermined count value to the SLC non-
`volatile memory module and which determined
`blocks in the SLC are determined in accordance
`with the next equivalent range of physical
`addresses determined by the controller
`wherein the controller is further adapted to
`maintain a count value of those blocks that are
`accessed most frequently and, on a periodic
`basis when the count value is a predetermined
`count value, transfer the contents of those
`counted blocks into the SLC non-volatile
`memory module, wherein the counted blocks
`transferred to after reaching the predetermined
`count value are determined in accordance with
`the next equivalent range of physical addresses
`determined by the controller
`300:1, 12 wherein
`the mapping
`is performed as
`necessitated by the system to maximize
`lifetime
`300:1, 12 wherein a failure of the data integrity test
`performed by the controller results in a
`remapping of the address space to a
`different physical range of addresses and
`transfer of data corresponding to the stored
`data to those remapped physical addresses
`
`240:6
`
`# Claim(s)
`6
`298:1
`385:1
`240:1, 6
`240:1
`
`7
`
`8
`
`9
`
`10
`
`
`
`Vervain
`Plain and
`ordinary
`meaning
`Plain and
`ordinary
`meaning
`
`Micron
`
`
`
`WD
`Indefinite
`
`Indefinite.
`Although it is possible for
`a person of ordinary skill
`(“POSA”) to identify some
`embodiments that fall
`within the scope of the
`claim, a POSA would not
`be reasonably certain of
`the full scope of the claim.
`
`Plain and
`ordinary
`meaning
`
`Plain and
`ordinary
`meaning
`Plain and
`ordinary
`meaning
`
`Indefinite.
`Although it is possible for
`POSA to identify some
`embodiments that fall
`within the scope of the
`claim, a POSA would not
`be reasonably certain of
`the full scope of the claim.
`
`
`
`Indefinite
`
`
`
`Indefinite
`under IPXL
`Holdings v.
`Amazon.com
`
`v
`
`Micron Ex. 1067, p. 6
`Micron v. Vervain
`IPR2021-01549
`
`

`

`Case 6:21-cv-00487-ADA Document 33 Filed 01/03/22 Page 7 of 23
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`
`
`INTRODUCTION
`
`Plain meaning is the proper claim construction for all 10 disputed claim terms. For the first
`
`five terms, Defendants import limitations that are inconsistent with the intrinsic record and
`
`Defendants’ own documents. For some of terms, Defendants rely heavily on expert testimony to
`
`rewrite the prosecution history. These strained and convoluted arguments are not clear disavowal.
`
`For the next five terms, Defendants argue the terms are indefinite, even though Micron’s expert
`
`understands their meaning in Micron’s IPRs. Meanwhile, the specification explains exactly what
`
`the claim terms mean. In their Opening Brief, Defendants ignored the specification. Now,
`
`Defendants fault Vervain for looking to the specification. But the test is whether the claims, read
`
`in light of the specification, inform with reasonable certainty the scope of the invention. The Court
`
`should be wary of Defendants’ arguments. For many of the terms, Defendants have
`
`mischaracterized Vervain’s positions and shifted their own positions to try and make their
`
`constructions appear less objectionable than they really are.
`
`
`
`THE PLAIN MEANING TERMS
`
`The plain and ordinary meaning applies to each of the following terms. Vervain’s plain
`
`meaning constructions for SLC and MLC should be adopted. The rest need no construction.
`
`A.
`
`“SLC non-volatile memory” (298:1, 5; 385:1, 5; 240:1, 6; 300:1, 3, 4, 7, 12)
`
`Vervain
`Plain and ordinary meaning, where the plain
`and ordinary meaning is “nonvolatile memory
`that stores one bit of information per cell”
`
`Micron
`
`
`WD
`Non-volatile memory where each
`cell is capable of storing no more
`than one bit of information per cell
`
`B.
`
`“MLC non-volatile memory” (298:1, 4; 385:1, 4; 240:1, 6; 300:1, 3, 4, 12)
`
`Vervain
`Plain and ordinary meaning, where the plain
`and ordinary meaning is “nonvolatile memory
`that stores multiple bits of information per cell”
`
`Micron
`
`
`WD
`Non-volatile memory where each
`cell is capable of storing multiple
`bits of information per cell
`
`1
`
`Micron Ex. 1067, p. 7
`Micron v. Vervain
`IPR2021-01549
`
`

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`Case 6:21-cv-00487-ADA Document 33 Filed 01/03/22 Page 8 of 23
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`WD does not dispute that under its construction, a dual-mode memory cell that is
`
`configured to operate in SLC-mode might be considered MLC, even though it has the functional
`
`characteristics of SLC. Dkt. 31, 5-8. WD also “does not dispute” that SLC and MLC memory
`
`have dramatic differences in speed, endurance, and capacity. Id., 6. Yet WD still suggests through
`
`its construction that dual-mode memory is always “MLC,” even when it is configured in SLC
`
`mode with improved speed and endurance.
`
`Faced with this inconsistency between WD’s construction and the patent specification, WD
`
`resorts to the theory that Vervain’s claims were developed “at a time where hardware was
`
`incapable of being used variably to store one or multiple bits per cell.” Dkt. 31, 2. In other words,
`
`WD claims that because configurable SLC-mode/MLC-mode (dual-mode) flash did not exist at
`
`the time of Vervain’s invention, it should not be considered as part of claim construction. But this
`
`is not true: dual-mode flash was well known at the time of the invention. In fact, the intrinsic
`
`record is replete with references to configurable dual-mode memory—some of them in WD’s own
`
`patents. For example, Gorobets2 described multiple systems for allocating memory into mixed
`
`MLC and SLC modes. Ex. 26, [0131, 0133-34]. Lasser also acknowledged “SLC mode” memory.
`
`Ex. 27, [0056]. Other intrinsic references similarly discussed memory devices “programmable . .
`
`. to have either an SLC configuration or an MLC configuration.” Ex. 28, [0036]; Ex. 29, [0026]
`
`(“a common pool of spare blocks may be apportioned as a pool of spare SLC blocks and a pool of
`
`spare MLC blocks”).
`
`Vervain’s own patent specification explains that “a system may set SLC NAND flash equal
`
`to 12.5% or 25% of MLC NAND flash (total non-volatile memory storage space=MLC+SLC).”
`
`Dkt. 29-3, 4:61-63. This shows that the patents themselves contemplate that SLC-mode flash may
`
`
`2 Gorobets and Lasser both list SanDisk, Western Digital’s predecessor, as the assignee.
`
`2
`
`Micron Ex. 1067, p. 8
`Micron v. Vervain
`IPR2021-01549
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`

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`Case 6:21-cv-00487-ADA Document 33 Filed 01/03/22 Page 9 of 23
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`
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`be used, and that it should be referred to as “SLC NAND flash” even if it might have otherwise
`
`been configurable as MLC.
`
`WD admitted in its own Lasser patent application—cited on the face of the 300 patent and
`
`therefore part of the intrinsic record—that “[i]n SLC-type flash memories, each cell stores one bit,
`
`and . . . [i]n MLC-type flash memories, each cell stores multiple bits.” Ex. 27, [0009]. This is
`
`nearly identical to Vervain’s construction, as are the definitions WD provided in its own glossary.
`
`Dkt. 29-8. Yet WD’s briefing does not even address its own glossary definitions, which, to be
`
`clear, are from an Internet Archive copy dated October 20, 2010, not “created after the priority
`
`date of the patents-in-suit.”
`
`Finally, the extrinsic evidence supports Vervain’s construction—even the portions of Lee
`
`that WD cited in the Reply Brief. Lee’s statement that “[b]y storing two (or more) bits on a single
`
`memory cell, MLC flash memory achieves significant density increases” indicates that memory is
`
`only “MLC” flash if two or more bits per cell are stored. Dkt. 29-12, 2. Section 2.3 explains that
`
`“it is possible for [MLC-capable flash memory] to act as SLC flash memory.” Id., 4. This use of
`
`SLC is consistent with Vervain’s construction, not WD’s. And Section 6 explains that “FlexFS
`
`can . . . flexibly increas[e] the size of the SLC region,” indicating that flash that is reconfigured
`
`from MLC to SLC mode, and that flash should be referred to as “SLC.” Id., 14.
`
`In summary, the intrinsic evidence, WD’s extrinsic evidence, and WD’s own admissions
`
`show that in the context of the patents-in-suit, MLC flash is nonvolatile memory that stores
`
`multiple bits per cell, and SLC flash is nonvolatile memory that stores one bit per cell.
`
`C.
`
`“data integrity test” (298:1; 385:1; 240:1, 6; 300:1, 12)
`
`Vervain
`Plain and
`ordinary
`meaning
`
`Micron
`Current proposal: “testing data for errors after the data has been written to
`flash”
`
`WD
`
`
`3
`
`Micron Ex. 1067, p. 9
`Micron v. Vervain
`IPR2021-01549
`
`

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`Case 6:21-cv-00487-ADA Document 33 Filed 01/03/22 Page 10 of 23
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`
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`Former proposal: Plain and ordinary meaning, which is “a test conducted
`on data after it has been written to flash to ensure that the data was written
`correctly”
`
`In the Reply Brief, Micron changed its construction, now contending this term means
`
`“testing data for errors after the data has been written to flash.” But no construction is necessary.
`
`And if the Court decides that a construction is warranted, it should be limited to “test of data for
`
`errors” rather than adding the new limitation “after the data has been written to flash.”
`
`First, Micron argues that the term excludes all testing related to whether data is stored at
`
`the correct location. However, there are data integrity tests that relate to the location where data
`
`is stored. To use Micron’s USPS analogy, suppose someone receives an envelope addressed to
`
`them, but upon opening the envelope finds a letter addressed to someone else. The recipient would
`
`conclude that an error occurred—the sender must have put the letters in the wrong envelopes.
`
`They would determine this by reading the data—the contents of the letter—and noting that the
`
`name and address in the letter differ from the name and address on the envelope.
`
`Storage systems use similar techniques to detect problems with data integrity. For
`
`example, the “Data Integrity and Protection” section of a computer science textbook explains how
`
`disk controllers add a “physical identifier,” containing the “disk and sector number of the block,”
`
`to the “stored information” in each block. Ex. 30, 9. When reading a block, the physical identifier
`
`is verified: “the stored information should include” the correct sector information. If the
`
`information does not match, “a misdirected write has taken plance, and a corruption is now
`
`detected.” Id. 9-10.
`
`Such a test is more than just a comparison of addresses—it is a test of the information read
`
`from the memory. It is classified under “Data Integrity and Protection.” Ex. 30, 1. It indicates
`
`whether the data stored at a particular location is the wrong data—speaking directly to the
`
`4
`
`Micron Ex. 1067, p. 10
`Micron v. Vervain
`IPR2021-01549
`
`

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`Case 6:21-cv-00487-ADA Document 33 Filed 01/03/22 Page 11 of 23
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`“condition, “accuracy,” and “conformity” of the data, consistent with Micron’s dictionary
`
`definitions. See Dkt. 31, 8. And it is a test of data (the data stored at a particular location in flash)
`
`for errors. The construction should not exclude data integrity testing that tests data read from
`
`memory simply because the data read from memory relates to the address where the data is stored.
`
`Second, Micron identifies no lexicography or disavowal to suggest that the limitation of
`
`“after the data has been written to flash” should be imported from the specification. Nor is there
`
`support from the claim language itself. Micron argues that “[a]ll claims of the patents-in-suit”
`
`provide that the data integrity test is performed on data after it has been written to flash memory,
`
`but most of the claims recite no such limitation. For example, in the 298 and 385 patents, the only
`
`reference to “writes” is in step (d) of claim 1, whereas the data integrity test is recited in step (b).
`
`The case law cited by Micron does little to support its position. PPC Broadband holds (in
`
`the context of the broadest-reasonable-interpretation standard used only by the USPTO) that the
`
`claims and specification inform the skilled artisan as to the definition; PPC Broadband does not
`
`hold that it is proper to import limitations from the specification, as Micron attempts to do here.
`
`See PPC Broadband, Inc. v. Corning Optical Commc’s RF, LLC, 815 F.3d 747, 752 (Fed. Cir.
`
`2016). Micron’s claim differentiation case law is similarly unpersuasive: nothing in the
`
`specification limits “data integrity test” to a test performed after a write, so Vervain’s claim
`
`differentiation argument does not broaden the claims beyond their meaning in light of the
`
`specification.
`
`Finally, Micron’s proposal to replace “test” with “testing” does not make grammatical
`
`sense in the context of the claims. Where the claim refers to “fails a data integrity test,” it would
`
`not make sense to interpret this as “fails a testing data for errors.”
`
`5
`
`Micron Ex. 1067, p. 11
`Micron v. Vervain
`IPR2021-01549
`
`

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`Case 6:21-cv-00487-ADA Document 33 Filed 01/03/22 Page 12 of 23
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`
`
`D.
`
`“comparing the stored data to the retained data in the random access volatile
`memory” (300:1, 12)
`
`Vervain
`Plain and ordinary
`meaning
`
`WD
`Micron
`comparing the data obtained by reading the nonvolatile memory space
`to the data retained as part of a Write access operation, wherein both
`sets of the data are in the same random access volatile memory
`
`In their Reply Brief, Defendants mischaracterize Vervain’s positions and shift their own.
`
`First, Defendants claim that the parties agree on “what is compared and how it is compared.” Dkt.
`
`31, 10-11. But this is not true. In its Responsive Brief, Vervain stated:
`
`There is no reason to replace “stored data” with “data obtained by reading the
`nonvolatile memory space,” when they are not the same thing. Similarly, there is
`no reason to replace “retained data” with “data retained as part of a Write access
`operation. There is no such limitation in the claim.
`
`Dkt. 29, 21. Defendants never address these two glaring faults with their proposed construction.
`
`Instead Defendants paint a misleading picture that the parties are in agreement with these portions
`
`of their construction. The fact that Defendants’ construction misrepresents what the “stored data”
`
`and “retained data” are – is reason enough to reject Defendants’ proposed construction.
`
`Next, Defendants claim that Vervain does not dispute how data is compared, and that it
`
`excludes bit error tests such as those in Oribe reference. Dkt. 31, 10-11. Again this is not true. In
`
`its Responsive Brief, Vervain stated: “the memory in the controller can take on many different
`
`forms, and the controller can perform the comparison many different ways.” Dkt. 29, 23; Dkt. 29-
`
`2, ¶ 100. Vervain also explained that the test in Oribe was “not used to transfer data to new
`
`addresses,” and it has “no bearing on the meaning of this term.” Dkt. 29, 24. Thus, Vervain never
`
`agreed with Defendants on this point, and there is no basis for Defendants’ misstatement.
`
`Finally, Defendants misrepresent the prosecution history, and allege disavowal where
`
`there was none. In their Reply Brief, Defendants only cite the final office action response. This
`
`response does not, however, support Defendants’ construction. When describing the claims,
`
`6
`
`Micron Ex. 1067, p. 12
`Micron v. Vervain
`IPR2021-01549
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`

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`Case 6:21-cv-00487-ADA Document 33 Filed 01/03/22 Page 13 of 23
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`
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`Applicant distinguished the prior art on the basis that it did not compare stored data to retained
`
`data. Dkt. 28-18, 9-10. Applicant never said that both sets of data are in the same random access
`
`volatile memory (RAM). In fact, that would be impossible because the claim says that the stored
`
`data is in the MLC. Dkt. 29-5, 7:61-62 (“stored data in the MLC nonvolatile memory element”).
`
`Applicant also never said where or how the comparison is performed.
`
`The prior art Oribe does not compare stored data to data that is retained in a RAM. Instead,
`
`Oribe reads a single data object, and determines how many errors there are. Ex. 25, [0053].
`
`Because Oribe deals with a single data object, and therefore does not perform any comparison,
`
`there was no reason for Applicant to distinguish Oribe on the additional basis that the comparison
`
`be performed in a particular location. Id.
`
`Defendants’ Reply Brief makes much ado about the reference to “two blocks of memory
`
`space.” Dkt. 31, 7. But this reference never says the comparison has to occur in the RAM, as
`
`Defendants claim. It also never says that the “read data” (the “stored data” that is used for
`
`comparison) has to be stored in the RAM. And there was no reason to limit the claim to doing so.
`
`Because Oribe didn’t even perform a comparison, any comparison of stored data to retained data
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`would have been patentable over Oribe.
`
`It is not surprising then that the claims are silent about the location and method of
`
`performing the comparison. As stated above, the memory in the controller can take on many
`
`different forms, and the controller can perform the comparison many different ways. In fact, in
`
`the preferred embodiment, the retained data is read from the RAM into memory within the device
`
`controller in order to perform the comparison. Dkt. 29-5, 6:20-21, 6:33-35. Since the controller
`
`is using its own memory to perform the comparison, the controller would read the stored data
`
`directly into its own memory, not the RAM. Dkt. 29-2, ¶ 100.
`
`7
`
`Micron Ex. 1067, p. 13
`Micron v. Vervain
`IPR2021-01549
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`

`

`Case 6:21-cv-00487-ADA Document 33 Filed 01/03/22 Page 14 of 23
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`
`
`E.
`
`“to achieve enhanced endurance” (300:1, 12)
`
`Vervain
`Plain and
`ordinary meaning
`
`Micron
`Plain and ordinary meaning, which is “to achieve endurance (i.e.,
`lifetime) superior to that of the MLC nonvolatile memory element”
`
`WD
`
`
`Micron’s argument is based on the incorrect premise that endurance must be limited to the
`
`number of write/erase cycles that a particular cell can withstand. Dkt. 31, 12. What Micron fails
`
`to realize is that the 300 patent uses the term “endurance,” as it is commonly used in the art, to
`
`refer to the lifetime of both the individual cells and the flash memory system. This claim term is
`
`referring to the latter. When this claim term is properly viewed in this context, Micron’s argument
`
`unravels.
`
`The specification mentions that SLC has a higher endurance and can withstand between
`
`50,000 and 100,000 writes, while MLC has a lower endurance and can withstand between 3,000
`
`and 10,000 writes. Dkt. 29-5, 3:44-50. But then, two paragraphs later, the specification refers to
`
`the endurance of the flash memory:
`
`When a non-volatile storage system combines HDD, SLC and MLC (setting aside
`volatile memory for buffering, caching, etc) in a single (hybrid) system, new
`improvements and solutions are required to manage the methods of writing data
`optimally for improved life time (endurance) of flash memory. Accordingly,
`various embodiments of a NAND flash storage system that provide long lifetime
`(endurance) storage at low cost are described herein.
`
`Id., 3:62-4:2 (emphases added). And three paragraphs earlier, the patent states that wear-leveling
`
`can be used to prolong the service life of the flash memory. Id., 3:27-28. Thus, the specification
`
`equates service life with the endurance of the flash memory, id., 3:62-4:2, and the invention is
`
`concerned with enhancing the endurance of the flash memory, not the individual cells.
`
`Micron relies on the testimony of Mr. McAlexander to argue that the term “endurance”
`
`refers to the lifetime of the cells. But Mr. McAlexander never goes so far as to say that the term
`
`cannot refer to the lifetime of the flash memory. This is because the plain meaning of the term
`
`8
`
`Micron Ex. 1067, p. 14
`Micron v. Vervain
`IPR2021-01549
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`

`

`Case 6:21-cv-00487-ADA Document 33 Filed 01/03/22 Page 15 of 23
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`
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`encompasses both the lifetime of the cells and the flash memory system. In fact, during
`
`prosecution, the primary prior art reference Gorobets used the term “endurance” to refer to both.
`
`Ex. 26, [0155].3 And Exhibit 10 to Defendants’ Opening Brief describes how wear-leveling is
`
`used “[t]o enhance the endurance of flash memory.” Dkt. 28-11, 8. This is why Dr. Khatri
`
`explained in his declaration that a POSA would readily know that the endurance of a MLC cell is
`
`much smaller than the endurance of a flash memory system, and that the latter is the endurance of
`
`interest. Dkt. 29-2, ¶ 109.
`
`Micron’s reliance on Curtiss-Wright cannot overcome the fact that Applicant chose to not
`
`limit the claims to transferring data from MLC to SLC. In Curtiss-Wright, the Federal Circuit
`
`determined that reading the term “adjustable” more narrowly did not render the other independent
`
`claims superfluous. 438 F.3d 1374, 1381. Here, Defendants attempt to limit the transfer from
`
`MLC to SLC, which would render the language in the other independent claims superfluous.
`
`Additionally, the Federal Circuit was concerned that the district court’s construction was contrary
`
`to the specification. Id. Here, Vervain’s construction is consistent with the specification, which
`
`says that wear-leveling can be used to prolong the service life of the flash memory. Dkt. 29-5,
`
`3:27-28.
`
`Micron’s argument that the 300 patent says wear-leveling prolongs the “service life” (as
`
`opposed to “endurance”) of the flash memory is a distinction without a difference. The patent uses
`
`the words lifetime and endurance interchangeably, literally using the words “lifetime (endurance).”
`
`Id., 3:43-44, 3:45, 3:48, 3:66, 4:1, 5:18. Nonetheless, Micron asserts without any citation or
`
`
`3 Additionally, Defendants’ own documents refer to the “endurance” of the flash memory system.
`See, e.g., Dkt. 1-22, 3 (“long-term drive endurance”), 5 (“Drive Enduance,” “more NAND
`endurance,” “best product endurance that Micron has ever offered on a client SSD to date”), Dkt.
`29-8, 3 (“long-term data endurance).
`
`9
`
`Micron Ex. 1067, p. 15
`Micron v. Vervain
`IPR2021-01549
`
`

`

`Case 6:21-cv-00487-ADA Document 33 Filed 01/03/22 Page 16 of 23
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`
`
`authority that they are different concepts. Dkt. 31, 13. Defendants’ own Exhibit 10 exposes this
`
`bald assertion as fiction. It states unequivocally that “[t]o enhance the endurance of flash
`
`memory, many flash file systems adopt a special software technique called wear-leveling.” Dkt.
`
`28-11, 8. This sentence confirms that when the 300 patent says the wear-leveling “prolongs the
`
`service life,” it is saying it “enhances the endurance” of the flash memory system.
`
`Vervain’s tire analogy further demonstrates why Vervain is correct, and Micron is wrong.
`
`When you purchase a new set of tires, each of the tires may have a rating for 30,000 miles. But if
`
`the front right tear gets more wear than the rest, then the set of tires is not going to last as long as
`
`when the tires are rotated. By rotating the tires (leveling the wear), it is possible to increase the
`
`endurance (lifetime) of all four tires. The same is true in the 300 patent. When data is transferred
`
`from heavily-used MLC to lightly-used MLC, it “enhances the endurance” of the flash memory.
`
` THE NOT INDEFINITE TERMS
`
`For each of the following terms, Defendants have not met their burden of proving by clear
`
`and convincing evidence that the term is indefinite.
`
`A.
`
`“the list of logical address ranges having a minimum quanta of addresses”
`(298:1; 385:1; 240:1, 6)
`
`Vervain
`Plain and ordinary meaning
`
`
`
`Micron
`
`WD
`
`Indefinite
`
`Defendants’ Reply Brief confirms that WD misapplied the law in the Opening Brief. WD
`
`now concedes that (1) there is nothing inherently wrong with the word “minimum”; (2) the words
`
`“minimum quanta of addresses” are understandable; and (3) a POSA would understand that there
`
`is a “quanta of addresses” associated with a block or a page. Dkt. 31-14. Nonethel