Reply Declaration of Dr. David Liu
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`
`UNITED STATES PATENT AND TRADEMARK OFFICE
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`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`
`
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`
`
`MICRON TECHNOLOGY, INC.,
`Petitioner,
`
`v.
`
`VERVAIN, LLC,
`Patent Owner.
`
`____________________________
`Case No.: IPR2021-01549
`U.S. Patent No. 9,997,240
`Original Issue Date: June 12, 2018
`
`Title: LIFETIME MIXED LEVEL NON-VOLATILE MEMORY SYSTEM
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`
`
`REPLY DECLARATION OF DR. DAVID LIU
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`1
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`Micron Ex. 1057, p. 1
`Micron v. Vervain
`IPR2021-01549
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`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`
`
`
`
`
`MICRON TECHNOLOGY, INC.,
`Petitioner,
`
`v.
`
`VERVAIN, LLC,
`Patent Owner.
`
`____________________________
`Case No.: IPR2021-01549
`U.S. Patent No. 9,997,240
`Original Issue Date: June 12, 2018
`
`Title: LIFETIME MIXED LEVEL NON-VOLATILE MEMORY SYSTEM
`
`
`
`REPLY DECLARATION OF DR. DAVID LIU
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`1
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`Micron Ex. 1057, p. 1
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`Reply Declaration of Dr. David Liu
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`TABLE OF CONTENTS
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`I.
`II.
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`Page
`INTRODUCTION .......................................................................................... 3
`EDUCATION BACKGROUND, PROFESSIONAL EXPERIENCE,
`AND OTHER QUALIFICATIONS ............................................................... 3
`III. ASSIGNMENT AND MATERIALS CONSIDERED .................................. 4
`IV. UNDERSTANDING OF THE LAW ............................................................. 5
`V.
`LEVEL OF SKILL IN THE ART .................................................................. 5
`VI.
`THE 240 PATENT’S EFFECTIVE FILING DATE ..................................... 5
`VII. PATENT OWNER’S CONSTRUCTION OF “BLOCKS” AS BEING
`ONLY “PHYSICAL BLOCKS” IS INCONSISTENT WITH HOW A
`POSA WOULD HAVE UNDERSTOOD THE TERM ................................. 6
`VIII. DUSIJA AND SUTARDJA DISCLOSE OR RENDER OBVIOUS
`LIMITATION [1.F] ........................................................................................ 9
`SUTARDJA DISCLOSES OR RENDERS OBVIOUS LIMITATION
`[1.G] .............................................................................................................. 17
`DUSIJA IN VIEW OF SUTARDJA AND CHIN RENDERS
`OBVIOUS CLAIMS 1-2 AND 6-7 .............................................................. 21
`XI. DECLARATION .......................................................................................... 23
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`IX.
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`X.
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`2
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`I, David Liu, declare as follows:
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`I.
`
`INTRODUCTION
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`Reply Declaration of Dr. David Liu
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`1.
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`I have been retained by Micron Technology, Inc. (“Micron”) as an
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`independent expert consultant in this proceeding before the United States Patent
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`and Trademark Office (“PTO”). I am not an employee of Micron or any affiliate
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`or subsidiary of Micron.
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`2. My opinions and the bases for my opinions are set forth below.
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`3.
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`I am being compensated at $550 per hour for my work, plus
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`reimbursement for any reasonable expenses. My compensation is based solely on
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`the amount of time that I devote to activity related to this case and is in no way
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`contingent on the nature of my findings, the presentation of my findings in
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`testimony, or the outcome of this or any other proceeding. I have no other
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`financial interest in this proceeding.
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`II. EDUCATION BACKGROUND, PROFESSIONAL EXPERIENCE,
`AND OTHER QUALIFICATIONS
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`4. My education, background, and professional qualifications are set
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`forth in Paragraphs 5-14 of the previous declaration that was submitted in
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`connection with this proceeding (which I understand has been designated as
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`Exhibit 1009). My CV is included as Exhibit 1058.
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`III. ASSIGNMENT AND MATERIALS CONSIDERED
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`Reply Declaration of Dr. David Liu
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`5.
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`I have been asked to provide some additional opinions and elaboration
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`regarding the state of the art and what one of ordinary skill in the art would have
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`known as of the effective filing date of the 240 patent.
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`6.
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`I reserve the right to amend and supplement this declaration in light of
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`additional evidence, arguments, or testimony presented during this IPR or related
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`proceedings on the 240 patent.
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`7.
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`In forming the opinions set forth in this declaration, I have considered
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`and relied upon my education, knowledge of the relevant field, knowledge of
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`scientific and engineering principles, and my experience. To the extent applicable
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`to the opinions I render here, I have also reviewed and considered Patent Owner’s
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`Response in this proceeding, the materials listed in my prior declaration (Exhibit
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`1009), along with the following additional materials:
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`Exhibit
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`Description
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`1001
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`1059
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`1061
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`1062
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`1064
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`U.S. Patent No. 8,891,298 (the “298 patent”)
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`Deposition Transcript of Sunil Khatri (September 1, 2022)
`[IPR2021-01547, -01548 and -01549]
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`U.S. Patent No. 8,130,554 (“Linnell”)
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`U.S. Patent No. 7,917,709 (“Gorobets III”)
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`Byung-Woo Nam, Gap-Joo Na, and Sang-Won Lee, “A Hybrid
`Flash Memory SSD Scheme for Enterprise Database
`Applications”
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`4
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`Exhibit
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`Description
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`Reply Declaration of Dr. David Liu
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`1065
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`1066
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`2014
`
`Yuan-Hao Chang, Jen-Wei Hsieh, Tei-Wei Kuo, “Improving
`Flash Wear-Leveling by Proactively Moving Static Data”
`
`Muthukumar Murugan, “Rejuvinator: A Static Wear Leveling
`Algorithm for NAND Flash Memory with Minimized Overhead”
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`Declaration of Sunil Khatri in Support of Patent Owner’s
`Response in IPR 2021-01549
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`IV. UNDERSTANDING OF THE LAW
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`8.
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`Paragraphs 19-34 of my prior declaration (Ex. 1009) included a
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`section discussing my understanding of the law. I am not an attorney, but I have
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`been instructed in and applied the law as described in my prior declaration.
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`V. LEVEL OF SKILL IN THE ART
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`9.
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`Paragraphs 35-38 of my prior declaration (Ex. 1009) include my
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`understanding of the level of skill in the art. I understand that Patent Owner
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`adopted Petitioner’s definition of the level of skill in the art. I have applied the
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`same definition of an ordinarily skilled artisan here.
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`VI. THE 240 PATENT’S EFFECTIVE FILING DATE
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`10. As in my prior declaration, my opinions in this declaration are formed
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`from the perspective of a person of ordinary skill in the art as of July 19, 2011,
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`including both the knowledge of a person of ordinary skill in the art at that time as
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`well as how a person of ordinary skill in the art would understand the prior art.
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`VII. PATENT OWNER’S CONSTRUCTION OF “BLOCKS” AS BEING
`ONLY “PHYSICAL BLOCKS” IS INCONSISTENT WITH HOW A
`POSA WOULD HAVE UNDERSTOOD THE TERM
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`11.
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`I understand that Patent Owner has taken the position that the claim
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`term “blocks” means only physical blocks and does not include logical blocks
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`within its scope.
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`12. As an initial matter, I disagree that, in the context of the 240 patent, a
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`POSA would have understood “blocks” to refer only to physical blocks. Instead,
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`the term would have been understood to include both logical and physical blocks.
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`13.
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`I begin by noting that the surrounding claim language confirms that
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`the claim term “blocks” includes logical blocks within its scope. At a high level, a
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`“block” in flash memory can exist in two forms: the physical form, which was
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`known as a “physical block,” and the logical form, which was known as a “logical
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`block.” Ex. 1009, ¶¶ 61-70. As I noted in my original declaration, an address
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`map, namely, a logical-to-physical mapping, maps the logical blocks to physical
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`blocks. Id., ¶¶ 61-70.
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`14. Claim 1 starts with “one MLC non-volatile memory module
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`comprising a plurality of individually erasable blocks.” Claim 1 contains a similar
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`limitation for SLC. Importantly, the claim then recites “maintain[ing] an address
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`map of the MLC … non-volatile memory module[].” That map comprises: 1) “a
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`list of logical address ranges accessible by a computer system, the list of logical
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`address ranges having a minimum quanta of addresses” and 2) “each entry in the
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`Reply Declaration of Dr. David Liu
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`list of logical address ranges maps to a similar range of physical addresses
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`within … the at least one MLC non-volatile memory module.” Ex. 1005, Claim 1
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`(emphasis added). Thus, a POSA would have understood this logical to physical
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`mapping to disclose the mapping of logical blocks to physical blocks. Indeed,
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`claim 2 of the related 298 patent, which depends from claim 1 with the same
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`limitation, specifies that “the minimum quanta of [logical] addresses is equal to
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`one block,” expressly incorporating in the claim language logical and physical
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`blocks. Ex. 1001, 8:10-11.
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`15. Also, the claim language would be nonsensical if “block” only meant
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`“physical block.” Claim 1 recites a process in which one must “segregate[] those
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`blocks … into the at least one SLC non-volatile memory module.” And claim 6
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`teaches the “allocat[ing]” of blocks into SLC. If “block” was restricted to physical
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`blocks, these limitations would make no sense because one cannot “segregate” or
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`“allocate” physical blocks from one memory module to another. In the context of
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`the 240 patent, which has an MLC module and a separate SLC module, segregating
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`or allocating a physical block to a different module conjures up the notion of
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`physically moving the MLC block to the different SLC module. Even if one could
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`somehow do this (it is not possible), it would not remedy the problem that the 240
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`patent is directed at solving (i.e., ensuring that hot blocks are not rendered
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`unusable much faster than other blocks). Ex. 1005, 3:9-15. Even if one were able
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`Reply Declaration of Dr. David Liu
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`to move a physical block in MLC to SLC, it would still be an MLC block with the
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`same logical address and the same write count and thus would wear out in the same
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`amount of time. Thus, I understand that Patent Owner’s expert, Dr. Khatri, has
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`opined that the “segregating” limitation refers to segregating logical blocks to the
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`SLC module by remapping the logical block from MLC to SLC. Ex. 1059, 82:20-
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`84:1. I agree with Dr. Khatri’s analysis.
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`16.
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`I understand that Patent Owner has also contended that only physical
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`blocks can be erased and, thus, the claim’s requirement that the MLC and SLC
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`modules comprise “individually erasable blocks” must only be referring to
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`physical blocks. POR, 26-29. This is incorrect. Logical blocks are individually
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`erasable by the host. Moshayedi’s claims make this clear. Claim 1 includes a
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`limitation which requires “creating a list of one or more metrics associated with the
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`erasing [of] data blocks” and “rewriting the one or more logical blocks to a
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`physical address of the non-volatile memory based on the one or more metrics.”
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`Ex. 1012 (“Moshayedi”), claim 1. Claim 2 depends from claim 1 and requires that
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`“the one or more metrics associated with erasing data blocks comprise an erase
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`count of a logical block address (LBA).” This plainly discloses the erasure of
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`logical blocks.
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`Reply Declaration of Dr. David Liu
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`17.
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`I understand that Patent Owner’s expert, Dr. Khatri, has admitted that
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`logical blocks can be erased. Ex. 1059, 168:19-169:18. I agree. It was well-
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`known that logical blocks could be erased. Ex. 1061 (“Linnell”), 3:54-4:2
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`(“delet[ing]” a “logical block”), 6:63-7:8 (describing a “secure erase technique”
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`that “supports erasure of logical data blocks in at least NAND flash based
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`memory”). As Linnell explains, when a host would erase a logical block, one
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`technique was to mark the corresponding physical block invalid. Id., 7:9-19. As
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`Linnell demonstrates, secure erasure techniques were known such that erasing a
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`logical block would cause erasure of the physical block as well. Id., 7:48-67. Put
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`another way, it was well known for the host to issue erase commands for the
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`logical units, such as logical blocks, and then a corresponding operation to erase
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`the physical unit occurs (either immediately, see above, or at some point “later”).
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`Ex. 1062, 2:10-34 (“The host can issue a sector erase command to erase the logical
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`sector in the memory in order to delete all the sector data.”). Thus, Patent Owner’s
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`contention that it wasn’t possible to erase logical blocks is wholly false.
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`VIII. DUSIJA AND SUTARDJA DISCLOSE OR RENDER OBVIOUS
`LIMITATION [1.F]
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`18.
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`I understand that Patent Owner has argued that Sutardja’s
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`“measurements of logical address write frequencies” cannot disclose limitation
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`[1.F] because this limitation requires counting accesses to physical blocks, not
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`logical addresses (logical blocks). POR, 34-39. I disagree. As I opined above, the
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`claim term “blocks” would not have been understood to mean only “physical
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`Reply Declaration of Dr. David Liu
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`blocks.” ¶¶ 11-17, supra. Instead, the claim term “blocks” would have been
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`understood to include both logical blocks and physical blocks within its scope. Id.
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`As I described in my original declaration, as part of Sutardja’s write redirection
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`process, Sutardja can “receive[] write frequencies for logical addresses where data
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`is to be written from the host.” Ex. 1009, ¶ 158 (citing Sutardja, [0146]). And
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`Sutardja discloses “determin[ing] how frequently data is written to each of the
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`logical addresses.” Id., ¶ 158 (citing Sutardja, [0112]-[0113]). In other words,
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`Sutardja discloses counting accesses (writes) to logical addresses. A POSA would
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`have understood that counting writes to logical addresses is the counting of
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`accesses to blocks, namely, logical blocks. As I noted in my original declaration,
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`logical addresses are those that are used by the higher-level system to write data to
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`physical addresses in memory. Id., ¶ 62. An LBA (“logical block address”),
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`which a host uses to write data, is a “block” of logical addresses that corresponds
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`to a “block” of physical addresses. Id., 26 n.1. Sutardja’s system includes this
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`logical-to-physical mapping. Ex. 1011 (“Sutardja”), [0011]. For this reason,
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`Sutardja’s disclosure about counting writes to logical addresses would have been
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`understood to refer to the counting of writes to LBAs, i.e., logical blocks.
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`19.
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`I also note that Sutardja discloses counting accesses to physical
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`blocks, thereby satisfying the claim limitation even under Patent Owner’s
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`10
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`construction of “blocks.” My original declaration cited to paragraph [0111] of
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`Reply Declaration of Dr. David Liu
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`Sutardja. Ex. 1009, ¶ 158 (citing Sutardja, [0111]). I understand that Patent
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`Owner’s expert, Dr. Khatri, has stated that he understands that paragraph [0111] of
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`Sutardja discloses counting accesses to physical blocks. Ex. 1059, 112:20-115:6. I
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`agree with him. I also cited Sutardja at paragraph [0121], which likewise discloses
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`that the “wear leveling module” tracks physical erases and write counts for each
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`block. Sutardja, [0121]. Ex. 1009, ¶ 158 (citing Sutardja, [0121]).
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`20.
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` Dusija also discloses a count of erase/program cycles on physical
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`blocks. Dusija teaches that “the age of the memory device is determined by a hot
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`count maintained with each erase block of memory cells.” Ex. 1009, ¶ 157
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`(Ex. 1010 (“Dusija”), [0153]). A POSA would have understood that Dusija’s erase
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`blocks are physical blocks. For example, when discussing these “erase blocks,”
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`Dusija teaches that, in order to erase the “erase block,” it must be emptied of
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`charge whereas programming the block comprises adding a desired amount of
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`charge to the erase block. Dusija, [0077]. This aligns with the discussion of
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`physical blocks in my original declaration, wherein physical flash cells, unlike
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`logical blocks, may be programmed by physically adding a voltage pulse to the
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`control gate. Ex. 1009, ¶¶ 47-50.
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`21.
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`I understand that Patent Owner argues that “[t]he Petition presents no
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`evidence for why a system that determines how frequently data is written to each
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`of the logical addresses can meet a limitation that requires determining which
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`Reply Declaration of Dr. David Liu
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`blocks are accessed most frequently. Furthermore, the Petition presents no
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`evidence for why it would have been obvious to modify Sutardja to do so.” POR,
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`36-37. In my opinion, Sutardja expressly discloses that its techniques for moving
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`blocks between the first memory (MLC) and second memory (SLC) are applicable
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`to using either a count of logical accesses or a count of physical accesses. In other
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`words, no modification is necessary. Sutardja discloses that its wear leveling
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`module controls the mapping of logical blocks to physical blocks. Sutardja,
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`[0109]. Sutardja discloses that the wear leveling module may use a count of
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`physical accesses to “bias” (direct) logical blocks to the second memory. Id.,
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`[0128] (using physical count). Sutardja also discloses that the wear leveling
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`module may use a count of logical accesses to “bias” (direct) logical blocks to the
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`second memory. Id., [0129]-[0130] (using logical count). Thus, Sutardja’s wear
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`levelling module may direct logical blocks to the second memory (i.e., SLC) using
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`either count. Sutardja’s claims confirm this functionality. In claim 1, Sutardja
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`discloses “map[ping] logical addresses to physical addresses of one of said first
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`and second NVS memories.” Dependent claim 8, which depends on claim 1,
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`specifies that the system may track accesses to logical addresses and bias
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`frequently written logical addresses (logical blocks) to SLC. Dependent claim 13,
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`which depends on claim 1, adds that the system may track accesses to physical
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`addresses and perform the same biasing. Clearly, Sutardja discloses that its
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`Reply Declaration of Dr. David Liu
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`techniques which use a count may use either a logical count or a physical count.
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`22.
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`I understand that Patent Owner argues that none of the Petition’s
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`“cited paragraphs” discloses that Sutardja determines which blocks are most
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`frequently written on the theory that Sutardja operates on a single block. I
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`understand that the Petition cites to Sutardja, [0146]-[0147]. These paragraphs
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`describe a process in which “[c]ontrol measures actual write frequencies at which
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`data is in fact written to the logical addresses.” Id., [0147]. Note that Sutardja
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`refers to logical addresses in the plural. This is referring to tracking multiple
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`logical blocks (LBAs). ¶ 18, supra.
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`23. Similarly, I understand that Patent Owner argues that Dusija only
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`discloses an “erase count” for a single block. POR, 39. I disagree. First, Dusija
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`notes that the hot count is “maintained with each erase block of memory cells.”
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`Dusija, [0153] (emphasis added). Second, a POSA would have understood that it
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`makes no sense to count a single block in Dusija’s system. There are many blocks
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`in such a system, and wear leveling techniques apply to all (or most)1 blocks.
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`Indeed, Dusija discloses using its “hot count” to determine “the age of the memory
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`device.” Id. Here, tracking a single block would not indicate the age of the device
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`1 Special blocks, e.g., that store data that does not change, may not be subject to
`wear leveling techniques.
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`as Dusija desires, because it would only indicate the age of that particular block
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`Reply Declaration of Dr. David Liu
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`being counted. The only way to track the age of the entire memory device is to
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`track the “hot count” of each memory block, just as Dusija discloses.
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`24.
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`I understand that PO has also argued that Sutardja’s second memory is
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`not SLC and the first memory is not MLC. POR, 41-45. I disagree. As I
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`explained in my opening declaration, Sutardja’s second memory is SLC and the
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`first memory is MLC. Ex. 1009, ¶¶ 108, 158. For example, Sutardja discloses a
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`combined (“hybrid”) system with a first and second NVS memory in which the
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`second NVS memory has a greater lifetime, is more expensive, and is faster than
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`the first NVS memory. Sutardja, [0019], [0106], [0114], [0145]. These were
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`known benefits of MLC and SLC. Ex. 1009, ¶¶ 79-80. In my original declaration,
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`I noted that a POSA would have understood that SLC (i.e., the second NVS
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`memory) is faster, more durable, and has a longer lifetime than MLC (i.e., the first
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`NVS memory). Id. At the same time, MLC is cheaper than SLC and stores data
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`more densely. Id. Sutardja further provides an exemplary embodiment in which
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`“the first memory ha[s] a write cycle lifetime of 10,000, while the second memory
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`has a write cycle lifetime of 100,000.” Sutardja, [0161]. Again, these are known
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`hallmarks of MLC and SLC. Ex. 1009, ¶ 79 (“Conventional MLC can afford
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`roughly 10,000 erase operations in its operative lifespan while SLC affords
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`between 100,000-1,000,000 erase operations during its lifetime.”). Thus,
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`Sutardja’s descriptions of the first and second NVS memories align with a POSA’s
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`Reply Declaration of Dr. David Liu
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`understanding of MLC and SLC, respectively. Bolstering this, Sutardja’s claims
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`describe that the “second NVS memory includes single-level cell (SLC) flash
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`memory and said first NVS memory include[s] multi-level cell (MLC) flash
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`memory.” Sutardja, Claim 37. Based on these disclosures and the well-known
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`characteristics of MLC and SLC, a POSA would have understood Sutardja’s first
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`memory to be MLC and the second memory to be SLC.
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`25.
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`Indeed, Sutardja’s goals align with the well-known goals of a hybrid
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`memory system in that Sutardja is concerned with moving frequently written data
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`from the first memory (i.e., MLC) to the second memory (i.e., SLC). Ex. 1009,
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`¶¶ 80, 209-211. As I previously noted, SLC and MLC are different types of
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`memory, each with distinct advantages. ¶ 24, supra; Ex. 1009, ¶¶ 79-80 (SLC has
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`a longer lifetime with faster write speed). Thus, it was commonly known that
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`implementing a combined system that includes both MLC and SLC memory cells
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`provided the benefits associated with each type of memory. Ex. 1009, ¶ 80 (citing
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`Moshayedi, [0007]-[0008]; Ex. 1021, 3:45-58; Dusija, [0018]; Ex. 1022, [0018];
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`Ex. 1023, 1:32-42, 1:53-67). A POSA would have understood Sutardja to disclose
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`such a hybrid system with distinct MLC and SLC memories because that would
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`allow Sutardja’s “data shift” and write redirection to maximize device lifetime,
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`which was a problem Sutardja was attempting to solve. Sutardja, [0009] (“Once
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`the write cycle lifetime of the flash memory 104 has been exceeded, the controller
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`Reply Declaration of Dr. David Liu
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`102 can no longer reliably store data in the flash memory 104, and the solid-state
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`disk 100 may no longer be usable.”).
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`26.
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`I understand that Patent Owner has also argued that Sutardja’s process
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`of “normalization of the wear levels” makes the actual write lifetime irrelevant.
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`POR, 43-44. I disagree. First, I note that Sutardja’s “normalization of the wear
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`levels” is an optional feature and it is not discussed in either of Sutardja’s first or
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`second showings. For example, Sutardja notes that “[t]o achieve appropriate
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`comparisons, the erase counts can be normalized.” Sutardja, [0161] (emphasis
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`added). Thus, a POSA would not have understood this “normalization” to be
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`required. Second, contrary to Patent Owner’s assertion, this paragraph supports
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`that the “second memory” is SLC. Consistent with a POSA’s understanding, this
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`paragraph details an exemplary embodiment in which the lifetimes of the first
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`memory matches that of MLC and the second memory matches that of SLC. ¶¶
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`24-25, supra (citing Sutardja, [0161]). And Sutardja teaches that the “normalized
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`wear level” can be calculated by “divid[ing] the erase count by the total number of
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`erase counts a block in that memory is expected to be able to withstand [i.e., the
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`write cycle lifetime].” Sutardja, [0161]. In a given example, Sutardja notes that,
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`when the blocks in each memory have each been written 1,000 times, a block in
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`the first NVS memory (i.e., MLC) would have a normalization level of 1/10 (i.e.,
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`16
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`1,000/10,000) and a block the second NVS memory (i.e., SLC) would have a
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`Reply Declaration of Dr. David Liu
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`normalization level of 1/100 (i.e., 1,000/100,000). Id., [0162]. This confirms that
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`the second memory is SLC because it further proves that the write cycle lifetimes
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`of the memories match those of SLC and MLC. Id.; Ex. 1009, ¶ 79.
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`IX. SUTARDJA DISCLOSES OR RENDERS OBVIOUS LIMITATION
`[1.G]
`
`27. Patent Owner appears to argue that Sutardja does not disclose
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`limitation [1.G] because the Petition cites paragraphs [0149] and [0167]. POR, 47-
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`50. I also cite these paragraphs in my original declaration. Ex. 1009, ¶¶ 170. I
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`disagree for the following reasons.
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`28. First, I will reiterate some facts about flash architecture for context.
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`As I noted in my previous declaration, flash memory is organized into different
`
`units, such as “blocks,” “pages,” and/or “sectors.” Ex. 1009, ¶ 52. A block is the
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`smallest erasable unit and, thus, an erase operation must occur on the entire block.
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`Id. A page is the smallest writable unit and a block is made up of multiple pages.
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`Id.; Ex. 1019, 3. When writing to a page, the data in the other pages in the block
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`(or lack thereof) are not altered. Thus, when writing to a page, existing data in the
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`other pages does not change.
`
`29.
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`I likewise described in my previous declaration the well-known
`
`process of wear-leveling and the benefits associated therewith. Ex. 1009, ¶¶ 71-74.
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`“Dynamic wear leveling” is a process wherein the flash device “remaps” (i.e.,
`
`17
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`updates the logical to physical mapping for) incoming data to a block with lower
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`Reply Declaration of Dr. David Liu
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`wear. Id., ¶ 72. Thus, rather than writing to a physical block with a high wear
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`level, the incoming write may be remapped to an already-erased block with a lower
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`wear level. Id. Through this method, a flash device can select blocks with
`
`relatively low wear for incoming writes. Id. It was known that these
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`“redirections” could occur between MLC and SLC. As I noted before, a POSA
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`would have been motivated to direct incoming writes to SLC for blocks with high
`
`wear count and MLC for blocks with low wear count based on the lifetimes due to
`
`the characteristics of both types of memories. Id., ¶¶ 79-80. “Static wear leveling”
`
`was a similarly well-known process but involved the transfer of data that already
`
`existed in the block. Id., ¶ 73.
`
`30. Both wear leveling techniques rely on the availability of free sectors
`
`that can be filled up with new data. Ex. 1019, 41. Since data may be written in
`
`pages, but can only be erased in blocks, it was important to ensure that all data in
`
`an old block was moved to another location prior to erasure to prevent the erasure
`
`of valid data. Id.; Ex. 1064, 1 (“However, when updating a page in the block, all
`
`valid pages of the corresponding block must be copied to the free block.”), 4
`
`(describing a “block merge” process wherein “valid pages in [an] original data
`
`block” may be transferred to a new block so that the original data block may be
`
`erased); Ex. 1065, 5 (“before a block is erased, data of any valid pages in the block
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`18
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`must be copied to the other free pages”); Ex. 1066, 2-3 (describing “cop[ying]”
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`Reply Declaration of Dr. David Liu
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`“valid pages” to a new block before reclaiming a block); Ex. 1046, 7:54-66
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`(describing the remapping and moving of data to a new block so that the old block
`
`can be “reclaimed”). To invalidate a memory block, the controller selects a free
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`memory block, moves the data to that free memory block, and marks the original
`
`block as invalid. Ex. 1019, 41; Ex. 1064, 1, 4; Ex. 1065, 5; Ex. 1066, 2-3;
`
`Ex. 1046, 7:54-66. In a similar process known as “garbage collection,” blocks
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`containing invalid sectors would be selected and the portions of those blocks that
`
`contain valid sectors would be copied into free sectors of other blocks. Ex. 1019,
`
`41-42. After this, the whole block would be erased. Id. Garbage collection is
`
`typically performed as a background operation but can be performed during write
`
`operations. Id. Either process required valid data to be moved prior to erasure.
`
`31. Contrary to Patent Owner’s assertions, my declaration showed that
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`Sutardja discloses limitation [1.G]. Ex. 1009, ¶¶ 164-192; POR, 47-52. For
`
`context, Sutardja’s “data shift” is exemplary of the teachings I discussed above
`
`concerning the moving of data, block reclamation, and garbage collection. ¶¶ 28-
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`30, supra. In Sutardja’s “data shift,” the control module determines if a number of
`
`write operations to a block in MLC is greater than or equal to a predetermined
`
`threshold. Sutardja, [0149]. If it is, control “maps the logical addresses that
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`correspond to the first block [in MLC] to a second block [in SLC].” Id.
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`19
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`Reply Declaration of Dr. David Liu
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`32. First, a POSA would have understood the data in MLC to be
`
`transferred to SLC along with the logical address because, if it was not transferred,
`
`the logical address would point to the wrong data. If the valid data in MLC was
`
`not transferred to SLC as part of this operation, after the logical address was
`
`remapped to SLC, subsequent commands to those logical blocks seeking that data
`
`would draw errors because the device would not be able to locate it. ¶ 30, supra;
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`Ex. 1064, 1, 4; Ex. 1065, 5; Ex. 1066, 2-3; Ex. 1046, 7:54-66.
`
`33. Second, as I discussed above, a POSA would have understood the
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`data in the MLC block to be transferred to SLC as part of this process because it
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`would be required to transfer the valid data to SLC so that the MLC block could be
`
`erased and reclaimed through garbage collection. Supra, ¶¶ 27-30, supra. Upon
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`transferring the block to SLC, every page in the MLC block would be transferred
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`to SLC after which the MLC block would be marked invalid and, subsequently,
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`erased and reclaimed as a free block during garbage collection. Id.
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`34.
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`I understand that Patent Owner has claimed that Sutardja’s “data
`
`shift” and “wear level analysis” are disparate teachings. POR, 47-50. I disagree.
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`In my opinion, Patent Owner misunderstands Sutardja’s disclosure. Sutardja’s
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`paragraph [0167] merely provides context on what must happen after remapping
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`an address (i.e. after remapping the logical address to an SLC block, any valid data
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`must be transferred to the SLC block, which I describe above). Thus, paragraph
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`20
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`[0167] provides context for Sutardja’s “data shift” disclosure, namely, that
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`Reply Declaration of Dr. David Liu
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`remapping of the logical addresses from MLC to SLC may involve the swapping
`
`of data in those blocks. It “may” involve swapping because the swap is only
`
`necessary if valid data remains in the original MLC block (which is common). I
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`opined about this process above and noted that it was commonly known to keep
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`data as part of the same block or else (1) the logical pointer would point at
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`incorrect data and (2) garbage collection could potentially erase valid data that was
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`part of the old block. ¶¶ 27-33, supra; Ex. 1061, 1, 4; Ex. 1066, 2-3, Ex. 1065, 5;
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`Ex. 1046, 7:54-66.
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`35.
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`I understand that Patent Owner asserts that I did not explain the basis
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`for why a collective count falls within the claim scope. POR, 51. I disagree. See,
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`e.g., Ex. 1009, ¶ 175. I also note that the claim refers to “a count,” “the count,”
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`and multiple “blocks,” which suggests that a single count is within the claim scope.
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`X. DUSIJA IN VIEW OF SUTARDJA AND CHIN RENDERS OBVIOUS
`CLAIMS 1-2 AND 6-7
`
`36.
`
`I understand that Patent Owner has argued that Chin does not provide
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`any additional evidence for why claim 1 should be understood to cover a collective
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`count. POR, 51. I disagree. As I opined in my original declaration
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