`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`_____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`_____________
`
`MICRON TECHNOLOGY, INC.,
`Petitioner
`
`v.
`
`VERVAIN, LLC,
`Patent Owner
`_____________
`
`Case: IPR2021-01549
`U.S. Patent No. 9,997,240
`_____________
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`
`
`PATENT OWNER’S RESPONSE
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`

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`IPR2021-01549
` U.S. Patent No. 9,997,240
`
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`TABLE OF CONTENTS
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`I.
`
`II.
`
`INTRODUCTION ........................................................................................... 1
`
`OVERVIEW OF THE ’240 PATENT AND THE CHALLENGED
`CLAIMS .......................................................................................................... 2
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`A.
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`B.
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`C.
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`SLC AND MLC FLASH ........................................................................... 3
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`ADDRESS TABLE ..................................................................................... 5
`
`DATA INTEGRITY TESTS ......................................................................... 6
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`D. HOT AND COLD DATA ............................................................................ 6
`
`E.
`
`CLAIMS 1 AND 6 ..................................................................................... 7
`
`III.
`
`PERSON OF ORDINARY SKILL IN THE ART ........................................11
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`IV. OVERVIEW OF THE ALLEGED PRIOR ART ..........................................12
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`A. DUSIJA (EX. 1010) ................................................................................12
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`B.
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`C.
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`SUTARDJA (EX. 1011) ..........................................................................16
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`CHIN (EX. 1030) ...................................................................................21
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`V.
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`CLAIM CONSTRUCTION ..........................................................................24
`
`A.
`
`B.
`
`C.
`
`“BLOCKS” (CLAIMS 1 AND 6) ................................................................25
`
`“DATA INTEGRITY TEST” (CLAIMS 1 AND 6) ..........................................29
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`“ON A PERIODIC BASIS” (CLAIMS 1 AND 6) ............................................32
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`VI. THE CITED REFERENCES DO NOT RENDER CLAIMS 1-2 AND 6-7
`UNPATENTABLE ........................................................................................32
`
`A. DUSIJA IN VIEW OF SUTARDJA DOES NOT RENDER OBVIOUS CLAIMS 1-
`2 AND 6-7 (GROUND 1) .........................................................................33
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`
`
`DUSIJA IN VIEW OF SUTARDJA DOES NOT DISCLOSE OR SUGGEST
`LIMITATION [1.F] (GROUND 1)...................................................33
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`A) THE PETITION RELIES ON DISCLOSURES REGARDING LOGICAL
`ADDRESSES, NOT “BLOCKS” AS PROPERLY CONSTRUED .34
`
`B) THE PETITION HAS NOT ESTABLISHED THAT SUTARDJA
`DISCLOSES DETERMINING WHICH OF THE BLOCKS ARE
`ACCESSED MOST FREQUENTLY .......................................39
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`IPR2021-01549
` U.S. Patent No. 9,997,240
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`C) SUTARDJA’S DISCLOSURE OF MAPPING ADDRESSES TO THE
`SECOND NVS MEMORY DOES NOT DISCLOSE OR SUGGEST
`SEGREGATING CONTENTS OF BLOCKS TO SLC OR MLC AS
`IN LIMITATION [1.F] ........................................................41
`
`
`
`DUSIJA IN VIEW OF SUTARDJA DOES NOT DISCLOSE OR SUGGEST
`LIMITATION [1.G] (GROUND 1) ..................................................45
`
`A) THE PETITION DOES NOT ANALYZE “BLOCKS” FOR EITHER
`INTERPRETATION OF LIMITATION [1.G] UNDER THE
`PROPER CONSTRUCTION ..................................................46
`
`B) THE PETITION’S RELIANCE ON SUTARDJA’S DISCLOSURE OF
`SWAPPING DATA FOR ITS INDIVIDUAL COUNT
`INTERPRETATION OF LIMITATION [1.G] IS FLAWED .........47
`
`C) THE PETITION’S ANALYSIS FOR LIMITATION [1.G] UNDER ITS
`COLLECTIVE COUNT INTERPRETATION IS DEFICIENT .......50
`
`
`
`CLAIMS 2, 6, AND 7 (GROUND 1) ................................................52
`
`B.
`
`DUSIJA IN VIEW OF SUTARDJA AND CHIN DOES NOT RENDER OBVIOUS
`CLAIMS 1-2 AND 6-7 (GROUND 2) ........................................................52
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`VII. CONCLUSION ..............................................................................................53
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`ii
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`IPR2021-01549
` U.S. Patent No. 9,997,240
`
`
`TABLE OF AUTHORITIES
`
` Page(s)
`
`Cases
`
`Amazon Web Services, Inc. v. Saint Regis Mohawk Tribe,
`IPR2019-00103, Paper No. 22 (PTAB May 10, 2019) ...................................... 40
`
`Belden Inc. v. Berk-Tek,
`805 F.3d 1064 (Fed. Cir. 2015) .......................................................................... 44
`
`Bicon, Inc. v. Straumann Co.,
`441 F.3d 945 (Fed. Cir. 2006) ............................................................................ 30
`
`Corning Incorp. v. Danjou’s DSM IP Assets B.V.,
`Case No. IPR2013-00043, Paper No. 95 (PTAB May 1, 2014) ......................... 40
`
`DePuy Spine, Inc. v. Medtronic Sofamor Danek, Inc.,
`469 F.3d 1005 (Fed. Cir. 2006) .......................................................................... 25
`
`Hill-Rom Servs., Inc. v. Stryker Corp.,
`755 F.3d 1367 (Fed. Cir. 2014) .......................................................................... 30
`
`Innova/Pure Water, Inc. v. Safari Water Filtration Sys., Inc.,
`381 F.3d 1111 (Fed. Cir. 2004) .......................................................................... 31
`
`Merck & Co. v. Teva Pharm. USA, Inc.,
`395 F.3d 1364 (Fed. Cir. 2005) .......................................................................... 30
`
`Phillips v. AWH Corp.,
`415 F.3d 1303 (Fed. Circ. 2005) (en banc) .................................................. 24, 25
`
`Samsung SDI Co., Ltd. v. Ube Industries, Inc.,
`IPR2017-02116, Paper No. 8 (Mar. 12, 2018) ................................................... 50
`
`Toyota Motor Corp. v. Cellport Systems, Inc.,
`IPR2015-00633, Paper No. 11 (Aug. 14, 2015) ................................................. 25
`
`Vervain, LLC v. Micron Tech., Inc.,
`No. W-21-CV-00487-ADA, Dkt. 42 (W.D. Tex. Jan. 24, 2022) ................. 30, 32
`
`iii
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`

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`Statutes
`Statutes
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`35 U.S.C. § 316(€)
`ccccssesccsssesssssscccssssessssssccessssecsssusesssssesessssessssnsesessueesssssessssneessssseessse 1
`35 U.S.C. § 316(e) ..................................................................................................... 1
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`IPR2021-01549
`IPR2021-01549
`U.S. Patent No. 9,997,240
` U.S. Patent No. 9,997,240
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`
`Exhibit
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`EXHIBIT LIST
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`Description
`
`Ex. 2001 Declaration of Dr. Sunil Khatri
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`IPR2021-01549
` U.S. Patent No. 9,997,240
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`
`Previously
`Submitted
`X
`
`Ex. 2002 Chen et al., Ultra MLC Technology Introduction, Advantech
`Technical White Paper (Oct. 5, 2012) (“Chen”)
`
`Ex. 2003 Excerpts from Micheloni et al., Inside NAND Flash
`Memories (1st ed. 2010) (“Micheloni”)
`
`Ex. 2004 U.S. Patent No. 10,950,300 to G.R. Mohan Rao (“’300
`Patent”)
`
`Ex. 2005 Microsoft Computer Dictionary definition for “data
`integrity”
`
`Ex. 2006 Hargrave’s Communications Dictionary definition for “data
`integrity”
`
`Ex. 2007 https://www.law360.com/articles/1381597/albright-says-he-
`ll-very-rarely-put-cases-on-hold-for-ptab
`
`Ex. 2008 Docket Sheet for Case. No. 6:21-cv-487-ADA; Vervain v.
`Micron Technology et al.; U.S. District Court, Western
`District of Texas.
`
`Ex. 2009 Exhibit C-3, Invalidity Claim Chart for the ’240 Patent based
`on U.S. Patent Application Pub. No. 2011/0099460
`(“Dusija”)
`
`Ex. 2010 Exhibit C-18, Invalidity Claim Chart for the ’240 Patent
`based on U.S. Patent Application Pub. No. US 2008/0140918
`(“Sutardja”)
`
`Ex. 2011 Micron’s Preliminary Invalidity Contentions for U.S. Patent
`Nos. 8,891,298; 9,196,385; 9,997,240; and 10,950,300; Case.
`No. 6:21-cv-487-ADA; Vervain v. Micron Technology et al.;
`U.S. District Court, Western District of Texas.
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`X
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`X
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`X
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`X
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`X
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`X
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`X
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`v
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`Ex. 2012 Claim Construction Order in Vervain v. Micron Tech., Inc.,
`No. 6:21-cv-487-ADA (W.D. Tex.) and Vervain v. Western
`Digital Corp., No. 6:21-cv-488-ADA (W.D. Tex.) (Jan. 24,
`2022)
`
`IPR2021-01549
` U.S. Patent No. 9,997,240
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`X
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`Ex. 2013
`
`Intentionally Omitted
`
`Ex. 2014 Declaration of Dr. Sunil Khatri in Support of Patent Owner’s
`Response
`
`Ex. 2015 Transcript of June 10, 2022 Deposition of Dr. David Liu
`
`Ex. 2016 U.S. Patent No. 8,285,940
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`vi
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`IPR2021-01549
` U.S. Patent No. 9,997,240
`
`
`I.
`
`INTRODUCTION
`
`Vervain, LLC (“Patent Owner”) respectfully submits this Response to the
`
`Board’s decision to institute inter partes review (Paper No. 10, the “Decision”) and
`
`to the petition for inter partes review (Paper No. 1, the “Petition”) filed by Micron
`
`Technology, Inc. (“Petitioner”). The Board instituted review of U.S Patent No.
`
`9,997,240 (Ex. 1005, “the ’240 patent” or “the challenged patent”) on two grounds
`
`that challenge claims 1, 2, 6, and 7 (“the challenged claims”) of the ’240 patent.
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`Decision, 5, 25. Petitioner has not, however, carried its burden of proving
`
`unpatentability by a preponderance of the evidence (35 U.S.C. § 316(e)).
`
`As explained below and in the accompanying declaration of Patent Owner’s
`
`expert, Dr. Khatri, Petitioner has not established that the cited prior art discloses or
`
`suggests all of the limitations of the challenged claims.1 For example, the Petition
`
`does not analyze the claims and prior art under the proper construction of “blocks,”
`
`which the Petitioner improperly maps to teachings in the prior art regarding logical
`
`(not physical) blocks/addresses. Additionally, the Petition makes several errors in
`
`its analysis of limitations [1.F] and [1.G] of claim 1 the Dusija-Sutardja ground
`
`(Ground 1). Moreover, a person of ordinary skill in the art (POSA) would not have
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`
`1 Patent Owner submits the declaration of Dr. Khatri (Ex. 2014), an expert in the field
`
`of the ’240 patent. (Ex. 2014, ¶¶1-19.)
`
`1
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`

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`IPR2021-01549
` U.S. Patent No. 9,997,240
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`configured the system of the Dusija reference (Ex. 1010) in view of Sutardja (Ex.
`
`1011) in the manners proposed by Petitioner.
`
`Petitioner has not met its burden in this proceeding and has not established
`
`that the challenged claims are unpatentable. Accordingly, the patentability of the
`
`challenged claims should be confirmed.
`
`II. OVERVIEW OF THE ’240 PATENT AND THE CHALLENGED
`CLAIMS
`
`The ’240 Patent, entitled “Lifetime Mixed Level Non-Volatile Memory
`
`System” was filed on November 24, 2015 and has an effective filing date of July 19,
`
`2011. Ex. 1005. Dr. Mohan Rao is the sole named inventor of the ’240 Patent.
`
`At a high level, the ’240 Patent describes, among other things, a reliable flash
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`memory storage system combining both single-level cell (SLC) and multi-level cell
`
`(MLC) non-volatile memories.2 Id., Abstract; Ex. 2014, ¶¶24-39. Prior to the ’240
`
`Patent, Dr. Rao recognized that “MLC NAND flash SSDs are slowly replacing
`
`and/or coexisting with SLC NAND flash in newer SSD systems” because “MLC
`
`flash memory is less expensive than SLC flash memory[] on a cost per bit basis.”
`
`
`2 Non-volatile memories can store information even after the system is powered off.
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`Flash memory is a specific type of non-volatile memory, where data is stored in
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`“blocks” of “pages.” Ex. 1005, 2:48-65.
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`2
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`IPR2021-01549
` U.S. Patent No. 9,997,240
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`Ex. 1005, 3:32-33, 5:43-44. However, while “MLC NAND flash enjoys greater
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`density than SLC NAND flash” it comes “at the cost of a decrease in access speed
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`and lifetime (endurance).” Id., 3:37-40. As a result, various hybrid systems
`
`combining SLC and MLC (among others) have been developed to combine the
`
`benefits of both types of non-volatile flash storage at a low cost. Id., 3:63-65.
`
`The ’240 Patent addresses improvements and solutions for managing the
`
`writing of data optimally for improved reliability and lifetime (endurance) of such
`
`hybrid memory systems. Id., 3:58-65. Specifically, the Challenged Claims are
`
`directed to specific techniques for efficiently using SLC and MLC flash to improve
`
`the overall performance of the memory. Id., claims 1 and 6. For example, if certain
`
`data is used more frequently, then it is transferred to higher-performance SLC. Id.
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`By doing so, the number of errors is reduced, and overall endurance of the memory
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`is increased. Id., 3:63-65.
`
`A.
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`SLC and MLC Flash
`
`SLC memory stores 1 bit per cell, and MLC memory stores more than 1 bit
`
`per cell. Id., 2:13-16; Ex. 2014, ¶¶30-32. As noted above, there are pros and cons
`
`to SLC and MLC flash. In general, SLC is faster and less prone to errors, but
`
`requires more space and power to store a given amount of data. Ex. 1005, 1:53-58.
`
`The opposite is true of MLC. MLC flash is slower and more prone to errors, but
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`stores data more densely with less power consumption. Id., 3:37-40.
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`3
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`

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`SLC and MLC flash memories both use the same type of transistor called a
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`floating gate transistor. Id., 3:48. They both store a charge in the floating gate of
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`each transistor (cell), which changes the threshold voltage of the transistor. The
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`memory uses the threshold voltage to determine what bit, or bits, were stored in the
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`transistor. The MLC cell in the figure below illustrates threshold voltages for a 2-
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`bit MLC cell.
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`Ex. 2002, 5.
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`
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`The primary difference between SLC and MLC is what data each threshold
`
`voltage represents. With SLC flash, the transistor stores only a 1 or 0, so a wide
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`range of threshold voltages can be allotted to a single bit. This allows for faster and
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`more reliable memory access. On the other hand, MLC flash must be slowly and
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`carefully programmed to a narrower, more precise range of threshold voltages, with
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`each threshold voltage range representing a specific pair of bits (see figure above,
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`which shows four pairs of bits—11, 10, 01, and 00—corresponding to smaller ranges
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`of threshold voltages compared to the SLC). Ex. 1005, 3:35-40.
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`4
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`IPR2021-01549
` U.S. Patent No. 9,997,240
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`B. Address Table
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`To provide wear leveling, garbage collection, and bad block management, a
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`translation layer is used to map logical addresses to actual physical memory
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`locations. Ex. 2003, 9-11; Ex. 1005, 2:66-3:31; Ex. 2014, ¶33. As part of this
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`translation layer, “tables are widely used in order to map sectors and pages from
`
`logical to physical.” Ex. 2003, 9; Ex. 1005, 3:15-19. These tables map logical
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`blocks to physical blocks. Ex. 2003, 9-11; Ex. 1005, 3:15-19. Using a “block” or
`
`similar granularity is important, since flash memory is arranged so that when erasing
`
`and rewriting data, a whole block is “erased together.” Ex. 2003, 6; Ex. 1005, 2:55-
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`65. Dr. Rao explained that “[t]he address ranges within the translation table will
`
`assume some minimum quantum, such as, for example, one block…” Ex. 1005,
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`5:46-50. Dr. Rao further explained that memory is written and mapped on the
`
`granularity of a “quantum,” such as a block or page. Id., 5:46-50; FIGS. 3A-3B.
`
`During operation of the flash memory, logical addresses are frequently
`
`remapped to new physical locations. Id., 3:16-49, 4:20-24, 5:39-59. Over time, a
`
`particular logical address may be mapped or associated with many different physical
`
`locations (blocks). Ex. 2014, ¶¶33, 73-74. And multiple logical addresses may point
`
`to the same block over time, so there is not a one-to-one correspondence between
`
`the logical addresses and the blocks over time. Id.
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`5
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`

`IPR2021-01549
` U.S. Patent No. 9,997,240
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`C. Data Integrity Tests
`
`As mentioned above, when data is stored in MLC memory, it is more prone
`
`to errors than when data is stored in SLC memory. One reason for this is that the
`
`threshold voltage intervals for MLC memory are smaller than the intervals for SLC
`
`memory, and thus, errors can occur when writing or reading the data. Ex. 2014, ¶34.
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`Errors can also be caused by the data stored in neighboring cells. Id. A data integrity
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`test is a test that checks the integrity of the data (i.e., whether errors have occurred).
`
`This test can be run immediately after data is written, or at a later time. If the test
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`reveals a problem such as corrupt data, the data can be remapped to SLC (which is
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`less error-prone), and the address table is modified accordingly. Ex. 1005, 4:24-29.
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`Alternately, MLC data can be remapped to other MLC blocks, and the address table
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`is then modified accordingly. Id., 3:9-31.
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`D. Hot and Cold Data
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`One can distinguish between “hot” blocks (which receive more frequent
`
`writes), and “cold” blocks (which receive less frequent writes). Id., 6:46-52.
`
`Because SLC has greater endurance, “hot” blocks can be allocated to SLC to
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`increase the lifetime of the system. Id. “Cold” blocks, on the other hand, can be
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`allocated to MLC to take advantage of its higher density storage. Ex. 2014, ¶35.
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`As Dr. Rao explains, the contents of the “hot” blocks can be transferred to
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`SLC “on a periodic basis, such as, for example every 1000 writes or every 10,000
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`6
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`

`IPR2021-01549
` U.S. Patent No. 9,997,240
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`writes.” Ex. 1005, 6:52-58. By transferring groups of “hot” blocks on a periodic
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`basis, it allows the controller to transfer the data from MLC blocks to SLC as a
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`background process in-between write commands. Ex. 2014, ¶35.
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`E. Claims 1 and 6
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`In claim 1, the MLC and SLC comprise “erasable blocks” (highlighted red).
`
`These are the physical locations that must be erased before data can be written to
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`them. See [1.A] and [1.B] below. Meanwhile, an address map comprises a list of
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`“logical address ranges” (highlighted purple); these logical address ranges are
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`mapped to the physical address ranges for the blocks. [1.D].
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`[1.PRE] A system for storing data comprising:
`
`Claim 1
`
`[1.A]
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`at least one MLC…module comprising a plurality of individually
`
`erasable blocks;
`
`[1.B]
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`at least one SLC…module comprising a plurality of individually
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`erasable blocks; and
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`[1.C]
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`a controller coupled to the at least one MLC…module and the at least
`
`one SLC…module,
`
`[1.D]
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`the controller maintaining an address map of at least one of the MLC
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`and SLC…modules, the address map comprising a list of logical
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`address ranges accessible by a computer system, the list of logical
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`address ranges having a minimum quanta of addresses, wherein each
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`7
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`IPR2021-01549
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`entry in the list of logical address ranges maps to a similar range of
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`physical addresses within either the at least one SLC…module or
`
`within the at least one MLC…module;
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`[1.E] wherein the controller is adapted to determine if a range of addresses
`
`listed by an entry and mapped to a similar range of physical addresses
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`within the at least one MLC…module, fails a data integrity test, and, in
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`the event of such a failure, the controller remaps the entry to the next
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`available equivalent range of physical addresses within the at least one
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`SLC…module; and
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`[1.F] wherein the controller is further adapted to determine which of the
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`blocks of the plurality of the blocks in the MLC and SLC…modules
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`are accessed most frequently and wherein the controller segregates
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`those blocks that receive frequent writes into the at least one
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`SLC…module and those blocks that receive infrequent writes into the
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`at least one MLC…module, and
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`[1.G] maintain a count value of the blocks in the MLC…module determined
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`to have received frequent writes and that are accessed most frequently
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`on a periodic basis when the count value is a predetermined count
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`value, transfer the contents of the counted blocks in the MLC…module
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`determined to have received frequent writes after reaching the
`
`predetermined count value to the SLC…module and which determined
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`blocks in the SLC are determined in accordance with the next
`
`equivalent range of physical addresses determined by the controller.
`
`8
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`

`

`IPR2021-01549
` U.S. Patent No. 9,997,240
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`As can be seen above, claim 1 uses the claim terms “blocks” and “logical
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`address ranges” to refer to two different things. The blocks are the physical locations
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`in the MLC and SLC where the data is stored. [1.A-B]. Each block has a fixed
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`“range of physical addresses.” [1.D]. Meanwhile, the address map contains a list of
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`logical address ranges that are mapped to the physical address ranges. As the claim
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`indicates, the logical address ranges are remapped to new physical address ranges.
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`[1.E]. Thus, a logical address range does not permanently point to a specific physical
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`address range. Rather the corresponding physical address range may change over
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`time.
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`Turning to [1.F], the claim refers to “the blocks,” where the antecedent basis
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`is “erasable blocks” in [1.A-B]. Thus, the controller is adapted to “determine which
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`of the [erasable blocks]…are accessed most frequently.” Additionally, [1.F] recites
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`that the controller segregates blocks with “frequent writes” to SLC, and “infrequent
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`writes” to MLC.
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`Finally, in [1.G], the controller is adapted to transfer the contents of blocks
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`that receive frequent writes to SLC memory. Additionally [1.G] recites that this
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`transfer is done on a periodic basis when the count value is a predetermined count
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`value.
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`Like claim 1, claim 6 recites that the controller is adapted to determine the
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`blocks that are accessed most frequently, and more specifically, maintain a count
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`9
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`IPR2021-01549
` U.S. Patent No. 9,997,240
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`value those blocks that are accessed most frequently (see [6.G.i]). Additionally, the
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`controller is adapted to transfer the contents of those “counted blocks” to SLC
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`memory (see [6.G.ii]).
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`[6.PRE] A system for storing data comprising:
`
`Claim 6
`
`[6.A]
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`at least one MLC…module comprising a plurality of individually
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`erasable blocks;
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`[6.B]
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`at least one SLC…module comprising a plurality of individually
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`erasable blocks; and
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`[6.C]
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`a controller coupled to the at least one MLC…module and the at least
`
`one SLC…module,
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`[6.D]
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`the controller maintaining an address map of at least one of the MLC
`
`and SLC…modules, the address map comprising a list of logical
`
`address ranges accessible by a computer system, the list of logical
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`address ranges having a minimum quanta of addresses, wherein each
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`entry in the list of logical address ranges maps to a similar range of
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`physical addresses within either the at least one SLC…module or
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`within the at least one MLC…module;
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`10
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`IPR2021-01549
` U.S. Patent No. 9,997,240
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`[6.E] wherein the controller allocates those blocks that receive frequent
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`writes into the SLC…module as hot blocks and those blocks that only
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`receive infrequent writes into the MLC…module as cold blocks; and
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`[6.F] wherein the controller is adapted to determine if a range of addresses
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`listed by an entry and mapped to a similar range of physical addresses
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`within the at least one MLC…module, fails a data integrity test, and, in
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`the event of such a failure, the controller remaps the entry to the next
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`available equivalent range of physical addresses within the at least one
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`SLC…module;
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`[6.G.i] wherein the controller is further adapted to maintain a count value of
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`those blocks that are accessed most frequently and,
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`[6.G.ii] on a periodic basis when the count value is a predetermined count
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`value, transfer the contents of those counted blocks into the
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`SLC…module, wherein the counted blocks transferred to after
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`reaching the predetermined count value are determined in accordance
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`with the next equivalent range of physical addresses determined by the
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`controller.
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`III. PERSON OF ORDINARY SKILL IN THE ART
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`For purposes of this proceeding only, Patent Owner adopts Petitioner’s
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`definition of a person of ordinary skill in the art (POSA). Petition, 27; Ex. 2014,
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`¶¶20-23.
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`IV. OVERVIEW OF THE ALLEGED PRIOR ART
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`For the purposes of this Response, only Dusija, Sutardja, and Chin are relevant
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`because they are the only references asserted against independent claims 1 and 6.
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`A. Dusija (Ex. 1010)
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`Dusija addresses a problem that occurs with flash memory—as it ages, its
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`error rate increases, which requires a resource intensive ECC to correct errors. Ex.
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`1010, [0012-0017]; Ex. 2014 ¶¶53-59. As Dusija explains, in order to ensure data
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`integrity in such situations, a complex, computationally intensive ECC is utilized
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`which results in memory performance degradation. Ex. 1010, [0014]. To address
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`this problem, Dusija “provid[es] a mechanism to control and limit the errors arising
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`after writing to high density memory [i.e., MLC] … and a second chance to rewrite
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`data with less error if the copy in the high density memory has excessive errors.”
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`Id., [0024]. By using the disclosed mechanism the ECC complexity is reduced and
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`an “advantage is gained at the slight expense of an additional post-write read and
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`infrequent additional rewrites to a less [sic, lower] density memory portion [i.e.,
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`SLC].” Id.
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`In contrast to the ’240 Patent, the SLC in Dusija is primarily used for
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`enhancing memory life by starting an error management process “after the memory
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`has aged to a predetermined amount.” Id., Abstract. Hence, the primary teaching of
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`Dusija is to extend memory life when the memory is aging, and not slow it down by
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`doing the “error management … when a memory is new with little or no errors.” Id.
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`Thus, Dusija teaches a MLC memory chip where a nominal amount of SLC is
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`deployed only late in the lifetime of the MLC memory in order to avoid ECC
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`processing at the controller ASIC. Id., [0016], [0024], [0155].
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`To reduce ECC complexity and increase memory performance, Dusija
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`describes a flash memory device 90 including a controller ASIC chip 102
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`(highlighted purple) and a memory chip 100 (highlighted blue).
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`Id., FIG. 1, [0016], [0059], [0106].3 The memory array 200 is shown in more detail
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`in Figures 14A-14B, 16A-16C, and 20A-20C. Exemplary Figure 20A is reproduced
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`below.
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`Id., FIG. 20A. As seen above, the memory array 200 comprises “a first portion
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`operating with less error but of lower density storage” and a “second portion
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`3 Unless otherwise noted, Patent Owner added coloring to Figures.
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`operating with a higher density but less robust storage” (highlighted blue). Id.,
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`Abstract.
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`For the low density storage portion of the memory, Dusija discloses memory
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`referred to as “D1” which it describes as memory cells storing 1 bit of data—i.e.,
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`SLC. For the high density storage portion of the memory, Dusija discloses memory
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`referred to as “D3” which it describes as memory cells storing 3 bits of data—i.e.,
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`MLC. Id., [0025], [0028].
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`In the embodiment shown in Figure 20A, Dusija describes that input data from
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`the host is first cached in a first section 411 (highlighted yellow) of the D1 memory
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`and subsequently folded into D3 memory. Id., [0162-0163]. The D1 (SLC) memory
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`is primarily used for staging and caching incoming data from the host.
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`Further, Dusija describes “post-write-read” error management processes
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`where, when enabled, a filled D3 block is read back and compared to the data in the
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`D1 block to determine whether the error rate exceeds a predetermined threshold. Id.,
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`[0028], [0162-0163]. If so, the currently written D3 block is rejected and a retry
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`takes place with data being refolded into a new D3 block. Id. The new D3 block is
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`again read back and checked for excessive errors. Id. If the new D3 block passes,
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`then it is determined to have good data and the original data in the D1 block is made
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`obsolete. Id. If the new D3 block still shows excessive error, the process is repeated
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`for a predetermined number of retries after which time the D1 to D3 folding
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`operation is abandoned with the original data kept at D1. Id.
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`In further contrast to the ’240 Patent, as Petitioner acknowledges, Dusija does
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`not describe maintaining a write count for SLC and MLC blocks and allocating those
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`blocks that receive the most frequent write to SLC memory. This is not surprising
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`given Dusija’s limited secondary use of SLC to reduce ECC complexity. Id., [0024]
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`(describing the “advantage gained at the slight expense of…infrequent additional
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`rewrites to a less density memory portion [i.e., SLC]”) (emphasis added).
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`B.
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`Sutardja (Ex. 1011)
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`Sutardja describes a solid-state memory system having a controller and two
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`separate solid-state nonvolatile memory referred to as the first and second NVS
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`memories. Ex. 1011, Abstract; Ex. 2014, ¶¶60-65. According to Sutardja, “the first
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`NVS memory has a first storage capacity that is greater than a second storage
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`capacity of the second NVS memory.” Ex. 1011, [0012]. Both memories “may
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`include single-level cell (SLC) flash memory or multi-level cell (MLC) flash
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`memory.” Id., [0108].
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`In contrast to the ’240 Patent, Sutardja states that the memories are treated “as
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`if all the blocks formed a single memory.” Id., [0160-0162]. For example, Sutardja
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`describes that “[w]hen a write request arrives from the host, the wear leveling
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`module may select the block of memory that has been written to the least from
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`among the available blocks” and “then maps the incoming logical address to the
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`physical address of this block.” Id., [0111]. Sutardja further explains that “[o]ver
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`time, this may produce a nearly uniform distribution of write operations across
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`memory blocks.” Id.
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`In further contrast to the ’240 Patent, Sutardja does not determine which of
`
`the blocks are accessed most frequently by maintaining a count of the number of
`
`times each one of the blocks is accessed. Instead, Sutardja maintains “normalized
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`write … and/or erase cycle counts.” Id., [0122], [0160-0165]. Further, Sutardja
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`relies on “write frequencies for logical addresses” to manage the solid-state memory
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`system. Id., [0146]. As seen in Figure 7A below, every mention of “frequency” is
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`referring to the “logical addresses.”
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`Id., FIG. 7A. There is no mention in Figure 7A or the corresponding paragraphs
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`[0145-0147] of determining which physical blocks are accessed most frequently. At
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`the bottom of Figure 7A is a circle “B” to indicate that the flowchart continues to the
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`
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`next Figure 7B.
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`Id., FIG. 7B. In step 514, the control determines whether it is time to perform data
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`shift analysis. Id., [0148]. But Sutardja never explains when, if ever, it is time to
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`perform the data shift analysis. Id.
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`To the right of step 514, is a circle “C” to indicate that the flowchart continues
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`to the next Figure 7C.
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`Id., FIG. 7C. Figure 7C is the first time that the word “block” is used. But like
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`before, there is no mention of determining which of the blocks are accessed most
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`frequently by maintaining a count of the number of times each one of the blocks is
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`accessed. In other words, these operations are performed on a per-block basis, and
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`not on blocks. In step 520, the control determines if a number of write operations to
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`a first block during a predetermined time is greater than or equal to a predetermined
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`threshold. Id., [0149]. Sutardja never explains, however, what the “predetermined
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`time” or “predetermined threshold” are.
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`If the number of writes exceeds the threshold, the control maps the
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`corresponding logical addresses to a block of the second NVS memory. Id., [0149],
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`FIG. 7C (step 522). There is no mention in Sutardja of transferring the contents of
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`the first block to SLC. In fact, Sutardja states that the second NVS memory may
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`include SLC or MLC. Id., [0108]. To the extent the second NVS memory even
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`includes SLC, there is no mention of transferring the data to SLC.
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`As mentioned above, Sutardja maps data to blocks that have the least
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`normalized wear, regardless of whether they are SLC or MLC. In essence, Sutardja
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`attempts to create a memory system which is operated “as if all the blocks formed a
`
`single memory,” where data is wr