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`UNITED STATES PATENT AND TRADEMARK OFFICE
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`MICRON TECHNOLOGY, INC.,
`Petitioner,
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`v.
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`VERVAIN, LLC,
`Patent Owner.
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`
`
`IPR2021-01549
`U.S. Patent No. 9,997,240
`
`
`
`DECLARATION OF SUNIL P. KHATRI
`IN SUPPORT OF PATENT OWNER’S RESPONSE
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`Vervain Ex. 2014, p.1
`Micron v. Vervain
`IPR2021-01549
`
`

`

`Declaration of Sunil P. Khatri, Ph. D.
`IPR2021-01549
`U.S. Patent No. 9,997,240
`
`
`TABLE OF CONTENTS
`
`
`
`
`
`INTRODUCTION .......................................................................................... 1
`
`BACKGROUND AND QUALIFICATIONS ................................................ 1
`
` SCOPE OF ASSIGNMENT AND MATERIALS
`CONSIDERED ............................................................................................. 12
`
` PERSON OF ORDINARY SKILL IN THE ART ........................................ 13
`
` GENERAL BACKGROUND OF THE RELEVANT
`TECHNOLOGY ........................................................................................... 15
`
`A.
`
`SLC and MLC Flash ........................................................................... 17
`
`B. Address Table ..................................................................................... 19
`
`C. Data Integrity Tests ............................................................................. 20
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`D. Hot and Cold Data .............................................................................. 20
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` THE ’240 PATENT ...................................................................................... 21
`
` CLAIM CONSTRUCTION .......................................................................... 22
`
`A.
`
`“blocks” (claims 1, 6) ......................................................................... 22
`
`B.
`
`C.
`
`“data integrity test” (claim 1).............................................................. 27
`
`“on a periodic basis” (claims 1, 6) ...................................................... 27
`
` OVERVIEW OF THE PRIOR ART ............................................................. 27
`
`A. Dusija (Ex. 1010) ................................................................................ 27
`
`B.
`
`Sutardja (Ex. 1011) ............................................................................. 32
`
`C.
`
`Chin (Ex. 1030)................................................................................... 37
`
` THE CITED REFERENCES DO NOT DISCLOSE OR
`SUGGEST ALL OF THE FEATURES OF CLAIMS 1-2
`and 6-7........................................................................................................... 41
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`

`

`Declaration of Sunil P. Khatri, Ph. D.
`IPR2021-01549
`U.S. Patent No. 9,997,240
`
`
`A. Dusija in View of Sutardja Does Not Disclose or
`Suggest All the Features of Claims 1-2 and 6-7
`(Ground 1)........................................................................................... 41
`
`1.
`
`2.
`
`Limitation [1.F] – “wherein the controller is
`further adapted to determine which of the
`blocks of the plurality of the blocks in the
`MLC and SLC non-volatile memory modules
`are accessed most frequently and wherein the
`controller segregates
`those blocks
`that
`receive frequent writes into the at least on
`SLC non-volatile memory module and those
`blocks that receive infrequent writes into the
`at least one MLC nonvolatile module” .................................... 41
`
`Limitation [1.G] – “maintain a count value
`of the blocks in the MLC non-volatile memory
`module determined to have received frequent
`writes and that are accessed most frequently
`on a periodic basis when the count value is a
`predetermined count value, transfer the
`contents of the counted blocks in the MLC
`non-volatile memory module determined to
`have received frequent writes after reaching
`the predetermined count value, transfer the
`contents of the counted blocks in the MLC
`non-volatile memory module determined to
`have received frequent writes after reaching
`the predetermined count value to the SLC
`non-volatile memory module and which
`determined blocks in the SLC are determined
`in accordance with the next equivalent range
`of physical addresses determined by the
`controller” ................................................................................ 53
`
`3.
`
`Claims 2, 6, and 7 (Ground 1) .................................................. 60
`
`ii
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`IPR2021-01549
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`Declaration of Sunil P. Khatri, Ph. D.
`IPR2021-01549
`U.S. Patent No. 9,997,240
`
`
`B. Dusija in View of Sutardja and Chin Does Not
`Disclose or Suggest All the Features of 1-2 and 6-7
`(Ground 2)........................................................................................... 60
`
`
`
`CONCLUSION ............................................................................................. 62
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`
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`iii
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`IPR2021-01549
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`Declaration of Sunil P. Khatri, Ph. D.
`IPR2021-01549
`U.S. Patent No. 9,997,240
`
`
`DECLARATION OF SUNIL P. KHATRI, PH. D
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`
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`I, Sunil P. Khatri, do hereby declare as follows:
`
`
`
`INTRODUCTION
`
`
`
`I have been retained on behalf of Vervain, LLC (“Vervain”), and its
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`counsel, McKool Smith, P.C., as an expert in this proceeding. I am personally
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`knowledgeable about the matters stated herein and am competent to make this
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`declaration.
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`
`
`I understand that Vervain will submit this Declaration in connection
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`with the Patent Owner’s Response in IPR2021-01549, which I have been informed
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`is an inter partes review (IPR) proceeding challenging the patentability of certain
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`claims of U.S. Patent No. 9,997,240 (“the ’240 patent” or “the challenged patent”).
`
`
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`I receive compensation at an hourly rate of $700 per hour for my time
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`working on this matter, plus expenses. I have no financial interest in Vervain or in
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`the patents involved in this litigation, and my compensation is not dependent on the
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`outcome of this litigation. The conclusions I present are due to my own judgment.
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` BACKGROUND AND QUALIFICATIONS
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`
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`I have over thirty-five years of experience with electronics, electrical
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`engineering, and computer engineering. A copy of my latest curriculum vitae (CV),
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`which I understand was submitted previously as part of my prior declaration in this
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`
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`

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`Declaration of Sunil P. Khatri, Ph. D.
`IPR2021-01549
`U.S. Patent No. 9,997,240
`
`proceeding (Exhibit 2001, Appendix A), provides further details regarding my
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`background and qualifications. During my career, I have acquired extensive
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`knowledge and experience with VLSI circuits, computer architecture, testing,
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`computer-aided design (CAD) algorithms and algorithm acceleration, logic
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`synthesis, semiconductor memory, redundancy, synchronous and asynchronous
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`circuits, and related software and hardware topics. Most relevant to the challenged
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`patents, my technical expertise includes extensive work with semiconductor memory
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`devices such as DRAM, SRAM and flash. My work with semiconductor memory
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`devices has included work on 3D integration and novel ring-based memory
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`architectures, power and speed tradeoffs using selective body bias, architectures and
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`circuit approaches for processing-in-memory, radiation hardening analysis for
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`memories, the use of flash transistors for designing logic circuits (such as ternary
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`Content-addressable Memories (CAMs), Field Programmable Gate Arrays
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`(FPGAs), convolutional neural networks (CNNs) for machine learning (ML), low
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`drop-out (LDO) voltage regulators, digital to analog converters (DACs), and
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`traditional binary-valued as well as ternary-valued general purpose digital logic),
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`and clocking and source-synchronous design. I recently was awarded a research
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`grant by the Air Force Research Laboratory (AFRL) in Rome, NY, to conduct
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`research in secure digital circuits using flash-based digital design approaches.
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`
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`2
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`Declaration of Sunil P. Khatri, Ph. D.
`IPR2021-01549
`U.S. Patent No. 9,997,240
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`Additionally, I have submitted a book chapter on the use of flash transistors in novel
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`Very Large Scale Integrated (VLSI) design applications. My MS thesis involved
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`designing a memory interface for a multi-threaded Reduced Instruction Set
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`Computing (RISC) microprocessor.
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`
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`The following describes some of my relevant experience. I earned my
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`Bachelor of Science in Electrical Engineering in 1987 from the Indian Institute of
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`Technology, Kanpur, India. After graduating with my B.S. degree, I was a candidate
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`for a Master of Science degree in Electrical and Computer Engineering at the
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`University of Texas from 1987–89. At the University of Texas, I held the
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`Microelectronics and Computer Development (MCD) Fellowship from 1987–89. I
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`also conducted my M.S. research and wrote my thesis on the design of the METRIC
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`memory interface and memory system. METRIC was one of the first super-scalar
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`processors that was developed in the world. I earned an M.S. degree in 1989 from
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`the University of Texas, Austin.
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`
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`After leaving the University of Texas, I worked at Motorola Inc. from
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`1989–93 as a design engineer for the MC88110 reduced instruction set computing
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`(RISC) microprocessor team, followed by the PowerPC 603 RISC microprocessor
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`design team. My duties included the design of digital and analog circuitry, test logic
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`circuits and layout, JTAG boundary scan design, input/output driver design, and
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`
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`3
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`Declaration of Sunil P. Khatri, Ph. D.
`IPR2021-01549
`U.S. Patent No. 9,997,240
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`clock phase-locked loop (PLL) logic and clock distribution. During my time at
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`Motorola, I was independently responsible for the design of the factory test
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`controller of the MC88110 microprocessor. I performed all attendant tasks in a
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`“vertical” VLSI design methodology, which included high-level modeling, circuit
`
`and layout design and verification, as well as global and detailed routing. I also
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`helped in the design of the Translation Lookaside Buffer (TLB) unit, which included
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`a static random-access memory (SRAM) block.
`
`
`
`In 1999, I earned a Doctor of Philosophy degree in Electrical
`
`Engineering and Computer Sciences from the University of California, Berkeley.
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`While at Berkeley, I held the California Microelectronics (MICRO) Fellowship in
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`1993.
`
`
`
`I joined the faculty at the University of Colorado, Boulder, in 2000 as
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`an Assistant Professor of Electrical and Computer Engineering. At the University of
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`Colorado my research focused on VLSI logic design automation, VLSI layout design
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`automation, and VLSI design methodologies to address Deep Submicron (DSM)
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`issues such as crosstalk and power.
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`
`
`I joined the faculty at Texas A&M University in 2004 as an Assistant
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`Professor in Electrical and Computer Engineering. In 2010 I was promoted to
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`Associate Professor in Electrical and Computer Engineering. In 2015, I was
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`
`
`4
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`

`

`Declaration of Sunil P. Khatri, Ph. D.
`IPR2021-01549
`U.S. Patent No. 9,997,240
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`promoted to full Professor in Electrical and Computer Engineering. My research
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`focuses on three primary areas: the first is computer systems, including computer
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`architecture from the circuits up, and algorithm acceleration using GPUs, FPGAs
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`and custom ICs. The second is logic and its applications, while the third area consists
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`of interdisciplinary extensions of the first two. Some specific recent research topics
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`include circuit design using floating gate devices, wireless power delivery, battery-
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`less electronic systems, machine learning architectures, secure computing
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`approached from both a hardware and software perspective, and the mathematics of
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`scalable cryptocurrency. One of my new focus areas is intelligent and secure
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`computing viewed from the hardware (circuit) as well as the software levels. I am
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`conducting research on tamper-proof memory techniques, as well as multi-row read
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`architectures for SRAM, DRAM and flash memory arrays.
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` At Texas A&M I teach classes that cover memories extensively,
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`featuring thorough discussion of sense amplifiers, row and column decoders, and
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`different types of memory circuits. For example, in Electrical and Computer
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`Engineering (ECEN) 752 “Advances in VLSI Circuit Design,” a graduate level
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`course, I cover all aspects of VLSI design, including memory design. In ECEN
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`449/749 “Microprocessor System Design,” and in ECEN 752, I cover memories,
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`including flash memories, the design of flash memory cells, the organization of
`
`
`
`5
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`Declaration of Sunil P. Khatri, Ph. D.
`IPR2021-01549
`U.S. Patent No. 9,997,240
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`memories into multiple banks, and the division of data across multiple banks of
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`memory, as well as other design techniques that can be used to optimize and manage
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`memories. This course is attended by both undergraduate (ECEN 449) and graduate
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`(ECEN 749) students. In ECEN 454 “Digital Circuit Design,” a senior
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`undergraduate course, I cover circuit design techniques for memory in detail. The
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`Ph.D. thesis of one of my recent doctoral students dealt with the use of flash
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`transistors to design logic circuits. The research of a recent M.S. student entailed a
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`new ring-based source synchronous architecture for 3D DRAM technologies, which
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`has been published at a conference and in a journal and is being submitted for
`
`dissemination as a research monograph. Currently, 3 of the Ph.D. students that I
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`advise are conducting research in novel uses of floating gate (flash) transistors for
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`machine learning, analog circuits, and secure digital hardware. In the past, I have
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`conducted research into new topologies for efficient memory redundancy as part of
`
`a course project for my graduate course.
`
` Since 2000, I have earned 24 research contracts from funders including
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`Intel, the National Science Foundation, the National Security Agency, Altera
`
`Corporation,
`
`the National Center
`
`for Atmospheric Research, National
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`Semiconductor Corporation, and several private sources. The total amount for these
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`research grants is $17.53 million, of which my portion is $2.85 million.
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`
`
`6
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`IPR2021-01549
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`

`

`Declaration of Sunil P. Khatri, Ph. D.
`IPR2021-01549
`U.S. Patent No. 9,997,240
`
`
`
`
`I have a total of over 275 peer-reviewed publications. Among these
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`papers, five received a best paper award, while seven others received best paper
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`nominations (including one journal best paper nomination). An additional six journal
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`papers and six conference papers are currently undergoing peer review. I have co-
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`authored nine research monographs, one edited research monograph, and three book
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`chapters. Additionally, I have six awarded U.S. Patents (one of which was filed
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`during my tenure at Texas A&M), two filed provisional U.S. Patents, and another
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`U.S. Patent which is currently under review and was also submitted during my tenure
`
`at Texas A&M. I have co-authored one invited journal paper and 13 invited
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`conference or workshop papers (including one from Design Automation Conference
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`(DAC) and one from Allerton). Moreover, I was invited to serve as a panelist at a
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`conference seven times and have presented two conference tutorials. I received the
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`“Outstanding Professor Award” in the ECE Department at Texas A&M University
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`in 2007 and also in 2020. My H-index is 33 (per Google Scholar).
`
` Since 2003, I have published numerous research monographs, journal
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`papers, and conference papers on flash transistors and memory systems, as detailed
`
`in my CV. A few papers on relevant subject areas authored or co-authored by me
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`include:
`
`
`
`7
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`IPR2021-01549
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`

`

`Declaration of Sunil P. Khatri, Ph. D.
`IPR2021-01549
`U.S. Patent No. 9,997,240
`
`
`•
`
`"CIDAN-XE: Computing in DRAM with Artificial Neurons", Singh,
`
`Wagle, Khatri, Vrudhula. Frontiers in Electronics, section Integrated
`
`Circuits and VLSI. Vol. 3, Feb 2022;
`
`•
`
`"A Flash-based Current-mode IC to Realize Quantized Neural
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`Networks", Scott, Lee, Khatri, Vrudhula. Design Automation and Test
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`in Europe (DATE) Conference, Mar 2022, virtual conference;
`
`•
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`"CIDAN: Computing in DRAM with Artificial Neurons", Singh,
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`Wagle, Vrudhula, Khatri. 39th IEEE International Conference on
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`Computer Design (ICCD) 2021, pp. 349-356, Oct 2021, virtual
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`conference;
`
`•
`
`Fast, Ring-based Design of 3D Stacked DRAM, IEEE Transactions on
`
`Very Large Scale Integrated Circuits (VLSI) Systems (TVLSI), Vol 27
`
`number 8, Aug 2019. pp. 1731-1741;
`
`•
`
`•
`
`Fast, Ring-Based Design of 3D Stacked DRAM, IEEE International
`
`Conference on Computer Design 2017: pp. 665-672;
`
`Selective Forward Body Bias for High Speed and Low Power SRAMs,
`
`Journal of Low Power Electronics, Vol. 5, No. 2, Aug. 2009, pp. 185-
`
`95;
`
`•
`
`Low Power and High Performance SRAM Design using Bank-based
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`Selective Forward Body Bias, IEEE/ACM Great Lakes Symposium on
`
`VLSI, May 10-12, 2009, Boston, MA, pp. 441-44;
`
`•
`
`Modeling Dynamic Stability of SRAMs in the Presence of Single Event
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`Upsets (SEUs), IEEE International Symposium on Circuits and
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`Systems, May 18-21, 2008, Seattle, WA, pp. 1788-91;
`
`
`
`8
`
`Vervain Ex. 2014, p.12
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`IPR2021-01549
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`

`

`Declaration of Sunil P. Khatri, Ph. D.
`IPR2021-01549
`U.S. Patent No. 9,997,240
`
`
`•
`
`“Design of a Flash-based Circuit for Multi-valued Logic”, Proceedings
`
`of the Great Lakes Symposium on VLSI (GLSVLSI) 2017, pp. 41-46,
`
`May 10-12, 2017. Banff, Canada.
`
`•
`
`"SAT-Based Optimization
`
`for Flash-Based Digital Designs",
`
`IEEE/ACM Design Automation Conference (DAC), Jun 18-22 2017,
`
`Austin, TX.
`
`•
`
`"A Flash-based Digital Circuit Design Flow", IEEE/ACM International
`
`Conference on Computer-Aided Design (ICCAD) 2016, Austin, TX,
`
`Nov 2016.
`
`•
`
`"Implementing low power digital circuits using flash devices", 2016
`
`IEEE 34th International Conference on Computer Design (ICCD), pp.
`
`109-116, Oct 3-5, 2016, Phoenix, AZ.
`
`•
`
`•
`
`•
`
`"Exploring Flash Devices to Implement Digital Circuits", IEEE/ACM
`
`Design Automation Conference (DAC), June 2016, Austin, TX.
`
`FTCAM: An Area-efficient Flash-based Ternary CAM Design, IEEE
`
`Transactions on Computers, Vol. 65, No. 8, Aug. 2016, pp. 2652-58;
`
`An Area-efficient Ternary CAM Design Using Floating Gate
`
`Transistors, IEEE International Conference on Computer Design, Oct.
`
`19-22, 2014, Seoul, S. Kor., pp. 55-60; and
`
`•
`
`A Fast Ternary CAM Design for IP Networking Applications,
`
`International Conference on Computer Communications and Networks,
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`October 22, 2003, Dallas, TX, pp. 434-39 (awarded best paper).
`
`
`In addition to my work on the papers listed above, I have also served as an editor
`
`for IEEE Transactions on Computers, ACM Transactions on Design Automation of
`
`
`
`9
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`

`

`Declaration of Sunil P. Khatri, Ph. D.
`IPR2021-01549
`U.S. Patent No. 9,997,240
`
`Electronic Systems, and MDPI Journal of Electronics.
`
`
`
`I have served as EDA Track Co-Chair for ICECS 2014, Panel Chair for
`
`TexasWISE 2014, Track Co-Chair (VLSI Systems, Applications and Computer
`
`Aided Design track) for ICECS 2013, Poster Session Chair for TexasWISE 2013,
`
`Advisory Committee for HotPI 2013, Panel Session Chair for SLiP 2013, Track
`
`Chair (Logic track) for ICCAD 2009-10, 2015-17, Track Chair (logic track) for DAC
`
`2016-17, General Chair for IWLS 2009, Technical Program Chair for IWLS 2008,
`
`Track Co-Chair, Computer Aided Network DEsign (CANDE) Track, for ISCAS
`
`2008-10, Track Co-chair for the DSP track for ISCAS 2022, Track Co-Chair, Test
`
`and Methodologies Track, for ICCD 2007, Panel Chair for ITSW 2009, Publicity
`
`Co-Chair for GLS-VLSI 2009, and as a member of the TPC for several conferences.
`
`
`
`I am generally familiar with the analysis of patents. I am a named
`
`inventor on the following U.S. Patents:
`
`•
`
`Data Processing System Having Serial Self Address Decoding and
`
`Method of Operation, United States Patent No. 5,347,523, issued
`
`September 13, 1994;
`
`•
`
`•
`
`Circuit Identifier for Use with Focused Ion Beam Equipment, United
`
`States Patent No. 5,408,131, issued April 18, 1995 (“the ’131 patent”);
`
`Driver Circuit with Self-Adjusting Impedance Matching, United States
`
`Patent No. 5,448,182, issued September 5, 1995 (“the ’182 patent”);
`
`
`
`10
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`Vervain Ex. 2014, p.14
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`

`

`Declaration of Sunil P. Khatri, Ph. D.
`IPR2021-01549
`U.S. Patent No. 9,997,240
`
`
`•
`
`Circuit Identifier for Use with Focused Ion Beam Equipment, United
`
`States Patent No. 6,156,579, issued December 5, 2000 (“the ’579
`
`patent”);
`
`Datapath Design Methodology and Routing Apparatus, United States
`
`Patent No. 6,598,215, issued July 22, 2003;
`
`Low Power Reconfigurable Circuits with Delay Compensation, United
`
`States Patent No. 7,880,505, issued February 1, 2011.
`
`•
`
`•
`
`
`
` The ’131 and ’579 patents are directed to an identification means for
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`redundant circuits that distinguishes said circuits by respective function. This allows
`
`for identification by focused ion beam equipment, which can then repair, replace, or
`
`supplement circuits as necessary. These patents disclose a scheme for replacing
`
`defective cells or circuits within a larger circuit.
`
` The ’182 patent relates to a driver circuit capable of switching from one
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`driving impedance to a second in response to the output signal of a first driver portion
`
`reaching a predetermined voltage. It discloses a driver circuit capable of adjusting
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`circuit configurations depending upon the current output state. It results in
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`significantly reduced noise on board-level traces even without using terminating
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`resistors.
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`
`
`11
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`Vervain Ex. 2014, p.15
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`

`Declaration of Sunil P. Khatri, Ph. D.
`IPR2021-01549
`U.S. Patent No. 9,997,240
`
`
` SCOPE OF ASSIGNMENT AND MATERIALS CONSIDERED
`
`
`
`I have been retained by Vervain (“Patent Owner”) to provide an
`
`explanation to the Board regarding the invention described and claimed in the
`
`challenged patent. I understand Petitioner Micron Technology, Inc. (“Micron” or
`
`“Petitioner”), has filed a petition for inter partes review, No. IPR2021-01549,
`
`against the challenged patent. I have been retained to provide my opinions regarding
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`various technical issues relating to the validity of the challenged patent over the prior
`
`art references identified by Micron’s petition.
`
`
`
`In preparing this Declaration, I am relying on my own knowledge and
`
`expertise as well as the following documents:
`
`• U.S. Patent No. 9,997,240 (Ex. 1005) to G.R. Mohan Rao (“the ’240
`
`patent”);
`
`• Prosecution history (Ex. 1006) of the challenged patent, which I
`
`understand constitutes the exchange of correspondence between the
`
`Patent Office and the applicant;
`
`• Micron’s petition for inter partes review (Paper No. 1), No. IPR2021-
`
`01549, as well as the declaration of Dr. David Liu (Ex. 1009) submitted
`
`in support thereof and the transcript of Dr. Liu’s deposition (Ex. 2015);
`
`• The alleged prior art references relied upon in Micron’s petitions;
`
`• The claim construction order issued on January 24, 2022 for Case Nos.
`
`6:21-cv-487-ADA; Vervain v. Micron Technology et al.; U.S. District
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`Court, Western District of Texas; 6:21-cv-488-ADA; Vervain v.
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`Micron v. Vervain
`IPR2021-01549
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`

`

`Declaration of Sunil P. Khatri, Ph. D.
`IPR2021-01549
`U.S. Patent No. 9,997,240
`
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`Western Digital Corporation et al.; U.S. District Court, Western
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`District of Texas (Ex. 2012);
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`• U.S. Patent No. 8,284,940 (Ex. 2016);
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`• Any other documents cited or discussed within this Declaration.
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` PERSON OF ORDINARY SKILL IN THE ART
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` When interpreting a patent, I understand that it is important to view the
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`disclosure and claims of that patent from the level of ordinary skill in the relevant
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`art at the time of the invention, which I have been asked to initially consider as the
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`2011 time frame, including and up to July 19, 2011, which is the filing date of
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`Provisional Application No. 61/509,257, which I am informed is a provisional
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`application to which the ’240 patent claims priority. I am informed that the ’240
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`patent also claims priority to Application No. 13/455,267 filed April 25, 2012, which
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`issued as U.S. Patent No. 8,891,298, and my opinions and analysis are still
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`applicable if the April 25, 2012 date is considered as the time of the invention. My
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`opinion of the level of ordinary skill in the art with regard to the challenged patent
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`is based on my personal experience working and teaching in the fields of electrical
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`engineering and computer science, including work with memory technologies, my
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`knowledge of the background and education of colleagues and others working in that
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`general field as of and for several years prior to the 2011-2012 time frame, my study
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`of the challenged patent, and its file history, and my knowledge of:
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`

`Declaration of Sunil P. Khatri, Ph. D.
`IPR2021-01549
`U.S. Patent No. 9,997,240
`
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`• The level of education and experience of persons actively working in the
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`field at the time the subject matter at issue was developed;
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`• The types of problems encountered in the art at the time the subject matter
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`was developed;
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`• The prior art patents and publications;
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`• The activities of others working in that same technical field;
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`• Prior art solutions to the problems addressed by the relevant art; and
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`• The sophistication of the technology at issue in this case.
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`
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`In determining the level of ordinary skill in the art, I also considered
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`the following factors: (1) the sophistication of the relevant technology; (2) the
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`rapidity with which innovations are made in that field; and (3) the educational level
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`of active workers in that field. It is my further understanding that these factors are
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`not exhaustive and are merely a useful guide to determining the level of ordinary
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`skill in the art.
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` Taking the above factors into account, in my opinion a person of
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`ordinary skill in the art (POSA) in the technology field of the challenged patent
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`would be a person with at least a Bachelor of Science degree in electrical
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`engineering, computer engineering, or a closely related field, with at least 3-5 years
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`of experience in the design of non-volatile memory devices. An individual with an
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`advanced degree in a relevant field would require less experience in the design of
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`non-volatile memory devices.
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`IPR2021-01549
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`

`Declaration of Sunil P. Khatri, Ph. D.
`IPR2021-01549
`U.S. Patent No. 9,997,240
`
`
`
`
`I understand that Micron’s expert, Dr. David Liu, agrees with this
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`definition. Ex. 1009, ¶37. This accords with my experience. Many of the individuals
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`hired by semiconductor manufacturing companies at the time of the invention did
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`not have graduate degrees, and thus the level of ordinary skill in the art should
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`specifically include such individuals.
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` GENERAL BACKGROUND OF THE RELEVANT TECHNOLOGY
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` Volatile memory, such as static random access memory (“SRAM”) and
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`dynamic random access memory (“DRAM”), lose their contents when the power
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`supply to the memory circuit is turned off. However, more persistent memory is
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`needed for many applications, such as photos in a digital camera, bootable code or
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`settings in circuits, or a wide range of data storage needs. Non-volatile memories
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`(e.g., thumb drives, hard drives, and compact discs) can store information after the
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`system is powered off. Traditionally, media such as rotating mechanical hard disks,
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`floppy disks, compact discs, or magnetic tapes was used for persistent storage in
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`computing systems, but these media are large, bulky, and slow, and use a large
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`amount of power. Flash memory is a specific type of non-volatile memory, where
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`data is stored in “blocks” of “pages.” Flash memory chips have come to be used for
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`persistent data storage in a wide range of applications. Data stored in flash memory
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`
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`Declaration of Sunil P. Khatri, Ph. D.
`IPR2021-01549
`U.S. Patent No. 9,997,240
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`persists across power on/off cycles and has a small size, high performance, and low
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`power consumption.
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` Flash memory uses a special type of transistor (called a “floating gate
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`transistor”) that, unlike a regular transistor, has two gates – a “floating gate” and a
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`“control gate.” In a floating gate transistor, charge is stored on an electrically
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`isolated conductor, called the floating gate. This charge has no path to dissipate (or
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`discharge). The charge on the floating gate effectively changes the threshold voltage
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`of the floating gate transistor, and thereby controls the current flowing between the
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`source and drain. This change in current allows the user to determine the value
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`stored in the cell.
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` To erase the cell, a voltage is applied between the drain and the control
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`gate. Charge is then dissipated through a mechanism called Fowler-Nordheim (FN)
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`tunneling.
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` To program a cell, a high voltage is applied to the control gate, while
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`the drain, source and bulk terminals are held low. In this situation, charge (electrons)
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`become trapped in the floating gate (based on the duration and magnitude of the
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`voltage applied to the control gate).
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` Floating gate transistors individually are limited in endurance.
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`Depending on the type of transistor and how it is configured, an individual transistor
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`IPR2021-01549
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`Declaration of Sunil P. Khatri, Ph. D.
`IPR2021-01549
`U.S. Patent No. 9,997,240
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`may not work reliably after it has been programmed and erased too many times. For
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`example, endurance for some flash transistors is on the order of 10,000 to 100,000
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`program-erase cycles. Flash transistors wear out, until they eventually reach this
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`endurance limit and fail.
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` Because of the limited endurance of floating gate transistors, and
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`because some locations in a memory may be very frequently rewritten in practice, it
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`is not always feasible to use the same transistor for every read/write to a specific
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`memory location. Rather, flash memory typically includes a controller that uses a
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`flash translation layer to map logical addresses (used by the host computer or
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`application) to physical addresses used to address the flash transistors in the physical
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`flash memory. This flash translation layer allows for wear to be leveled across all
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`the transistors on a device, and for bad blocks to be managed and avoided.
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`A.
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`SLC and MLC Flash
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` Early flash memory stored only a “0” or a “1” value in each transistor.
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`A “0” resulted from storing a certain range of threshold voltages in the transistor,
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`and a “1” resulted from storing a different range of threshold voltages in the
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`transistor, as shown below. This is today known as “SLC,” or “single level cell,”
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`flash. Later on, to increase the density of storage in flash memory, a technique
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`known as “MLC,” or “multiple level cell,” was introduced, where multiple threshold
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`
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`IPR2021-01549
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`Declaration of Sunil P. Khatri, Ph. D.
`IPR2021-01549
`U.S. Patent No. 9,997,240
`
`voltage levels were stored in each transistor would represent multiple bits of data.
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`For example, the following diagram shows how in SLC flash, for the same total
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`threshold voltage range, large threshold voltage ranges are assigned to the “1” and
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`“0” bits respectively, whereas in MLC flash, smaller threshold voltage ranges are
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`assigned to multiple-bit values such as “11,” “10,” “01,” and “00.”
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`
`
`Chen et al., Ultra MLC Technology Introduction, Advantech Technical White Paper
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`
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`(Oct. 5, 2012), 3.
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` The primary difference between SLC and MLC is what data each
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`threshold voltage is interpreted to represent. With SLC flash, the transistor stores
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`only a 1 or 0, so a wide range of threshold voltages can be allotted to a single bit.
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`This allows for faster and more reliable memory access. On the other hand, MLC
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`flash must be slowly and carefully pro