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`UNITED STATES PATENT AND TRADEMARK OFFICE
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`MICRON TECHNOLOGY, INC.,
`Petitioner,
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`v.
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`VERVAIN, LLC,
`Patent Owner.
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`
`
`IPR2021-01549
`U.S. Patent No. 9,997,240
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`PATENT OWNER’S PRELIMINARY RESPONSE
`PURSUANT TO 35 U.S.C. § 313 AND 37 C.F.R. § 42.107
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`TABLE OF CONTENTS
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`TABLE OF AUTHORITIES ................................................................................... iii
`EXHIBIT LIST .......................................................................................................... v
`I.
`INTRODUCTION ........................................................................................... 1
`II. OVERVIEW OF THE ’240 PATENT AND THE CHALLENGED
`CLAIMS .......................................................................................................... 4
`A.
`SLC and MLC Flash ............................................................................. 5
`B. Address Table ........................................................................................ 6
`C. Data Integrity Tests ............................................................................... 7
`D. Hot and Cold Data ................................................................................. 8
`E.
`Claims 1 and 6 ....................................................................................... 9
`III. CLAIM CONSTRUCTION .......................................................................... 13
`A.
`“data integrity test” (claims 1 and 6) ................................................... 14
`B.
`“on a periodic basis” (claims 1 and 6) ................................................ 16
`IV. OVERVIEW OF THE CITED PRIOR ART ................................................ 17
`A. Dusija ................................................................................................... 17
`B.
`Sutardja ................................................................................................ 22
`C.
`Chin ..................................................................................................... 26
`REASONS FOR DENYING INSTITUTION ............................................... 30
`A.
`The Board Should Exercise Its Discretion and Deny Institution ........ 30
`1.
`Factor 1: No Motion to Stay has Been Filed and the
`District Court is Unlikely to Grant a Stay ................................. 32
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`V.
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`2.
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`3.
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`4.
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`2.
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`3.
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`4.
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`B.
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`C.
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`Factor 2: The Board Will Issue a Final Written Decision
`Almost Three Months after the Parallel District Court
`Trial ........................................................................................... 32
`Factor 3: The Parties and District Court Have Invested—
`and Will Continue to Invest—Significant Time into the
`District Court Litigation ............................................................ 33
`Factor 4: There is Significant Overlap Between This
`Proceeding and the Parallel District Court Case ....................... 34
`Factor 5: The Parties are the Same in Both Proceedings .......... 36
`5.
`Factor 6: The Merits of the Petition are Not Strong ................. 37
`6.
`Additional Considerations ........................................................ 37
`7.
`The Petition Does Not Establish That Claims 1 and 6 Would
`Have Been Obvious over Dusija in View of Sutardja (Ground
`1) .......................................................................................................... 37
`1.
`The Petition Fails to Establish That Dusija or Sutardja
`Teach or Suggest [1.F] or [6.G.i] .............................................. 38
`The Petition Fails to Establish That Sutardja Teaches or
`Suggests [1.G] or [6.G.ii] .......................................................... 45
`The Petition Fails to Establish a Proper Motivation to
`Combine Dusija and Sutardja ................................................... 47
`The Petition Fails to Demonstrate a Reasonable
`Expectation of Success in Combining Dusija and
`Sutardja ..................................................................................... 53
`The Petition Does Not Establish That Claims 1 and 6 Would
`Have Been Obvious over Dusija, Sutardja, and Chin (Ground 2) ...... 55
`VI. CONCLUSION .............................................................................................. 58
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`TABLE OF AUTHORITIES
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`Page(s)
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`
`CASES
`Apple Inc. v. Fintiv, Inc.,
`IPR2020-00019, Paper 11 (PTAB Mar. 20, 2020) ......................................passim
`Bicon, Inc. v. Straumann Co.,
`441 F.3d 945 (Fed. Cir. 2006) ............................................................................ 15
`Cuozzo Speed Techs., LLC v. Lee,
`136 S. Ct. 2131 (2016) ........................................................................................ 30
`DePuy Spine, Inc. v. Medtronic Sofamor Danek, Inc.,
`469 F.3d 1005 (Fed. Cir. 2006) .......................................................................... 13
`E-One Inc. v. Oshkosh Corp.,
`IPR2019-00162, Paper 16 (PTAB June 5, 2019) ............................................... 37
`Harmonic Inc. v. Avid Tech., Inc.,
`815 F.3d 1356 (Fed. Cir. 2016) .......................................................................... 30
`Hill-Rom Servs., Inc. v. Stryker Corp.,
`755 F.3d 1367 (Fed. Cir. 2014) .......................................................................... 14
`In re Gurley,
`27 F.3d 551 (Fed. Cir. 1994) .............................................................................. 53
`In re Magnum Oil Tools Int’l, Ltd.,
`829 F.3d 1364 (Fed. Cir. 2016) .......................................................................... 54
`Innova/Pure Water, Inc. v. Safari Water Filtration Sys., Inc.,
`381 F.3d 1111 (Fed. Cir. 2004) .......................................................................... 15
`Intel Corp. v. VLSI Tech. LLC,
`IPR2019-01192, Paper 15 (PTAB Jan. 9, 2020) ................................................ 31
`KSR Int’l Co. v. Teleflex Inc.,
`550 U.S. 398 (2007) ............................................................................................ 48
`
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`iii
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`Merck & Co. v. Teva Pharm. USA, Inc.,
`395 F.3d 1364 (Fed. Cir. 2005) .......................................................................... 15
`Phillips v. AWH Corp.,
`415 F.3d 1303 (Fed. Circ. 2005) (en banc) ........................................................ 13
`Samsung Elecs. Co. Ltd., v. Clear Imaging Research, LLC,
`IPR2020-01400, Paper 13 (PTAB Feb. 3, 2021) ................................................ 35
`SK Innovation Co. LTD., v. LG Chem, LTD.,
`IPR2020-01239, Paper 14 (PTAB Jan. 12, 2021) ........................................ 36, 37
`Sotera Wireless, Inc. v. Masimo Corp.,
`IPR2020-01019, Paper 12 (PTAB Dec. 1, 2020) ............................................... 35
`TQ Delta, LLC v. Cisco Sys., Inc.,
`942 F.3d 1352 (Fed. Cir. 2019) .......................................................................... 48
`STATUTES
`35 U.S.C. § 313 .......................................................................................................... 1
`35 U.S.C. § 314(a) ..................................................................................... 1, 2, 30, 31
`35 U.S.C. § 315(e)(2) ......................................................................................... 35, 36
`OTHER AUTHORITIES
`37 C.F.R. § 42.4(a) ................................................................................................... 30
`37 C.F.R. § 42.107 ..................................................................................................... 1
`37 C.F.R. § 100(b) (2019) ........................................................................................ 13
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`EXHIBIT LIST
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`Exhibit No.
`2001
`
`Description
`Declaration of Dr. Sunil Khatri
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`Chen et al., Ultra MLC Technology Introduction, Advantech
`Technical White Paper (Oct. 5, 2012) (“Chen”)
`
`Excerpts from Micheloni et al., Inside NAND Flash Memories (1st ed.
`2010) (“Micheloni”)
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`U.S. Patent No. 10,950,300 to G.R. Mohan Rao (“’300 patent”)
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`Microsoft Computer Dictionary definition for “data integrity”
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`Hargrave’s Communications Dictionary definition for “data integrity”
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`https://www.law360.com/articles/1381597/albright-says-he-ll-very-
`rarely-put-cases-on-hold-for-ptab
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`Docket Sheet for Case. No. 6:21-cv-487-ADA; Vervain v. Micron
`Technology et al.; U.S. District Court, Western District of Texas.
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`Exhibit C-3, Invalidity Claim Chart for the ’240 Patent based on U.S.
`Patent Application Pub. No. 2011/0099460 (“Dusija”)
`
`Exhibit C-18, Invalidity Claim Chart for the ’240 Patent based on
`U.S. Patent Application Pub. No. US 2008/0140918 (“Sutardja”)
`
`Micron’s Preliminary Invalidity Contentions for U.S. Patent Nos.
`8,891,298; 9,196,385; 9,997,240; and 10,950,300; Case. No. 6:21-cv-
`487-ADA; Vervain v. Micron Technology et al.; U.S. District Court,
`Western District of Texas
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`Claim Construction Order; Case. No. 6:21-cv-487-ADA; Vervain v.
`Micron Technology et al.; U.S. District Court, Western District of
`Texas
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`v
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`2002
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`2003
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`2004
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`2005
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`2006
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`2007
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`2008
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`2009
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`2010
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`2011
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`2012
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`I.
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`INTRODUCTION
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`
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`U.S. Patent 9,997,240
`IPR2021-01549
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`Vervain, LLC (“Patent Owner” or “Vervain”) submits this preliminary
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`response in accordance with 35 U.S.C. § 313 and 37 C.F.R. § 42.107, responding to
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`the Petition for Inter Partes Review (“Petition”) of U.S. Patent No. 9,997,240 (the
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`“’240 Patent”) filed by Micron Technology, Inc. (“Micron” or “Petitioner”). Micron
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`petitions for inter partes review of claims 1-2 and 6-7 of the ’240 Patent, which is
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`owned by Vervain. Micron’s Petition includes two grounds. Ground 1 relies on the
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`combination of U.S. Patent App. Pub. No. 2011/0099460 (“Dusija”) and U.S. Patent
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`App. Pub. No. 2008/0140918 (“Sutardja”). Ground 2 relies on the three-way
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`combination of Dusija, Sutardja, and U.S. Patent App. Pub. No. 2010/0017650
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`(“Chin”). The Board should decline institution for the following reasons.
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`First, the Board should exercise its discretion and deny institution under 35
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`U.S.C. § 314(a). The parallel district court case, which involves four patents and not
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`just the one patent at issue here, has moved beyond its infancy and is progressing at
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`a steady clip. The district court already issued an order on a substantive motion and
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`held the Markman. Before the institution decision is due in this proceeding, the
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`parties will have spent three months in fact discovery—almost halfway through the
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`allotted fact discovery period. And trial in the parallel district court case—a date the
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`district court confirmed after the recently-completed Markman—is scheduled for
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`three months before the final written decision deadline here. Furthermore, Micron
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`asserts overlapping prior art in the parallel district court case both outright and under
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`U.S. Patent 9,997,240
`IPR2021-01549
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`the guise of being system art, but refuses to agree to any meaningful estoppel if there
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`is an institution here. On these facts, the advanced parallel district court proceeding
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`should proceed and this Petition should be denied under 35 U.S.C. § 314(a).
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`Second, the Board should deny institution on both Grounds because none of
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`the references teach or suggest elements [F] and [G] of claim 1 (hereinafter, [1.F]
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`and [1.G]), and elements [G.i] and [G.ii] of claim 6 (hereinafter, [6.G.i] and [6.G.ii]).
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`These elements require determining the blocks (as opposed to the logical addresses)
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`that are accessed most frequently by maintaining a count of the number of times each
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`one of the blocks is accessed, and transferring the contents of those blocks that
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`receive the most frequent writes to SLC memory. The claimed “blocks” are the
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`physical locations where the data is actually stored. The “logical address ranges”
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`are temporary or “pointer” addresses that may change over time.
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`Third, Petitioner relies primarily on Sutardja for [1.F] and [6.G.i] for both
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`Grounds. Petitioner acknowledges, however, that Sutardja “determines how
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`frequently data is written to each of the logical addresses.” Petitioner has not shown,
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`nor can it, that Sutardja determines the blocks that are accessed most frequently, and
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`transfers the contents of those blocks to SLC memory. Moreover, Petitioner has not
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`presented any evidence why it would have been obvious to do so.
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`Fourth, the Board should deny institution for the additional reason that
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`Sutardja does not teach or suggest transferring the contents of the blocks to SLC, as
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`required by [1.G] and [6.G.ii]. Rather Sutardja teaches that MLC and SLC should
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`be “normalized” and treated “homogeneously.” Therefore, Sutardja teaches away
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`from transferring the contents to SLC.
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`Fifth, Petitioner relies on the three-way-combination of Dusija, Sutardja, and
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`Chin for Ground 2. The Petition cites Chin for the limited assertion that it would
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`have been obvious to use a “collective write count” to start the “data shift analysis”
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`in Sutardja. Petitioner does not assert (nor can it) that Chin teaches or suggests
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`determining the blocks that are accessed most frequently by maintaining a count of
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`the number of times each one of the blocks is accessed, and transferring the contents
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`of those blocks that receive the most frequent writes to SLC memory. Therefore,
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`Chin does not remedy these deficiencies of Dusija and Sutardja.
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`Sixth, the Board should deny institution on Grounds 1-2 because Petitioner
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`has not demonstrated that a POSA would have had both (1) a motivation to combine
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`the asserted Dusija and Sutardja references, and (2) an expectation of success
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`combining them. More specifically, Dusija teaches that SLC should be used for a
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`limited purpose after the device has aged. Sutardja, on the other hand, teaches that
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`SLC and MLC should be used interchangeably throughout the life of the device.
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`Because of these diametrically different approaches, there would have been no
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`U.S. Patent 9,997,240
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`motivation to combine the references.
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`Accordingly, Patent Owner requests that the Board deny institution of
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`Micron’s Petition.
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`II. OVERVIEW OF THE ’240 PATENT AND THE CHALLENGED
`CLAIMS
`The ’240 Patent, entitled “Lifetime Mixed Level Non-Volatile Memory
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`System” was filed on November 24, 2015 and has an effective filing date of July 19,
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`2011. Ex. 1005. Dr. Mohan Rao is the sole named inventor of the ’240 Patent.
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`At a high level, the ’240 Patent describes, among other things, a reliable flash
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`memory storage system combining both single-level cell (SLC) and multi-level cell
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`(MLC) non-volatile memories.1 Id., Abstract. Prior to the ’240 Patent, Dr. Rao
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`recognized that “MLC NAND flash SSDs are slowly replacing and/or coexisting
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`with SLC NAND flash in newer SSD systems” because “MLC flash memory is less
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`expensive than SLC flash memory[] on a cost per bit basis.” Id., 3:32-33, 5:43-44.
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`However, while “MLC NAND flash enjoys greater density than SLC NAND flash”
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`it comes “at the cost of a decrease in access speed and lifetime (endurance).” Id.,
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`1 Non-volatile memories can store information even after the system is powered off.
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`Flash memory is a specific type of non-volatile memory, where data is stored in
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`“blocks” of “pages.” Ex. 1005, 2:48-65.
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`3:37-40. As a result, various hybrid systems combining SLC and MLC (among
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`U.S. Patent 9,997,240
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`others) have been developed to combine the benefits of both types of non-volatile
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`flash storage at a low cost. Id., 3:63-65.
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`The ’240 Patent addresses improvements and solutions for managing the
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`writing of data optimally for improved reliability and lifetime (endurance) of such
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`hybrid memory systems. Id., 3:58-65. Specifically, the Challenged Claims are
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`directed to specific techniques for efficiently using SLC and MLC flash to improve
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`the overall performance of the memory. Id., claims 1 and 6. For example, if certain
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`data is used more frequently, then it is transferred to higher-performance SLC. Id.
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`By doing so, the number of errors is reduced, and overall endurance of the memory
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`is increased. Id., 3:63-65.
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`A.
`SLC and MLC Flash
`SLC memory stores 1 bit per cell, and MLC memory stores more than 1 bit
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`per cell. Id., 2:13-16. As noted above, there are pros and cons to SLC and MLC
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`flash. In general, SLC is faster and less prone to errors, but requires more space and
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`power to store a given amount of data. Id., 1:53-58. The opposite is true of MLC.
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`MLC flash is slower and more prone to errors, but stores data more densely with less
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`power consumption. Id., 3:37-40.
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`SLC and MLC flash memories both use the same type of transistor called a
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`floating gate transistor. Id., 3:48. They both store a charge in the floating gate of
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`each transistor (cell), which changes the threshold voltage of the transistor. The
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`U.S. Patent 9,997,240
`IPR2021-01549
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`memory uses the threshold voltage to determine what bit, or bits, were stored in the
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`transistor. The MLC cell in the figure below illustrates threshold voltages for a 2-
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`bit MLC cell.
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`Ex. 2002, 5.
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`
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`The primary difference between SLC and MLC is what data each threshold
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`voltage represents. With SLC flash, the transistor stores only a 1 or 0, so a wide
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`range of threshold voltages can be allotted to a single bit. Ex. 1005, 3:34-35. This
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`allows for faster and more reliable memory access. On the other hand, MLC flash
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`must be slowly and carefully programmed to a narrower, more precise range of
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`threshold voltages, with each threshold voltage range representing a specific pair of
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`bits (see figure above, which shows four pairs of bits—11, 10, 01, and 00—
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`corresponding to smaller ranges of threshold voltages compared to the SLC). Id.,
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`3:35-37.
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`B. Address Table
`To provide wear leveling, garbage collection, and bad block management, a
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`translation layer is used to map logical addresses to actual physical memory
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`locations. Ex. 2003, 9-11; Ex. 1005, 2:66-3:31. As part of this translation layer,
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`“tables are widely used in order to map sectors and pages from logical to physical.”
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`Ex. 2003, 9; Ex. 1005, 3:15-19. These tables map logical blocks to physical blocks.
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`Ex. 2003, 9-11; Ex. 1005, 3:15-19. Using a “block” or similar granularity is
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`important, since flash memory is arranged so that when erasing and rewriting data,
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`a whole block is “erased together.” Ex. 2003, 6; Ex. 1005, 2:55-65. Dr. Rao
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`explained that “[t]he address ranges within the translation table will assume some
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`minimum quantum, such as, for example, one block…” Id., 5:46-50. Dr. Rao further
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`explained that memory is written and mapped on the granularity of a “quantum,”
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`such as a block or page. Id., 5:46-50; Figs. 3A-B.
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`During operation of the flash memory, logical addresses are frequently
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`remapped to new physical locations. Id., 3:16-49, 4:20-24, 5:39-59. Over time, a
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`particular logical address may be mapped or associated with many different physical
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`locations (blocks). Ex. 2001, ¶ 45. And multiple logical addresses may point to the
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`same block over time, so there is not a one-to-one correspondence between the
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`logical addresses and the blocks over time. Id.
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`C. Data Integrity Tests
`As mentioned above, when data is stored in MLC memory, it is more prone
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`to errors, and some data is more prone to errors than other data. One reason for this
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`is that the threshold voltage intervals for MLC memory are smaller than the intervals
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`for SLC memory, and thus, errors can occur when writing or reading the data. Ex.
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`2001, ¶ 33. Errors can also be caused by the data stored in neighboring cells. Id. A
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`data integrity test is a test that checks the integrity of the data (i.e., whether errors
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`have occurred). This test can be run immediately after data is written, or at a later
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`time. If the test reveals a problem such as corrupt data, the data can be remapped to
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`SLC (which is less error-prone), and the address table is modified accordingly. Ex.
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`1005, 4:24-29. Alternately, MLC data can be remapped to other MLC blocks, and
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`the address table is then modified accordingly. Id., 3:9-31.
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`D. Hot and Cold Data
`One can distinguish between “hot” blocks (which receive more frequent
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`writes), and “cold” blocks (which receive less frequent writes). Id., 6:46-52.
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`Because SLC has greater endurance, “hot” blocks can be allocated to SLC to
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`increase the lifetime of the system. Id. “Cold” blocks, on the other hand, can be
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`allocated to MLC to take advantage of its higher density storage.
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`As Dr. Rao explains, the contents of the “hot” blocks (plural) can be
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`transferred to SLC “on a periodic basis, such as, for example every 1000 writes or
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`every 10,000 writes.” Id., 6:52-58. By transferring groups of “hot” blocks on a
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`periodic basis, it allows the controller to transfer the data from MLC blocks to SLC
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`as a background process in-between write commands. Ex. 2001, ¶¶ 34, 54.
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`U.S. Patent 9,997,240
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`E. Claims 1 and 6
`In claim 1, the MLC and SLC comprise “erasable blocks” (highlighted red).
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`These are the physical locations that must be erased before data can be written to
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`them. See [1.A] and [1.B] below. Meanwhile, an address map comprises a list of
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`“logical address ranges” (highlighted purple); these logical address ranges are
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`mapped to the physical address ranges for the blocks. [1.D].
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`[1.PRE] A system for storing data comprising:
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`Claim 1
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`[1.A]
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`[1.B]
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`[1.C]
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`[1.D]
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`at least one MLC…module comprising a plurality of individually
`erasable blocks;
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`at least one SLC…module comprising a plurality of individually
`erasable blocks; and
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`a controller coupled to the at least one MLC…module and the at least
`one SLC…module,
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`the controller maintaining an address map of at least one of the MLC
`and SLC…modules, the address map comprising a list of logical
`address ranges accessible by a computer system, the list of logical
`address ranges having a minimum quanta of addresses, wherein each
`entry in the list of logical address ranges maps to a similar range of
`physical addresses within either the at least one SLC…module or
`within the at least one MLC…module;
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`U.S. Patent 9,997,240
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`[1.E] wherein the controller is adapted to determine if a range of addresses
`listed by an entry and mapped to a similar range of physical addresses
`within the at least one MLC…module, fails a data integrity test, and, in
`the event of such a failure, the controller remaps the entry to the next
`available equivalent range of physical addresses within the at least one
`SLC…module; and
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`[1.F] wherein the controller is further adapted to determine which of the
`blocks of the plurality of the blocks in the MLC and SLC…modules
`are accessed most frequently and wherein the controller segregates
`those blocks that receive frequent writes into the at least one
`SLC…module and those blocks that receive infrequent writes into the
`at least one MLC…module, and
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`[1.G] maintain a count value of the blocks in the MLC…module determined
`to have received frequent writes and that are accessed most frequently
`on a periodic basis when the count value is a predetermined count
`value, transfer the contents of the counted blocks in the MLC…module
`determined to have received frequent writes after reaching the
`predetermined count value to the SLC…module and which determined
`blocks in the SLC are determined in accordance with the next
`equivalent range of physical addresses determined by the controller.
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`As can be seen above, claim 1 uses the claim terms “blocks” and “logical
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`address ranges” to refer to two different things. The blocks are the physical locations
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`in the MLC and SLC where the data is stored. [1.A-B]. Each block has a fixed
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`“range of physical addresses.” [1.D]. Meanwhile, the address map contains a list of
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`logical address ranges that are mapped to the physical address ranges. Id. As the
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`claim indicates, the logical address ranges are remapped to new physical address
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`ranges. [1.E]. Thus, a logical address range does not permanently point to a specific
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`physical address range. Rather the corresponding physical address range may
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`change over time.
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`Turning to [1.F], the claim refers to “the blocks,” where the antecedent basis
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`is “erasable blocks” in [1.A-B]. Thus, the controller is adapted to “determine which
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`of the [erasable blocks]…are accessed most frequently.” Additionally, [1.F] recites
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`that the controller segregates blocks with “frequent writes” to SLC, and “infrequent
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`writes” to MLC.
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`Finally, in [1.G], the controller is adapted to transfer the contents of blocks
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`that receive frequent writes to SLC memory. Additionally [1.G] recites that it is
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`done on a periodic basis when the count value is a predetermined count value.
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`Like claim 1, claim 6 recites that the controller is adapted to determine the
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`blocks that are accessed most frequently, and more specifically, maintain a count
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`value those blocks that are accessed most frequently (see [6.G.i]). Additionally, the
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`controller is adapted to transfer the contents of those “counted blocks” to SLC
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`memory (see [6.G.ii]).
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`Claim 6
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`U.S. Patent 9,997,240
`IPR2021-01549
`
`[6.PRE] A system for storing data comprising:
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`[6.A]
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`[6.B]
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`[6.C]
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`[6.D]
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`at least one MLC…module comprising a plurality of individually
`erasable blocks;
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`at least one SLC…module comprising a plurality of individually
`erasable blocks; and
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`a controller coupled to the at least one MLC…module and the at least
`one SLC…module,
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`the controller maintaining an address map of at least one of the MLC
`and SLC…modules, the address map comprising a list of logical
`address ranges accessible by a computer system, the list of logical
`address ranges having a minimum quanta of addresses, wherein each
`entry in the list of logical address ranges maps to a similar range of
`physical addresses within either the at least one SLC…module or
`within the at least one MLC…module;
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`[6.E] wherein the controller allocates those blocks that receive frequent
`writes into the SLC…module as hot blocks and those blocks that only
`receive infrequent writes into the MLC…module as cold blocks; and
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`[6.F] wherein the controller is adapted to determine if a range of addresses
`listed by an entry and mapped to a similar range of physical addresses
`within the at least one MLC…module, fails a data integrity test, and, in
`the event of such a failure, the controller remaps the entry to the next
`available equivalent range of physical addresses within the at least one
`SLC…module;
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`U.S. Patent 9,997,240
`IPR2021-01549
`
`[6.G.i] wherein the controller is further adapted to maintain a count value of
`those blocks that are accessed most frequently and,
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`[6.G.ii] on a periodic basis when the count value is a predetermined count
`value, transfer the contents of those counted blocks into the
`SLC…module, wherein the counted blocks transferred to after
`reaching the predetermined count value are determined in accordance
`with the next equivalent range of physical addresses determined by the
`controller.
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`
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`III. CLAIM CONSTRUCTION
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`The claims in a post-grant review are construed using the same standard that
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`applies in district court proceedings, as set forth in Phillips v. AWH Corp., 415 F.3d
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`1303 (Fed. Circ. 2005) (en banc); 37 C.F.R. § 100(b) (2019). Claim terms are
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`afforded “their ordinary and customary meaning,” which is “the meaning that the
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`term would have to a [POSA] in question at the time of the invention.”2 Phillips,
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`415 F.3d at 1312–13. “In determining the meaning of the disputed claim limitation,
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`we look principally to the intrinsic evidence of record, examining the claim language
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`itself, the written description, and the prosecution history, if in evidence.” DePuy
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`2 For purposes of this preliminary response only, Patent Owner has used
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`Petitioner’s definition of a POSA. Petition, 27.
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`Spine, Inc. v. Medtronic Sofamor Danek, Inc., 469 F.3d 1005, 1014 (Fed. Cir. 2006)
`
`U.S. Patent 9,997,240
`IPR2021-01549
`
`
`
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`(citing Phillips, 415 F.3d at 1312-17).
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`A.
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`“data integrity test” (claims 1 and 6)
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`This term does not require construction, and it should be given the full scope
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`of its plain meaning—just as the district court already did. Ex. 2012 (district court’s
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`Claim Construction Order). Micron’s proposed construction—“a test conducted
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`after a write to flash to ensure that the data was written correctly”—imports
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`unnecessary limitations from the specification that are not present in the term “data
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`integrity test.” Micron has not identified any definition or disavowal (nor can it) that
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`would justify limiting the ordinary meaning of the term “data integrity test” to
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`Micron’s unduly narrow construction. See Hill-Rom Servs., Inc. v. Stryker Corp.,
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`755 F.3d 1367, 1371 (Fed. Cir. 2014). In fact, Micron’s construction contradicts the
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`intrinsic evidence in multiple ways.
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`For example, in the claims of related U.S. Patent No. 10,950,300, claim 1 and
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`12 refer to “performing a data integrity test on stored data in the MLC nonvolatile
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`memory element after at least a Write access operation.” Ex. 2004. If the term “data
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`integrity test” itself required that the test occur on “data after it has been written to
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`flash,” the claim’s separate requirement that the test be performed “on stored
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`data…after at least a Write access operation” would be rendered meaningless. Such
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`a construction is heavily disfavored: a guiding principle of claim construction is the
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`preference that a court give every term independent meaning within the claim. See
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`U.S. Patent 9,997,240
`IPR2021-01549
`
`
`
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`Bicon, Inc. v. Straumann Co., 441 F.3d 945, 950 (Fed. Cir. 2006) (“claims are
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`interpreted with an eye toward giving effect to all terms in the claim.”); Merck &
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`Co. v. Teva Pharm. USA, Inc., 395 F.3d 1364, 1372 (Fed. Cir. 2005) (“A claim
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`construction that gives meaning to all the terms of the claim is preferred over one
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`that does not do so.”); Innova/Pure Water, Inc. v. Safari Water Filtration Sys., Inc.,
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`381 F.3d 1111, 1119 (Fed. Cir. 2004) (“While not an absolute rule, all claim terms
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`are presumed to have meaning in a claim.”).
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`Nor does anything in the ’240 Patent specification require that a “data integrity
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`test” is necessarily limited to a test performed at a particular time, or to data that has
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`already been written to flash. Rather, it is possible to test the integrity of data in a
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`variety of circumstances. Indeed, Vervain’s plain meaning construction of this
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`term—i.e., testing the integrity of data—is entirely consistent with the stated purpose
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`of Dr. Rao’s invention, which includes “providing reliable storage through the use
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`of non-volatile memories.” Ex. 1005, 1:40-47. Nearly any data integrity test would
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`further Dr. Rao’s stated purpose of providing reliable storage.
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`Finally, the extrinsic evidence supports Vervain’s construction. The
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`Microsoft Computer Dictionary defines “data integrity” as “[t]he accuracy of data
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`and its conformity to its expected value, especially after being transmitted or
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`processed.” Ex. 2005, 3. Hargrave’s Communications Dictionary defines it as “[t]he
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`condition that exists when data are unaltered after a process as compared to data
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`U.S. Patent 9,997,240
`IPR2021-01549
`
`
`
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`before the process.” Ex. 2006, 8. Neither definition indicates that data integrity is
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`tested only “after it has been written to flash to ensure that the data was written
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`correctly.”
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`Thus, as the district court already held, this term should be given the full scope
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`of its plain meaning. Ex. 2012 (district court’s Claim Construction Order).
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`B.
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`“on a periodic basis” (claims 1 and 6)
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`Peti