EXHIBIT C-18
`INVALIDITY CLAIM CHART FOR THE ’240 PATENT
`BASED ON U.S. PATENT APPLICATION PUB. NO. US 2008/0140918 (“Sutardja”)
`
`U.S. Patent Application Publication No. US 2008/0140918 (“Sutardja”) was filed on December 7, 2007 and published on June 12,
`2008. Sutardja is prior art to the ’240 patent under at least 35 U.S.C. §§ 102(a), (b), (e) (pre-AIA). The asserted claims of the ’240
`patent are anticipated by Sutardja expressly and/or inherently or rendered obvious, either alone or in combination with other
`references, as set forth in the cover pleading for Micron’s Initial Invalidity Contentions and as further explained in the chart below.
`
`This chart is based on Defendants’ present understanding of Plaintiff’s apparent positions as to the scope of the asserted claims. By
`including prior art that invalidates the claims of the patent based on Plaintiff’s claim construction and infringement positions,
`Defendants are neither adopting nor acceding in any manner to Plaintiff’s claim construction and infringement positions.
`Furthermore, nothing stated herein shall be treated as an admission or suggestion that Defendants agree with Plaintiff regarding either
`the scope of any of the asserted claims or the claim constructions Plaintiff advances in its infringement allegations or anywhere else.
`Nor shall anything in this chart be treated as an admission that any of Defendants’ accused technology meets any limitations of the
`claims.
`
`Claim 1
`[1.Pre] A system for storing
`data comprising:
`
`U.S. Pat. No. 9,997,240
`Disclosure in Sutardja
`To the extent the preamble is limiting, Sutardja discloses and/or renders obvious a system for storing
`data.
`
`[1.A] at least one MLC non-
`volatile memory module
`comprising a plurality of
`individually erasable blocks;
`
`See, e.g.,
`
` FIGs. 1-3
`[0012]
`
`[0108]
`
`
`Sutardja discloses and/or renders obvious at least one MLC non-volatile memory module comprising
`a plurality of individually erasable blocks.
`
`See, e.g.,
`
` FIG. 3
`[0013]
`
`[0108]
`
`
`1
`
`Vervain Ex. 2010, p. 1
`Micron v. Vervain
`IPR2021-01549
`
`

`

`EXHIBIT C-18
`INVALIDITY CLAIM CHART FOR THE ’240 PATENT
`BASED ON U.S. PATENT APPLICATION PUB. NO. US 2008/0140918 (“Sutardja”)
`
`
`
`
`[0121]
`[0011]
`
`[1.B] at least one SLC non-
`volatile memory module
`comprising a plurality of
`individually erasable blocks;
`
`[1.C] a controller coupled to
`the at least one MLC non-
`volatile memory module and
`the at least one SLC non-
`volatile memory module,
`
`[1.D.i] the controller
`maintaining an address map
`of at least one of the MLC
`and SLC non-volatile memory
`modules, the address map
`comprising a list of logical
`address ranges accessible by a
`
`Sutardja discloses and/or renders obvious at least one SLC non-volatile memory module comprising a
`plurality of individually erasable blocks;
`
`See, e.g.,
`
`
`
`
`[0108]
`[0011]
`
`Sutardja discloses and/or renders obvious a controller coupled to the at least one MLC non-volatile
`memory module and the at least one SLC non-volatile memory module
`
`See, e.g.,
`
` FIGs. 1-7
`[0105]
`
`[0107]
`
`[0118]
`
`[0129]-[1030]
`
`
`See also Claim limitations [1.A-B] and accompanying citations.
`
`Sutardja discloses and/or renders obvious the controller maintaining an address map of at least one of
`the MLC and SLC non-volatile memory modules, the address map comprising a list of logical address
`ranges accessible by a computer system
`
`See, e.g.,
`
`
`
`[0042]
`
`2
`
`Vervain Ex. 2010, p. 2
`Micron v. Vervain
`IPR2021-01549
`
`

`

`computer system,
`
`EXHIBIT C-18
`INVALIDITY CLAIM CHART FOR THE ’240 PATENT
`BASED ON U.S. PATENT APPLICATION PUB. NO. US 2008/0140918 (“Sutardja”)
`
`[0105]
`
`[0118]
`
`[0149]
`
`[0150]
`
` FIG. 7C
`[0011]-[0012] (controller performs logical to physical mapping)
`
`[0047]
`
`[0107]
`
`
`[1.D.ii] the list of logical
`address ranges having a
`minimum quanta of addresses
`
`[1.D.iii] wherein each entry in
`the list of logical address
`ranges maps to a similar range
`of physical addresses within
`either the at least one SLC
`non-volatile memory module
`or within the at least one
`MLC non-volatile memory
`module
`
`Sutardja discloses and/or renders obvious the list of logical address ranges having a minimum quanta
`of addresses.
`
`See, e.g.,
`
`
`
`
`
`
`
`[0018]-[0019] (block addressing)
`[0027]-[0028]
`[0036]-[0037]
`[0111]
`[0121]-[0123]
`
`Sutardja discloses and/or renders obvious wherein each entry in the list of logical address ranges maps
`to a similar range of physical addresses within either the at least one SLC non-volatile memory
`module or within the at least one MLC non-volatile memory module
`
`See, e.g.,
`
`
`
`
`
`
`
`[0042]
`[0112]
`[0118]
`[0126]
`[0149]-[0150]
`
`3
`
`Vervain Ex. 2010, p. 3
`Micron v. Vervain
`IPR2021-01549
`
`

`

`EXHIBIT C-18
`INVALIDITY CLAIM CHART FOR THE ’240 PATENT
`BASED ON U.S. PATENT APPLICATION PUB. NO. US 2008/0140918 (“Sutardja”)
`
`
`
`[0167]
`
`
`Sutardja discloses and/or renders obvious wherein the controller is adapted to determine if a range of
`addresses listed by an entry and mapped to a similar range of physical addresses within the at least one
`MLC non-volatile memory module, fails a data integrity test
`
`See, e.g.,
`
`
`
`
`
`
`
`
`
`[0108]
`[0111]
`[0105]
`[0118]
`[0123]
`[0135]-[0137] (degradation module)
`
`
`
`
`
`[1.E.i] wherein the controller
`is adapted to determine if a
`range of addresses listed by
`an entry and mapped to a
`similar range of physical
`addresses within the at least
`one MLC non-volatile
`memory module, fails a data
`integrity test
`
`[1.E.ii] in the event of such a
`failure, the controller remaps
`the entry to the next available
`equivalent range of physical
`addresses within the at least
`one SLC non-volatile memory
`module
`
`[1.F.i] wherein the controller
`is further adapted to
`determine which of the blocks
`
`
`Sutardja discloses and/or renders obvious in the event of such a failure, the controller remaps the entry
`to the next available equivalent range of physical addresses within the at least one SLC non-volatile
`memory module
`
`See, e.g.,
`
`
`
`
`
`
`
`
`
`[0108]
`[0111]
`[0105]
`[0118]
`[0123]
`[0138] (wear leveling adjusted based on degradation)
`
`
`Sutardja discloses and/or renders obvious wherein the controller is further adapted to determine which
`of the blocks of the plurality of the blocks in the MLC and SLC non-volatile memory modules are
`accessed most frequently
`
`4
`
`Vervain Ex. 2010, p. 4
`Micron v. Vervain
`IPR2021-01549
`
`

`

`EXHIBIT C-18
`INVALIDITY CLAIM CHART FOR THE ’240 PATENT
`BASED ON U.S. PATENT APPLICATION PUB. NO. US 2008/0140918 (“Sutardja”)
`
`of the plurality of the blocks
`in the MLC and SLC non-
`volatile memory modules are
`accessed most frequently
`
`[1.F.ii] wherein the controller
`segregates those blocks that
`receive frequent writes into
`the at least one SLC non-
`volatile memory module and
`those blocks that receive
`infrequent writes into the at
`least one MLC nonvolatile
`module
`
`[1.G] and [i] maintain a count
`value of the blocks in the
`MLC non-volatile memory
`module determined to have
`
`
`
`
`
`
`See, e.g.,
`
`
`
`[0106]
`
`[0108]
` Claim 37 (MLC and SLC)
`
`[0111], [0121] (storing count)
`
`[0118] (controller includes wear leveling module)
`
`[0146] (receive “write frequencies for logical addresses” from the host)
`
`[0147] (tracking actual counts)
`
`
`
`Sutardja discloses and/or renders obvious wherein the controller segregates those blocks that receive
`frequent writes into the at least one SLC non-volatile memory module and those blocks that receive
`infrequent writes into the at least one MLC nonvolatile module
`
`See, e.g.,
`
`
`
`[0106]
`
`[0108]
`
`[0118] (controller includes wear leveling module)
`
`[0146]-[0147]
` Claim 37 (MLC and SLC)
`
`[0167]
`
`
`See also claim limitation [1.G] and accompanying citations.
`
`Sutardja discloses and/or renders obvious and [i] maintain a count value of the blocks in the MLC
`non-volatile memory module determined to have received frequent writes and that are accessed most
`frequently [ii] on a periodic basis when the count value is a predetermined count value transfer the
`contents of the counted blocks in the MLC non-volatile memory module determined to have received
`
`5
`
`Vervain Ex. 2010, p. 5
`Micron v. Vervain
`IPR2021-01549
`
`

`

`EXHIBIT C-18
`INVALIDITY CLAIM CHART FOR THE ’240 PATENT
`BASED ON U.S. PATENT APPLICATION PUB. NO. US 2008/0140918 (“Sutardja”)
`
`received frequent writes and
`that are accessed most
`frequently [ii] on a periodic
`basis when the count value is
`a predetermined count value
`transfer the contents of the
`counted blocks in the MLC
`non-volatile memory module
`determined to have received
`frequent writes after reaching
`the predetermined count value
`to the SLC non-volatile
`memory module and [iii]
`which determined blocks in
`the SLC are determined in
`accordance with the next
`equivalent range of physical
`addresses determined by the
`controller.
`
`Claim 2
`[2] The system of claim 1,
`wherein the MLC and SLC
`each comprise flash
`memories.
`
`frequent writes after reaching the predetermined count value to the SLC non-volatile memory module
`and [iii] which determined blocks in the SLC are determined in accordance with the next equivalent
`range of physical addresses determined by the controller.
`
`See, e.g.,
`
`
`
`
`
`
`
`
`
`
`
`[0108]
`[0111]
`[0121] (storing count)
`[0123]
`[0146]-[0147] (measuring actual write counts)
`[0148]-[0149] (data shift analysis)
`[0152]-[0153] (wear level analysis)
`[0160]-[0163] (write cycle lifetime is constant)
`[0167] (swapping data)
`
`See also claim limitation [1.F.i] and accompanying citations.
`
`Disclosure in Sutardja
`Sutardja discloses and/or renders obvious the system of claim 1, wherein the MLC and SLC each
`comprise flash memories.
`
`See, e.g.,
`
`
`
`
`[0172], [0175]
`[0185]
`
`Claim 6
`[6.Pre] A system for storing
`data comprising:
`
`Disclosure in Sutardja
`To the extent the preamble is limiting, Sutardja discloses and/or renders obvious a system for storing
`data.
`
`6
`
`Vervain Ex. 2010, p. 6
`Micron v. Vervain
`IPR2021-01549
`
`

`

`EXHIBIT C-18
`INVALIDITY CLAIM CHART FOR THE ’240 PATENT
`BASED ON U.S. PATENT APPLICATION PUB. NO. US 2008/0140918 (“Sutardja”)
`
`[6.A] at least one MLC non-
`volatile memory module
`comprising a plurality of
`individually erasable blocks;
`
`[6.B] at least one SLC non-
`volatile memory module
`comprising a plurality of
`individually erasable blocks;
`
`[6.C] a controller coupled to
`the at least one MLC non-
`volatile memory module and
`the at least one SLC non-
`volatile memory module
`
`[6.D.i] the controller
`maintaining an address map
`of at least one of the MLC
`and SLC non-volatile memory
`modules, the address map
`comprising a list of logical
`address ranges accessible by a
`
`See, e.g.,
`
`
` Claim limitation [1.PRE] and accompanying citations
`
`
`Sutardja discloses and/or renders obvious at least one MLC non-volatile memory module comprising
`a plurality of individually erasable blocks;
`
`See, e.g.,
`
`
` Claim limitation [1.A] and accompanying citations
`
`
`Sutardja discloses and/or renders obvious at least one SLC non-volatile memory module comprising a
`plurality of individually erasable blocks;
`
`See, e.g.,
`
`
` Claim limitation [1.B] and accompanying citations
`
`
`Sutardja discloses and/or renders obvious a controller coupled to the at least one MLC non-volatile
`memory module and the at least one SLC non-volatile memory module
`
`See, e.g.,
`
`
` Claim limitation [1.C] and accompanying citations
`
`
`Sutardja discloses and/or renders obvious the controller maintaining an address map of at least one of
`the MLC and SLC non-volatile memory modules, the address map comprising a list of logical address
`ranges accessible by a computer system
`
`See, e.g.,
`
`
`7
`
`
`
`
`
`Vervain Ex. 2010, p. 7
`Micron v. Vervain
`IPR2021-01549
`
`

`

`EXHIBIT C-18
`INVALIDITY CLAIM CHART FOR THE ’240 PATENT
`BASED ON U.S. PATENT APPLICATION PUB. NO. US 2008/0140918 (“Sutardja”)
`
`computer system
`
`[6.D.ii] the list of logical
`address ranges having a
`minimum quanta of addresses
`
`[6.D.iii] wherein each entry in
`the list of logical address
`ranges maps to a similar range
`of physical addresses within
`either the at least one SLC
`non-volatile memory module
`or within the at least one
`MLC non-volatile memory
`module
`[6E] wherein the controller
`allocates those blocks that
`receive frequent writes into
`the SLC non-volatile memory
`module as hot blocks and
`those blocks that only receive
`infrequent writes into the
`MLC non-volatile memory
`module as cold blocks; and
`[6.F.i] wherein the controller
`is adapted to determine if a
`range of addresses listed by
`an entry and mapped to a
`similar range of physical
`
`
`
`
`
` Claim limitation [1.D] and accompanying citations
`
`
`Sutardja discloses and/or renders obvious the list of logical address ranges having a minimum quanta
`of addresses.
`
`See, e.g.,
`
`
` Claim limitation [1.D] and accompanying citations
`
`
`Sutardja discloses and/or renders obvious wherein each entry in the list of logical address ranges maps
`to a similar range of physical addresses within either the at least one SLC non-volatile memory
`module or within the at least one MLC non-volatile memory module
`
`See, e.g.,
`
`
` Claim limitation [1.D] and accompanying citations
`
`
`
`
`
`Sutardja discloses and/or renders obvious wherein the controller allocates those blocks that receive
`frequent writes into the SLC non-volatile memory module as hot blocks and those blocks that only
`receive infrequent writes into the MLC non-volatile memory module as cold blocks.
`
`See, e.g.,
`
`
` Claim limitation [1.F] and accompanying citations
`
`Sutardja discloses and/or renders obvious wherein the controller is adapted to determine if a range of
`addresses listed by an entry and mapped to a similar range of physical addresses within the at least one
`MLC non-volatile memory module, fails a data integrity test
`
`See, e.g.,
`
`8
`
`Vervain Ex. 2010, p. 8
`Micron v. Vervain
`IPR2021-01549
`
`

`

`EXHIBIT C-18
`INVALIDITY CLAIM CHART FOR THE ’240 PATENT
`BASED ON U.S. PATENT APPLICATION PUB. NO. US 2008/0140918 (“Sutardja”)
`
`addresses within the at least
`one MLC non-volatile
`memory module, fails a data
`integrity test, and,
`[6.F.ii] in the event of such a
`failure, the controller remaps
`the entry to the next available
`equivalent range of physical
`addresses within the at least
`one SLC non-volatile memory
`module;
`
`[6.G] wherein the controller is
`further adapted to [i] maintain
`a count value of those blocks
`that are accessed most
`frequently, and, [ii] on a
`periodic basis when the count
`value is a predetermined
`count value, transfer the
`contents of those counted
`blocks into the SLC non-
`volatile memory module, [iii]
`wherein the counted blocks
`transferred to after reaching
`the predetermined count value
`are determined in accordance
`with the next equivalent range
`of physical addresses
`determined by the controller.
`Claim 7
`The system of claim 6,
`
` Claim limitation [1.E] and accompanying citations
`
`Sutardja discloses and/or renders obvious in the event of such a failure, the controller remaps the entry
`to the next available equivalent range of physical addresses within the at least one SLC non-volatile
`memory module
`
`See, e.g.,
`
` Claim limitation [1.E] and accompanying citations
`
`Sutardja discloses and/or renders obvious wherein the controller is further adapted to [i] maintain a
`count value of those blocks that are accessed most frequently, and, [ii] on a periodic basis when the
`count value is a predetermined count value, transfer the contents of those counted blocks into the SLC
`non-volatile memory module, [iii] wherein the counted blocks transferred to after reaching the
`predetermined count value are determined in accordance with the next equivalent range of physical
`addresses determined by the controller.
`
`See, e.g.,
`
` Claim limitation [1.G] and accompanying citations
`
`Disclosure in Sutardja
`Sutardja discloses and/or renders obvious the system of claim 6, wherein the MLC and SLC each
`
`9
`
`Vervain Ex. 2010, p. 9
`Micron v. Vervain
`IPR2021-01549
`
`

`

`EXHIBIT C-18
`INVALIDITY CLAIM CHART FOR THE ’240 PATENT
`BASED ON U.S. PATENT APPLICATION PUB. NO. US 2008/0140918 (“Sutardja”)
`
`wherein the MLC and SLC
`each comprise flash
`memories.
`
`comprise flash memories.
`
`See, e.g.,
`
` Claim limitation [2] and accompanying citations
`
`10
`
`Vervain Ex. 2010, p. 10
`Micron v. Vervain
`IPR2021-01549
`
`