( 12 ) United States Patent
`Rao
`
`US 10,950,300 B2
`( 10 ) Patent No .:
`( 45 ) Date of Patent :
`Mar. 16 , 2021
`
`USO10950300B2
`
`( 54 ) LIFETIME MIXED LEVEL NON - VOLATILE
`MEMORY SYSTEM
`( 71 ) Applicant : VERVAIN , LLC , Dallas , TX ( US )
`( 72 ) Inventor : G. R. Mohan Rao , Allen , TX ( US )
`( 73 ) Assignee : Vervain , LLC , Dallas , TX ( US )
`Subject to any disclaimer , the term of this
`( * ) Notice :
`patent is extended or adjusted under 35
`U.S.C. 154 ( b ) by 0 days .
`( 21 ) Appl . No .: 16 / 006,299
`( 22 ) Filed :
`Jun . 12 , 2018
`( 65 )
`Prior Publication Data
`US 2018/0294029 A1
`Oct. 11 , 2018
`
`Related U.S. Application Data
`( 60 ) Continuation of application No. 14 / 950,553 , filed on
`Nov. 24 , 2015 , now Pat . No. 9,997,240 , which is a
`( Continued )
`
`( 51 ) Int . Ci .
`GIIC 11/56
`GO6F 12/02
`
`( 2006.01 )
`( 2006.01 )
`( Continued )
`
`( 52 ) U.S. Ci .
`CPC
`
`GIIC 11/5635 ( 2013.01 ) ; G06F 11/1068
`( 2013.01 ) ; G06F 11/1072 ( 2013.01 ) ;
`( Continued )
`( 58 ) Field of Classification Search
`G06F 11/1068 ; G06F 11/1072 ; G06F
`CPC
`12/0246 ; G06F 2212/7202 ; G11C
`
`( 56 )
`
`11/5621 ; G11C 11/5635 ; G11C 11/5678 ;
`G11C 16/16 ; G11C 16/3495 ; G11C
`29/52 ; G11C 29/79 ; G11C 2211/5641
`See application file for complete search history .
`References Cited
`U.S. PATENT DOCUMENTS
`3/2009 Lee
`7,505,338 B2 *
`7,855,916 B2 12/2010 Rao
`( Continued )
`
`G11C 11/5621
`365 / 185.09
`
`OTHER PUBLICATIONS
`Goodson et al , “ Design Tradeoffs in a Flash Translation Layer . "
`( Year : 2010 ) . *
`
`( Continued )
`Primary Examiner Richard Elms
`Assistant Examiner R Lance Reidlinger
`( 74 ) Attorney , Agent , or Firm - Bill R. Naifeh
`( 57 )
`ABSTRACT
`A flash controller for managing at least one MLC non
`volatile memory module and at least one SLC non - volatile
`memory module . The flash controller is adapted to deter
`mine if a range of addresses listed by an entry and mapped
`to said at least one MLC non - volatile memory module fails
`a data integrity test . In the event of such a failure , the
`controller remaps said entry to an equivalent range of
`addresses of said at least one SLC non - volatile memory
`module . The flash controller is further adapted to determine
`which of the blocks in the MLC and SLC non - volatile
`memory modules are accessed most frequently and allocat
`ing those blocks that receive frequent writes to the SLC
`non - volatile memory module and those blocks that receive
`infrequent writes to the MLC non - volatile memory module .
`12 Claims , 5 Drawing Sheets
`
`Compare Data Written to
`NAND FLASH Physical
`Address Range to Data Reaci
`from NAND FLASH Physical
`Address Range
`
`No
`
`Match ?
`
`116
`
`Success
`
`115
`
`System
`
`124
`
`100
`
`W - 1
`
`120 )
`
`Identify next
`quantur of
`available SI
`NAND flash
`
`106
`
`108
`
`1 22
`
`Available ?
`
`Yes
`
`Remap NAND fash
`physical range to
`next available SLO
`NAND flash
`
`126
`
`Road data quanlura
`frorn DRAM to memory
`of device controller
`
`Read logical address
`tange and NAND flash
`Playsical address tange
`to which data quantuin
`is to be written into
`memory of device
`controller
`
`Combine contents of
`NAND flash 1070TY
`with data quanturn to be
`written
`
`TOSA NAND flash
`physical address range
`
`appropriate NAND Cash
`pbysical range
`
`Read NAND Flash
`physical address range
`Into device controller
`117 + 7Y
`
`M - 1
`
`M - 2
`
`Vervain Ex. 2004, p. 1
`Micron v. Vervain
`IPR2021-01549
`
`

`

`US 10,950,300 B2
`Page 2
`
`Related U.S. Application Data
`continuation of application No. 14 / 525,411 , filed on
`Oct. 28 , 2014 , now Pat . No. 9,196,385 , which is a
`division of application No. 13 / 455,267 , filed on Apr.
`25 , 2012 , now Pat . No. 8,891,298 .
`
`( 60 ) Provisional application No. 61 / 509,257 , filed on Jul .
`19 , 2011 .
`( 51 ) Int . Ci .
`GIIC 16/34
`G06F 11/10
`GIIC 29/52
`GIIC 29/00
`G11C 16/16
`( 52 ) U.S. Cl .
`CPC
`
`( 2006.01 )
`( 2006.01 )
`( 2006.01 )
`( 2006.01 )
`( 2006.01 )
`G06F 12/0246 ( 2013.01 ) ; GIIC 11/5621
`( 2013.01 ) ; GIIC 11/5678 ( 2013.01 ) ; GIIC
`16/16 ( 2013.01 ) ; GIIC 16/3495 ( 2013.01 ) ;
`GIIC 29/52 ( 2013.01 ) ; GIIC 29/76 ( 2013.01 ) ;
`GO6F 2212/7202 ( 2013.01 ) ; GIIC 2211/5641
`( 2013.01 )
`
`( 56 )
`
`References Cited
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`3/2012 Miyachi
`8,140,800 B2 *
`9/2014 Moshayedi et al .
`8,825,941 B2
`8,891,298 B2
`11/2014 Rao
`9,196,385 B2
`11/2015 Roa
`6/2018 Rao
`9,997,240 B2
`2008/0181000 A1 *
`7/2008 Lasser
`
`7/2009 Oribe
`2009/0172267 A1 *
`2009/0268513 A1 * 10/2009 De Ambroggi
`2009/0307418 A1 * 12/2009 Chen
`12/2009 Moshayedi
`3/2010 Kund
`
`2009/0327591 Al
`2010/0058018 A1 *
`
`2010/0172179 A1 *
`
`7/2010 Gorobets
`
`2010/0325352 Al
`2011/0050870 A1
`2011/0060870 A1
`2011/0271043 Al
`
`12/2010 Schuette et al .
`3/2011 Hanari
`3/2011 Rao
`11/2011 Segal et al .
`
`G06F 11/1076
`711/165
`
`G11C 11/5628
`365 / 185.03
`G11C 16/3418
`711/103
`G11C 11/005
`365/163
`G06F 11/1048
`711/105
`
`G11C 7/04
`711/167
`GOOF 12/0246
`365 / 185.09
`
`OTHER PUBLICATIONS
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`Random Access Memory ( DRAM ) , IEEE Transactions on Electron
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`Memory With 24 - WL Stacked Layers and 50 MB / s High - Speed
`Programming ; IEEE Jounral of Solid - State Circuits , vol . 50 , No. 1 ,
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`Resnati , et al . , Temperature Effects in NAND Flash Memories : A
`Comparison Between 2 - D and 3 - D Arrays ; IEEE Electron Device
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`Cho et al . , An Innovative Indicator to Evaluate DRAM Cell Tran
`sistor Leakage Current Distribution ; Journal of Electron Devices
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`Frank Shu , The Myth of SSD Testing , Flash Memory Summit 2011 ,
`Santa Clara , CA.
`Bacchini et al . , Characterization of Data Retention Faults in DRAM
`Devices , Nov. 2014 .
`
`Micheloni et al . , Architectural and Integration Options for 3D
`NAND Flash Memories , Computers 2017 , 6 , 27 .
`James Myers , Data Integrity in Solid State Drives : What Superno
`vas Mean to You , IT Peer Network , Feb. 19 , 2014 .
`Bhati et al . , DRAM Refresh Mechanisms , Penalties , and Trade - Offs ,
`IEEE Transactions on Computers , vol . 64 , No. X , 2015 .
`Doug Rollins , SSD Enhancements : Protecting Data Integrity and
`Improving Responsiveness , Industry Perspectives , Jul . 30 , 2014 .
`Luo et al . , WARM : Improving NAND Flash Memory Lifetime with
`Write - hotness Aware Retention Management , IEEE , 2015 .
`Intel , Understanding the Flash Translation Layer ( FTL ) Specifica
`tion , Dec. 1998 .
`Tae - Sun Chung et al . , A Survey of Flash Translation Layer , Journal
`of Systems Architecture 55 , pp . 332-343 , 2009 .
`Seagate Technology LLC , The Transition to Advanced Format 4K
`Sector Hard Drives , Apr. 2010 .
`Roberto Bez et al . , Introduction to Flash Memory , Proceedings of
`the IEEE , vol . 91 , No. 4 , Apr. 2003 .
`Qingsing Wei et al . , WAFTL : A Workload Adaptive Flash Transla
`tion Layer with Data Partition , IEEE 27th Symposium on Massive
`Storage Systems and Technologies ( MSST ) , May 23-27 , 2011 .
`Taeho Kgil et al . , Improving NAND Flash Based Disk Caches ,
`International Symposium on Computer Architecture , Copyright
`2008 IEEE .
`Samsung Electronics Co. , Ltd. , 7th International Symposium on
`Advanced Gate Stack Technology , RPAM Technology from an
`Industrial Perspective , Process Development Team / RPAM PJT In
`Gyu Baek , Sep. 2010 .
`Paolo Pavan et al . , Flash Memory Cells — An Overview , Proceed
`ings of the IEEE , vol . 85 , No. 8 , Aug. 1997 .
`Yoshihisa Iwata et al . , A High - Density NAND EEPROM with
`Block - Page Programming for Microcomputer Applications , IEEE
`Journal of Solid - State Circuits , vol . 25 , No. 2 , Apr. 1990 .
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`NAND Flash Memory for Mass Storage Applications , IEEE Journal
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`Memory with FN - NOR Type Four - Level Cell , IEEE Journal of
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`Multilevel and High - Performance 512 - Mb Single - Level Modes ,
`IEEE Journal of Sold - State Circuits , vol . 36 , No. 11 , Nov. 2001 .
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`erations for High - Density 5 V - Only E2PROM's , IEEE Journal of
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`Polysilicon Technology , IEEE Journal of Sold - State Circuits , vol .
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`MIC Hybrid , Santa Clara , CA , Aug. 2008 .
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`ments and Analysis , Usenix Conference on File and Storage Tech
`nologies , San Jose , CA , Feb. 2010 .
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`ments and Analysis , Handout at Usenix Conference on File and
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`com , Apr. 2005 .
`Ismael Change Chalimi , Intalio , An Intalio White Paper , Cloud
`Computing is Memory Bound , May 2010 .
`
`Vervain Ex. 2004, p. 2
`Micron v. Vervain
`IPR2021-01549
`
`

`

`US 10,950,300 B2
`Page 3
`
`( 56 )
`
`References Cited
`OTHER PUBLICATIONS
`Hynix , 32Gb NAND Flash , HY27UK08BGFM , Product Descrip
`tion Sheet , Feb. 2007 .
`Chris Evans , Consultant with Langton Blue , SearchStorage.co.UK ,
`Enterprise MLC ; How flash vednors are boosting MLC write
`endurance , Jun . 3 , 2011 .
`Jesung Kim et al . , A Space - Efficient Flash Translation Layer for
`Compactflash Systems , IEEE Transactions on Consumer Electron
`ics , vol . 48 , No. 2 , May 2002 .
`Garth Goodson et al . , Design Tradeoffs in a Flash Translation Layer ,
`HPCA West 2010 ( High Perf Comp Arch Conference , Bangalore ,
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`tems , Spring 2009 .
`Ynag Hu , Achieving Page - Mapping FTL Performance at Block
`Mapping FTL Cost by Hiding Address Translation , 26th EIII
`Symposium on Massive Storage Systems and Technologies ( MSST )
`May 3-7 , 2010 .
`Clinton W. Smullen , IV et al . , Accelerating Enterprise Sold - State
`Disks with Non - Volatile Merge Caching , 2010 International Green
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`Monolithic 3D , Inc. Introducing our monolithic 3D resistive memory
`architecture , http://www.monolithic3d.com/2/post/2011/06/introducing
`our - 3d - resistive - memory - architecture.html , Jun . 27 , 2011 .
`
`Song Jiang et al . , S - FTL : An Efficient Address Translation for Flash
`Memory by Exploiting Spatial Locality , Proceedings of the MSST
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`Greg Atwood et al . , Intel Strata Flash TM Memory Technology
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`L2ARC : Second Level Adaptive Replacement Cache , Oracle White
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`
`* cited by examiner
`
`Vervain Ex. 2004, p. 3
`Micron v. Vervain
`IPR2021-01549
`
`

`

`U.S. Patent
`
`Mar. 16 , 2021
`
`Sheet 1 of 5
`
`US 10,950,300 B2
`
`12
`
`Processor
`
`20
`
`14
`
`DRAM
`
`Device
`Controller
`
`16
`
`18
`
`I / O
`
`I / O
`
`Disk ( s )
`
`24
`
`flash
`
`SLC
`flash
`
`( e . £ . , rotating media -
`magnetic or optical )
`
`26
`
`28
`
`FIG . 1
`
`Vervain Ex. 2004, p. 4
`Micron v. Vervain
`IPR2021-01549
`
`

`

`U.S. Patent
`
`Mar. 16 , 2021
`
`2
`
`Sheet 2 of 5
`
`US 10,950,300 B2
`
`LOGICAL
`ADDRESS RANGE
`
`PHYSICAL
`ADDRESS RANGE
`
`RO
`
`MLC / Block 0
`
`Failed Data
`Integrity Test
`
`3
`{
`
`TITE
`
`R2
`
`R3
`
`R4
`
`RN
`
`MLC / Block 1
`
`R
`
`POT
`
`MLC / Block 2
`
`MLC / Block 3
`
`MLC / Block 4
`
`MLC / Block N
`
`FIG . 2A
`
`LOGICAL
`ADDRESS RANGE
`
`PHYSICAL
`ADDRESS RANGE
`
`RO
`
`R1
`
`Remapping to SLO
`flash module
`
`}
`}
`
`R2
`
`R3
`
`R4
`
`RN
`
`MLC / Block 0
`
`MLC / Block 1
`
`u
`
`SLC / Block 0
`
`MLC / Block 3
`
`MLC / Block 4
`
`MLC / Block N
`
`FIG.2B
`
`Vervain Ex. 2004, p. 5
`Micron v. Vervain
`IPR2021-01549
`
`

`

`U.S. Patent
`
`Mar. 16 , 2021
`
`Sheet 3 of 5
`
`US 10,950,300 B2
`
`????????
`
`Begin
`
`100
`
`Read data quantum
`from DRAM into memory
`of device controller
`
`Read logical address
`range and NAND flash
`physical address range
`to which data quantum
`is to be written into
`memory of device
`controller
`
`Combine contents of
`NAND flash memory
`with data quantum to be
`written
`
`Erase NAND flash
`physical address range
`
`106
`
`108
`
`M - 2
`
`Write combined data to
`appropriate NAND flash
`physical range
`
`Read NAND Flash
`physical address range
`into device controller
`mernory
`
`112
`
`FIG . 3A
`
`Vervain Ex. 2004, p. 6
`Micron v. Vervain
`IPR2021-01549
`
`

`

`U.S. Patent
`
`Mar. 16 , 2021
`
`Sheet 4 of 5
`
`US 10,950,300 B2
`
`M - 1
`
`Compare Data Written to
`NAND FLASH Physical
`Address Range to Data Read
`from NAND FLASH Physical
`Address Range
`
`114
`
`No
`
`Match ?
`
`116
`
`120
`
`Identify next
`quantum of
`available SLC
`NAND flash
`
`122
`
`Yes
`
`Success
`
`118
`
`Available ?
`
`No
`
`System
`Failure
`
`124
`
`Yes
`
`Remap NAND flash
`physical range to
`next available SLC
`NAND flash
`
`126
`
`M - 2
`
`FIG . 3B
`
`Vervain Ex. 2004, p. 7
`Micron v. Vervain
`IPR2021-01549
`
`

`

`U.S. Patent
`
`Mar. 16 , 2021
`
`Sheet 5 of 5
`
`US 10,950,300 B2
`
`50
`
`60a
`
`62a
`
`54
`
`MLC
`
`MLC
`
`MLC
`
`MLC
`
`MLC
`
`MLC
`
`MLC
`
`SLC
`
`1
`
`t
`
`SLC
`
`MLC
`
`MLC
`
`ruHub
`
`.
`
`an
`
`MLC
`
`MLC
`
`MLC
`
`MLC
`
`MLC
`
`1
`
`$
`
`4
`
`MLC
`
`SLC
`
`? I
`
`}
`
`I
`1
`
`I
`
`SLC
`
`Interface
`
`FIG . 4
`
`60b
`
`62b
`
`58
`
`52
`
`Vervain Ex. 2004, p. 8
`Micron v. Vervain
`IPR2021-01549
`
`

`

`US 10,950,300 B2
`
`1
`LIFETIME MIXED LEVEL NON - VOLATILE
`MEMORY SYSTEM
`
`2
`stored data even when not powered . Magnetic ( rotating )
`hard disk drives ( HDD ) dominate this storage medium due
`to lower cost compared to solid state disks ( SSD ) . Optical
`( rotating ) disks , tape drives and others have a smaller role in
`CROSS - REFERENCE TO RELATED
`5 long - term storage systems . SSDs are preferred for their
`APPLICATIONS
`superior performance ( fast access time ) , mechanical reliabil
`This application is a Continuation of U.S. patent appli
`ity and ruggedness , and portability . Flash memory , more
`cation Ser . No. 14 / 950,553 filed on Nov. 24 , 2015 , entitled
`specifically NAND flash , is the dominant SSD medium
`LIFETIME MIXED LEVEL NON - VOLATILE MEMORY today .
`SYSTEM , which published on Jun . 2 , 2016 , as U.S. Appli
`RRAM , PCM , MAGRAIVI and others , will likely play a
`10
`cation Publication No. 2016-0155496 , now U.S. Pat . No.
`larger role in the future , each of them having their own
`9,997,240 issued Jun . 12 , 2018 , which is incorporated by
`advantages and disadvantages . They may ultimately replace
`reference in its entirety . U.S. application Ser . No. 14/950 ,
`flash memories , initially for use as a “ write buffer ” and later
`553 is a Continuation of U.S. patent application Ser . No.
`to replace “ SLC flash ” and “ MLC flash . ” MLC NAND flash
`14 / 525,411 , filed Oct. 28 , 2014 , entitled LIFETIME MIXED
`LEVEL NON - VOLATILE MEMORY SYSTEM , which 15 is a flash memory technology using multiple levels per cell
`published on Oct. 1 , 2015 , as U.S. Publication No. 2015-
`to allow more bits to be stored using the same number of
`0278013 , now U.S. Pat . No. 9,196,385 , issued on Nov. 24 ,
`transistors . In SLC NAND flash technology , each cell can
`2015. Application Ser . No. 14 / 525,411 is a Division of U.S.
`exist in one of two states , storing one bit of information per
`patent application Ser . No. 13 / 455,267 , filed Apr. 25 , 2012 ,
`cell . Most MLC NAND flash memory has four possible
`published on Jan. 24 , 2013 , as U.S. Publication No. 2013- 20 states per cell , so it can store two bits of information per cell .
`0021846 , now U.S. Pat . No. 8,891,298 , issued on Nov. 18 ,
`These semiconductor technology driven “ flash alterna
`2014 , entitled LIFETIME MIXED LEVEL NON - VOLA-
`tives , " i.e. , RRAM , PCM , MAGRAIVI and others , have
`TILE MEMORY SYSTEM . Application Ser . No. 13/455 ,
`several advantages over any ( SLC or MLC ) flash because
`267 claims the benefit of U.S. Provisional Application No.
`they : 1 ) allow data to be written over existing data ( without
`61 / 509,257 , filed Jul . 19 , 2011 , entitled LIFETIME MIXED 25 prior erase of existing data ) , 2 ) allow for an erase of
`LEVEL NAND FLASH SYSTEM . U.S. Pat . Nos . 9,997 ,
`individual bytes or pages ( instead of having to erase an
`240 ; 9,196,385 ; and 8,891,298 and Patent Application Pub
`entire block ) , and 3 ) possess superior endurance ( 1,000,000
`lication Nos . 2015-0278013 and 2013-0021846 are hereby
`write - erase cycles compared to typical 100,000 cycles for
`incorporated by reference in their entirety . This application
`SLC flash and less than 10,000 cycles for MLC flash ) .
`also incorporates by reference the complete disclosure of
`HDDs have several platters . Each platter contains 250-5 ,
`U.S. patent application Ser . No. 12 / 256,362 , filed Oct. 22 ,
`000 tracks ( concentric circles ) . Each track contains 64 to 256
`2008 , published on Apr. 30 , 2009 , as U.S. Publication No.
`sectors . Each sector contains 512 bytes of data and has a
`2009-0109787 , now U.S. Pat . No. 7,855,916 , issued on Dec.
`unique “ physical ( memory ) address . ” A plurality of sectors
`21 , 2010 , entitled NONVOLATILE MEMORY SYSTEMS
`WITH EMBEDDED FAST READ AND WRITE MEMO- is typically combined to form a “ logical block ” having a
`RIES . This application also incorporates by reference the 35 unique “ logical address . ” This logical address is the address
`at which the logical block of physical sectors appears to
`complete disclosure of U.S. patent application Ser . No.
`12 / 915,177 , filed Oct. 29 , 2010 , published on Mar. 10 , 2011 ,
`reside from the perspective of an executing application
`as U.S. Publication No. 2011-0060870 , now U.S. Pat . No.
`program . The size of each logical block and its logical
`8,194,452 , issued on Jun . 5 , 2012 , entitled NONVOLATILE
`address ( and / or address ranges / boundaries ) is optimized for
`MEMORY SYSTEMS WITH EMBEDDED FAST READ 40 the particular operating system ( OS ) and software applica
`tions executed by the host processor . A computer OS orga
`AND WRITE MEMORIES .
`nizes data as “ files . ” Each file may be located ( stored ) in
`TECHNICAL FIELD
`either a single logical block or a plurality of logical blocks ,
`and therefore , the location of files typically traverses the
`This application relates to a system and method for 45 boundaries of individual ( physical ) sectors . Sometimes , a
`providing reliable storage through the use of non - volatile
`plurality of files has to be combined and / or modified , which
`memories and , more particularly , to a system and method of
`poses an enormous challenge for the memory controller
`increasing the reliability and lifetime of a NAND flash
`device of a non - volatile memory system .
`storage system , module , or chip through the use of a
`SSDs are slowly encroaching on the HDD space and the
`combination of single - level cell ( SLC ) and multi - level cell
`( MLC ) NAND flash storage without substantially raising the 50 vast majority of NAND flash in enterprise servers utilizes a
`SLC architecture , which further comprises a NAND flash
`cost of the NAND flash storage system . The memory in a
`total non - volatile memory system may contain some SRAM controller and a flash translation layer ( FTL ) . NAND flash
`( static random - access memory ) , DRAM ( dynamic RAM ) ,
`devices are generally fragmented into a number of identi
`cally sized blocks , each of which is further segmented into
`RRAM ( resistive RAM ) , PCM ( phase change memory ) ,
`MAGRAM ( magnetic random - access memory ) , NAND 55 some number of pages . It should be noted that asymmetrical
`flash , and one or more HDDs ( hard disk drives ) when
`block sizes , as well as page sizes , are also acceptable within
`storage of the order of several terabytes is required . The SLC
`a device or a module containing devices . For example , a
`be flash , PCM , RRAM ,
`block may comprise 32 to 64 pages , each of which incor
`non - volatile memory
`can
`MAGRAM or any other solid - state non - volatile memory as
`porates 2-4 Kbit of memory . In addition , the process of
`long as it has endurance that is superior to that of MLC flash , 60 writing data to a NAND flash memory device is complicated
`and it provides for data access speeds that are faster than that
`by the fact that , during normal operation of , for example ,
`of MLC flash or rotating storage media ( e.g. , HDDs ) .
`single - level storage ( SLC ) , erased bits ( usually all bits in a
`block with the value of ' 1 ' ) can only be changed to the
`opposite state ( usually ‘ O ' ) once before the entire block must
`BACKGROUND
`65 be erased . Blocks can only be erased in their entirety , and ,
`when erased , are usually written to‘l ' bits . However , if an
`Non - volatile memories provide long - term storage of data .
`erased block is already there , and if the addresses ( block ,
`More particularly , non - volatile memories can retain the
`
`30
`
`Vervain Ex. 2004, p. 9
`Micron v. Vervain
`IPR2021-01549
`
`

`

`US 10,950,300 B2
`
`3
`4
`flash storage system that provides long lifetime ( endurance )
`page , etc. ) are allowed , data can be written immediately ; if
`storage at low cost are described herein .
`not , a block has to be erased before it can be written to .
`The following description is presented to enable one of
`FTL is the driver that works in conjunction with an
`ordinary skill in the art to make and use the disclosure and
`existing operating system ( or , in some embedded applica-
`is provided in the context of a patent application and its
`tions , as the operating system ) to make linear flash memory 5
`appear to the system like a disk drive , i.e. , it emulates a
`requirements . Various modifications to the preferred
`HDD . This is achieved by creating “ virtual ” small blocks of
`embodiment and the generic principles and features
`data , or sectors , out of flash's large erase blocks and man described herein will be readily apparent to those skilled in
`aging data on the flash so that it appears to be “ write in
`the art . Thus , the present disclosure is not intended to be
`place ” when in fact it is being stored in different locations in 10 limited to the embodiments shown , but is to be accorded the
`the flash . FTL further manages the flash so that there are
`widest scope consistent with the principles and features
`clean / erased places to store data .
`described herein .
`Given the limited number of writes that individual blocks
`within flash devices can tolerate , wear leveling algorithms
`SUMMARY
`are used within the flash devices ( as firmware commonly 15
`known as FTL or managed by a controller ) to attempt to
`According to one embodiment of the present disclosure ,
`ensure that “ hot ” blocks , i.e. , blocks that are frequently
`there is provided a system for storing data which comprises
`written , are not rendered unusable much faster than other
`at least one MLC nonvolatile memory module ( hereinafter
`blocks . This task is usually performed within a flash trans
`lation layer . In most cases , the controller maintains a lookup 20 referred to as “ MLC module ” ) and at least one SLC non
`volatile memory module ( hereinafter referred to as “ SLC
`table to translate the memory array physical block address
`( PBA ) to the logical block address ( LBA ) used by the host
`module " ) , each module comprises a plurality of individually
`system . The controller's wear - leveling algorithm determines
`erasable blocks . The data storage system according to one
`which physical block to use each time data is programmed ,
`embodiment of the present disclosure further comprises a
`eliminating the relevance of the physical location of data and 25 controller for controlling both the at least one MLC module
`enabling data to be stored anywhere within the memory
`and the at least one SLC module . In particular , the controller
`array and thus prolonging the service life of the flash
`maintains an address map comprising a list of individual
`memory . Depending on the wear - leveling method used , the
`logical address ranges each of which maps to a similar range
`controller typically either writes to the available erased
`of physical addresses within either the at least one MLC
`block with the lowest erase count ( dynamic wear leveling ) ; 30 module or the at least one SLC module . After each write to
`or it selects an available target block with the lowest overall
`( flash ) memory , the controller conducts a data integrity
`erase count , erases the block if necessary , writes new data to
`check to ensure that the data was written correctly . When the
`the block , and ensures that blocks of static data are moved
`data was not written correctly , the controller modifies the
`when their block erase count is below a certain threshold
`table so that the range of addresses on which the write failed
`( static wear leveling ) .
`35 is remapped to the next available range of physical addresses
`MLC NAND flash SSDs are slowly replacing and / or
`within the at least one SLC module . The SLC module can be
`coexisting with SLC NAND flash in newer SSD systems .
`( NAND ) flash , PCM , RRAM , MAGRAIVI or any other
`MLC allows a single cell to store multiple bits , and accord-
`solid - state non - volatile memory as long as it has endurance
`ingly , to assume more than two values ; i.e. , ' O ' or ' 1 ' . Most
`that is superior to that of MLC flash , and it provides for data
`MLC NAND flash architectures allow up to four ( 4 ) values 40 access speeds that are faster than that of MLC flash or
`per cell ; i.e. ,
`' 00 ' ,
`' 01 ' ,
`' 10 ' , or ' 11 ' . Generally , MLC rotating storage media ( e.g. , HDDs ) .
`NAND flash enjoys greater density than SLC NAND flash ,
`According to another embodiment of the present disclo
`at the cost of a decrease in access speed and lifetime
`sure , there is provided a system for storing data which
`( endurance ) . It should be noted , however , that even SLC
`comprises a controller that is further adapted to determine
`NAND flash has a considerably lower lifetime ( endurance ) 45 which of the blocks of the plurality of the blocks in the MLC
`than rotating magnetic media ( e.g. , HDDs ) , being able to
`and SLC non - volatile memory modules are accessed most
`withstand only between 50,000 and 100,000 writes , and
`frequently and wherein the controller segregates those
`MLC NAND flash has a much lower lifetime ( endurance )
`blocks that receive frequent writes into the at least one SLC
`than SLC NAND flash , being able to withstand only
`non - volatile memory module and those blocks that receive
`between 3,000 and 10,000 writes . As is well known in the 50 infrequent writes into the at least one MLC nonvolatile
`art , any " write ” or “ program ” to a block in NAND flash
`module .
`( floating gate ) requires an “ erase ” ( of a block ) before
`" write . "
`BRIEF DESCRIPTION OF THE DRAWINGS
`Despite its limitations , there are a number of applications
`that lend themselves to the use of MLC flash . Generally , 55
`The present disclosure will be more fully understood by
`MLC flash is used in applications where data is read many
`reference to the following detailed description of one or
`times ( but written few times ) and physical size is an issue .
`more preferred embodiments when read in conjunction with
`For example , flash memory cards for use in digital cameras
`the accompanying drawings , in which like reference char
`would be a good application of MLC flash , as MLC can
`acters refer to like parts throughout the views and in which :
`provide higher density memory at lower cost than SLC 60
`FIG . 1 is a block diagram of a computer system incor
`porating one embodiment of the present disclosure ;
`memory .
`When a non - volatile storage system combines HDD , SLC
`FIGS . 2A and 2B are drawings depicting a translation
`table / address map in accordance with one embodiment of
`and MLC ( setting aside volatile memory for buffering ,
`caching etc ) in a single ( hybrid ) system , new improvements
`the present disclosure ;
`and solutions are required to manage the methods of writing 65
`FIGS . 3A and 3B are a flow chart illustrating an exem
`data optimally for improved life time ( endurance ) of flash
`plary method for use in implementing one embodiment of
`memory . Accordingly , various embodiments of a NAND the present disclosure ; and
`
`Vervain Ex. 2004, p. 10
`Micron v. Vervain
`IPR2021-01549
`
`

`

`US 10,950,300 B2
`
`5
`FIG. 4 is a block diagram depicting one embodiment of
`the present disclosure for implementation within a NAND
`flash module.
`
`DETAILED DESCRIPTION
`
`Thepresent disclosure is directed to the reliable storage of
`data in read and write memory, and, in particular, to the
`reliable storage of data in non-volatile memory, such as, for
`example, NAND flash. Generally, and in particular regard to
`NANDflash memory, two separate banks of NAND flash
`are maintained by a controller. One bank contains economi-
`cal MLC NANDflash, while a second bank contains high
`endurance SLC NANDflash. The controller conducts a data
`
`integrity test after every write. If a particular address range
`fails a data integrity test, the address range is remapped from
`MLC NANDflash to SLC NANDflash. As the SLC NAND
`
`flash is used to boostthe lifetime (endurance) of the storage
`system,
`it can be considerably lesser in amount than the
`MLC NANDflash. For example, a system may set SLC
`NANDflash equal to 12.5% or 25% of MLC NANDflash
`(total non-volatile memory storage space=MLC+SLC).
`Tuming to the Figures and to FIG. 1 in particular, a
`computer system 10 depicting one embodimentof the pres-
`ent disclosure is shown. A processor 12 is coupled to a
`device controller 14, such as a chipset, using a data link well
`knownin the art, such as a parallel bus or packet-based link.
`The device controller 14 provides interface functions to the
`processor 12. In some computer systems, the device con-
`troller 14 may be an integral part of the (host) processor 12.
`The device controller 14 provides a numberof input/output
`ports 16 and 18, such as, for example, serial ports (e.g., USB
`ports and Firewire ports) and network ports (e.g., Ethernet
`ports and 802.11 “Wi-Fi” ports). The device controller 14
`may also control a bank of, for example, DRAM 20. In
`addition, the device controller 14 controls access to one or
`more disks 24, such as, for example, a rotating magnetic
`disk, or an optical disk, as well as two or more types of
`NANDflash memory. One type of NAND flash memory is
`a MLC NANDflash memory module 26. Another type of
`NANDflash memory is a SLC NANDflash memory module
`28.
`The device controller 14 maintains a translation table/
`
`address map which may include address translations for all
`devices in the computer syste