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`UNITED STATES PATENT AND TRADEMARK OFFICE
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`MICRON TECHNOLOGY, INC.,
`Petitioner,
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`v.
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`VERVAIN, LLC,
`Patent Owner.
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`
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`IPR2021-01549
`U.S. Patent No. 9,997,240
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`DECLARATION OF SUNIL P. KHATRI
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`Vervaiin Ex. 2001, p. 1
`Micron v. Vervaiin
`IPR2021-01549
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`TABLE OF CONTENTS
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`INTRODUCTION ...............................................................................................................1
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`BACKGROUND AND QUALIFICATIONS .....................................................................1
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`SCOPE OF ASSIGNMENT AND MATERIALS CONSIDERED ..................................10
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`PERSON OF ORDINARY SKILL IN THE ART .............................................................12
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`RELEVANT
`THE
`BACKGROUND OF
`GENERAL
`TECHNOLOGY ................................................................................................................13
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`A.
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`B.
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`C.
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`D.
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`SLC and MLC Flash ..............................................................................................16
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`Address Table ........................................................................................................17
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`Data Integrity Tests ................................................................................................18
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`Hot and Cold Data .................................................................................................18
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`THE PATENTS-IN-SUIT .................................................................................................18
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`TECHNICAL OPINIONS .................................................................................................20
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`CONCLUSION ..................................................................................................................26
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`Vervaiin Ex. 2001, p. 2
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`DECLARATION OF SUNIL P. KHATRI, PH. D
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`I, Sunil P. Khatri, do hereby declare as follows:
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`INTRODUCTION
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`I have been retained on behalf of Vervain, LLC (“Vervain”), and its
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`counsel, McKool Smith, P.C., as an expert in this proceeding. I am personally
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`knowledgeable about the matters stated herein and am competent to make this
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`declaration.
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`I understand that Vervain will submit this Declaration in connection
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`with their Patent Owner’s Preliminary Response in Micron’s petition for inter partes
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`review, No. IPR2021-01549.
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`I receive compensation at an hourly rate of $700 per hour for my time
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`working on this matter, plus expenses. I have no financial interest in Vervain or in
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`the patents involved in this litigation, and my compensation is not dependent on the
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`outcome of this litigation. The conclusions I present are due to my own judgment.
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`BACKGROUND AND QUALIFICATIONS
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`I have over thirty-five years of experience with electronics, electrical
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`engineering, and computer engineering. A copy of my latest curriculum vitae (CV)
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`is attached hereto as Appendix A and provides further details regarding my
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`background and qualifications. During my career, I have acquired extensive
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`knowledge and experience with VLSI circuits, computer architecture, testing,
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`1
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`computer-aided design (CAD) algorithms and algorithm acceleration, logic
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`synthesis, semiconductor memory, redundancy, synchronous and asynchronous
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`circuits, and related software and hardware topics. Most relevant to the challenged
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`patents, my technical expertise includes extensive work with semiconductor memory
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`devices such as DRAM, SRAM and flash. My work with semiconductor memory
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`devices has included work on 3D integration and novel ring-based memory
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`architectures, power and speed tradeoffs using selective body bias, architectures and
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`circuit approaches for processing-in-memory, radiation hardening analysis for
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`memories, the use of flash transistors for designing logic circuits (such as ternary
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`Content-addressable Memories (CAMs), Field Programmable Gate Arrays
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`(FPGAs), and traditional binary-valued as well as ternary-valued digital logic), and
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`clocking and source-synchronous design. I recently was awarded a research grant by
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`the Air Force Research Laboratory (AFRL) in Rome, NY, to conduct research in
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`secure digital circuits using flash-based digital design approaches. Additionally, I
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`will be submitting a book chapter on the use of flash transistors in novel Very Large
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`Scale Integrated (VLSI) design applications. My MS thesis involved designing a
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`memory interface for a multi-threaded Reduced Instruction Set Computing (RISC)
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`microprocessor.
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`The following describes some of my relevant experience. I earned my
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`Bachelor of Science in Electrical Engineering in 1987 from the Indian Institute of
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`Technology, Kanpur, India. After graduating with my B.S. degree, I was a candidate
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`for a Master of Science degree in Electrical and Computer Engineering at the
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`University of Texas from 1987–89. At the University of Texas, I held the
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`Microelectronics and Computer Development (MCD) Fellowship from 1987–89. I
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`also conducted my M.S. research and wrote my thesis on the design of the METRIC
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`memory interface and memory system. METRIC was one of the first super-scalar
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`processors that was developed in the world. I earned an M.S. degree in 1989 from
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`the University of Texas, Austin.
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`
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`After leaving the University of Texas, I worked at Motorola Inc. from
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`1989–93 as a design engineer for the MC88110 reduced instruction set computing
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`(RISC) microprocessor team. My duties included the design of digital and analog
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`circuitry, test logic and circuits, JTAG boundary scan design, input/output driver
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`design, and clock phase-locked loop (PLL) logic. During my time at Motorola, I was
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`independently responsible for the design of the factory test controller of the
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`MC88110 microprocessor. I performed all attendant tasks in a “vertical” VLSI
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`design methodology, which included high-level modeling, circuit and layout design
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`and verification, as well as global and detailed routing. I also helped in the design of
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`the Translation Lookaside Buffer (TLB) unit, which included a static random-access
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`memory (SRAM) block.
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`Vervaiin Ex. 2001, p. 5
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`In 1999, I earned a Doctor of Philosophy degree in Electrical
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`Engineering and Computer Sciences from the University of California, Berkeley.
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`While at Berkeley, I held the California Microelectronics (MICRO) Fellowship in
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`1993.
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`I joined the faculty at the University of Colorado, Boulder, in 2000 as
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`an Assistant Professor of Electrical and Computer Engineering. At the University of
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`Colorado my research focused on VLSI logic design automation, VLSI layout design
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`automation, and VLSI design methodologies to address Deep Submicron (DSM)
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`issues such as crosstalk and power.
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`I joined the faculty at Texas A&M University in 2004 as an Assistant
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`Professor in Electrical and Computer Engineering. In 2010 I was promoted to
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`Associate Professor in Electrical and Computer Engineering. In 2015, I was
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`promoted to full Professor in Electrical and Computer Engineering. My research
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`focuses on three primary areas: the first is computer systems, including computer
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`architecture from the circuits up, and algorithm acceleration using GPUs, FPGAs
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`and custom ICs. The second is logic and its applications, while the third area consists
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`of interdisciplinary extensions of the first two. Some specific recent research topics
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`include circuit design using floating gate devices, wireless power delivery, battery-
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`less electronic systems, machine learning architectures, secure computing
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`approached from both a hardware and software perspective, and the mathematics of
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`scalable cryptocurrency. One of my new focus areas is intelligent and secure
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`computing viewed from the hardware (circuit) as well as the software levels. I am
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`conducting research on tamper-proof memory techniques, as well as multi-row read
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`architectures for SRAM, DRAM and flash memory arrays.
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` At Texas A&M I teach classes that cover memories extensively,
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`featuring thorough discussion of sense amplifiers, row and column decoders, and
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`different types of memory circuits. For example, in Electrical and Computer
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`Engineering (ECEN) 752 “Advances in VLSI Circuit Design,” a graduate level
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`course, I cover all aspects of VLSI design, including memory design. In ECEN
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`449/749 “Microprocessor System Design,” and in ECEN 752, I cover memories,
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`including flash memories, the design of flash memory cells, the organization of
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`memories into multiple banks, and the division of data across multiple banks of
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`memory, as well as other design techniques that can be used to optimize and manage
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`memories. This course is attended by both undergraduate (ECEN 449) and graduate
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`(ECEN 749) students. In ECEN 454 “Digital Circuit Design,” a senior
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`undergraduate course, I cover circuit design techniques for memory in detail. The
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`Ph.D. thesis of one of my recent doctoral students dealt with the use of flash
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`transistors to design logic circuits. The research of a recent M.S. student entailed a
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`new ring-based source synchronous architecture for 3D DRAM technologies, which
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`has been published at a conference and in a journal and is being submitted for
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`Vervaiin Ex. 2001, p. 7
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`dissemination as a research monograph. In the past, I have conducted research into
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`new topologies for efficient memory redundancy as part of a course project for my
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`graduate course.
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` Since 2000, I have earned 24 research contracts from funders including
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`Intel, the National Science Foundation, the National Security Agency, Altera
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`Corporation,
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`the National Center
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`for Atmospheric Research, National
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`Semiconductor Corporation, and several private sources. The total amount for these
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`research grants is $17.53 million, of which my portion is $2.85 million.
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`
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`I have a total of over 268 peer-reviewed publications. Among these
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`papers, five received a best paper award, while six others received best paper
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`nominations (including one journal best paper nomination). An additional three
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`journal papers and two conference paper are currently undergoing peer review. I
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`have co-authored nine research monographs, one edited research monograph, and
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`three book chapters. Additionally, I have six awarded U.S. Patents (one of which
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`was filed during my tenure at Texas A&M), two filed provisional U.S. Patents, and
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`another U.S. Patent which is currently under review and was also submitted during
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`my tenure at Texas A&M. I have co-authored one invited journal paper and 13
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`invited conference or workshop papers (including one from Design Automation
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`Conference (DAC) and one from Allerton). Moreover, I was invited to serve as a
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`panelist at a conference seven times and have presented two conference tutorials. I
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`Vervaiin Ex. 2001, p. 8
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`received the “Outstanding Professor Award” in the ECE Department at Texas A&M
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`University in 2007 and also in 2020. My H-index is 33 (per Google Scholar).
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` Since 2003, I have published numerous research monographs, journal
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`papers, and conference papers on flash transistors and memory systems, as detailed
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`in my attached CV. A few papers on relevant subject areas authored or co-authored
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`by me include:
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`•
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`Fast, Ring-based Design of 3D Stacked DRAM, IEEE Transactions
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`on Very Large Scale Integrated Circuits (TVLSI), IEEE Transactions
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`on Very Large Scale Integration (VLSI) Systems. Vol 27 number 8,
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`•
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`•
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`•
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`•
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`•
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`Aug 2019. pp 1731-1741.;
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`Fast, Ring-Based Design of 3D Stacked DRAM, IEEE International
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`Conference on Computer Design 2017: pp 665-672;
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`Selective Forward Body Bias for High Speed and Low Power SRAMs,
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`Journal of Low Power Electronics, Vol. 5, No. 2, Aug. 2009, pp. 185-
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`95;
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`Low Power and High Performance SRAM Design using Bank-based
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`Selective Forward Body Bias, IEEE/ACM Great Lakes Symposium on
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`VLSI, May 10-12, 2009, Boston, MA, pp. 441-44;
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`Modeling Dynamic Stability of SRAMs in the Presence of Single Event
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`Upsets (SEUs), IEEE International Symposium on Circuits and
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`Systems, May 18-21, 2008, Seattle, WA, pp. 1788-91;
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`“Design of a Flash-based Circuit for Multi-valued Logic”, Proceedings
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`of the Great Lakes Symposium on VLSI (GLSVLSI) 2017, pp 41-46,
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`May 10-12, 2017. Banff, Canada.
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`7
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`Vervaiin Ex. 2001, p. 9
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`•
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`"SAT-Based Optimization
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`for Flash-Based Digital Designs",
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`IEEE/ACM Design Automation Conferenec (DAC), Jun 18-22 2017,
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`Austin, TX.
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`•
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`"A Flash-based Digital Circuit Design Flow", IEEE/ACM International
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`Conference on Computer-Aided Design (ICCAD) 2016, Austin, TX,
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`Nov 2016.
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`•
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`"Implementing low power digital circuits using flash devices", 2016
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`IEEE 34th International Conference on Computer Design (ICCD), pp
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`109-116, Oct 3-5, 2016, Phoenix, AZ.
`
`•
`
`•
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`•
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`"Exploring Flash Devices to Implement Digital Circuits", IEEE/ACM
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`Design Automation Conference (DAC), June 2016, Austin, TX.
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`FTCAM: An Area-efficient Flash-based Ternary CAM Design, IEEE
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`Transactions on Computers, Vol. 65, No. 8, Aug. 2016, pp. 2652-58;
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`An Area-efficient Ternary CAM Design Using Floating Gate
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`Transistors, IEEE International Conference on Computer Design, Oct.
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`19-22, 2014, Seoul, S. Kor., pp. 55-60; and
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`•
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`A Fast Ternary CAM Design for IP Networking Applications,
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`International Conference on Computer Communications and Networks,
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`October 22, 2003, Dallas, TX, pp. 434-39 (awarded best paper).
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`In addition to my work on the papers listed above, I have also served as an
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`editor for IEEE Transactions on Computers, ACM Transactions on Design
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`Automation of Electronic Systems, and MDPI Journal of Electronics.
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`
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`I have served as EDA Track Co-Chair for ICECS 2014, Panel Chair for
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`TexasWISE 2014, Track Co-Chair (VLSI Systems, Applications and Computer
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`Vervaiin Ex. 2001, p. 10
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`Aided Design track) for ICECS 2013, Poster Session Chair for TexasWISE 2013,
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`Advisory Committee for HotPI 2013, Panel Session Chair for SLiP 2013, Track
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`Chair (Logic track) for ICCAD 2009-10, 2015-17, Track Chair (logic track) for DAC
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`2016-17, General Chair for IWLS 2009, Technical Program Chair for IWLS 2008,
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`Track Co-Chair, Computer Aided Network DEsign (CANDE) Track, for ISCAS
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`2008-10, Track Co-chair for the DSP track for ISCAS 2022, Track Co-Chair, Test
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`and Methodologies Track, for ICCD 2007, Panel Chair for ITSW 2009, Publicity
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`Co-Chair for GLS-VLSI 2009, and as a member of the TPC for several conferences.
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`
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`I am generally familiar with the analysis of patents. I am a named
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`inventor on the following U.S. Patents:
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`•
`
`•
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`•
`
`•
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`•
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`Data Processing System Having Serial Self Address Decoding and
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`Method of Operation, United States Patent No. 5,347,523, issued
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`September 13, 1994;
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`Circuit Identifier for Use with Focused Ion Beam Equipment, United
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`States Patent No. 5,408,131, issued April 18, 1995 (“the ’131 patent”);
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`Driver Circuit with Self-Adjusting Impedance Matching, United States
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`Patent No. 5,448,182, issued September 5, 1995 (“the ’182 patent”);
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`Circuit Identifier for Use with Focused Ion Beam Equipment, United
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`States Patent No. 6,156,579, issued December 5, 2000 (“the ’579
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`patent);
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`Datapath Design Methodology and Routing Apparatus, United States
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`Patent No. 6,598,215, issued July 22, 2003;
`
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`Vervaiin Ex. 2001, p. 11
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`•
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`Low Power Reconfigurable Circuits with Delay Compensation, United
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`States Patent No. 7,880,505, issued February 1, 2011.
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`
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` The ’131 and ’579 patents are directed to an identification means for
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`redundant circuits that distinguishes said circuits by respective function. This allows
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`for identification by focused ion beam equipment, which can then repair, replace, or
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`supplement circuits as necessary. These patents disclose a scheme for replacing
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`defective cells or circuits within a larger circuit.
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` The ’182 patent relates to a driver circuit capable of switching from one
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`driving impedance to a second in response to the output signal of a first driver portion
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`reaching a predetermined voltage. It discloses a driver circuit capable of adjusting
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`circuit configurations depending upon the current output state.
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` SCOPE OF ASSIGNMENT AND MATERIALS CONSIDERED
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`I have been retained by Vervain (“Patent Owner”) to provide an
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`explanation to the Board regarding the inventions described in the Patents-In-Suit. I
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`understand Petitioner Micron Technology, Inc. (“Micron” or “Petitioner”), has filed
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`petitions for inter partes review, Nos. IPR2021-01547, -01548, -01549, and -01550,
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`against each of the patents-in-suit. I have been retained to provide my opinions
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`regarding various technical issues relating to the validity of the patents-in-suit over
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`the prior art references identified by Micron’s petitions.
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`Vervaiin Ex. 2001, p. 12
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`In preparing this Declaration, I am relying on my own knowledge and
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`expertise as well as the following documents:
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`• The Patents-In-Suit:
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`U.S. Patent No. 8,891,298 to G.R. Mohan Rao (“298
`patent”)
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`U.S. Patent No. 9,196,385 to G.R. Mohan Rao (“385
`patent”)
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`U.S. Patent No. 9,997,240 to G.R. Mohan Rao (“240
`patent”)
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`U.S. Patent No. 10,950,300 to G.R. Mohan Rao (“300
`patent”);
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`• Prosecution histories for the Patents-In-Suit, which I understand
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`constitute the exchange of correspondence between the Patent Office
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`and the applicant;
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`• Micron’s petitions for inter partes review, Nos. IPR2021-01547, -
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`01548, -01549, and -01550, as well as the declarations of Dr. David Liu
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`submitted in support thereof;
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`• The alleged prior art references cited in Micron’s petitions, including
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`U.S. Patent Application Publication Nos. 2011/0099460 (“Dusija”),
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`2008/0140918 (“Sutardja”), and 2010/0017650 (“Chin”); and
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`• The other references cited within this Declaration.
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`Vervaiin Ex. 2001, p. 13
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`PERSON OF ORDINARY SKILL IN THE ART
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` When interpreting a patent, I understand that it is important to view the
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`disclosure and claims of that patent from the level of ordinary skill in the relevant
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`art at the time of the invention. My opinion of the level of ordinary skill in the art
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`with regard to the Patents-in-Suit is based on my personal experience working and
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`teaching in the fields of electrical engineering and computer science, including work
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`with DRAM technologies, my knowledge of the background and education of
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`colleagues and others working in that general field as of and for several years prior
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`to the 1999 to 2001 time frame, my study of the Patents-in-Suit, and its file history,
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`and my knowledge of:
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`• The level of education and experience of persons actively working in the
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`field at the time the subject matter at issue was developed;
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`• The types of problems encountered in the art at the time the subject matter
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`was developed;
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`• The prior art patents and publications;
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`• The activities of others working in that same technical field;
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`• Prior art solutions to the problems addressed by the relevant art; and
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`• The sophistication of the technology at issue in this case.
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`
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`In determining the level of ordinary skill in the art, I also considered
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`the following factors: (1) the sophistication of the relevant technology; (2) the
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`Vervaiin Ex. 2001, p. 14
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`rapidity with which innovations are made in that field; and (3) the educational level
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`of active workers in that field. It is my further understanding that these factors are
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`not exhaustive and are merely a useful guide to determining the level of ordinary
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`skill in the art.
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` Taking the above factors into account, in my opinion a POSITA in the
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`technology field of the Patents-in-Suit would be a person with at least a Bachelor of
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`Science degree in electrical engineering, computer engineering, or a closely related
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`field, with at least 3-5 years of experience in the design of non-volatile memory
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`devices. An individual with an advanced degree in a relevant field would require
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`less experience in the design of non-volatile memory devices.
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`
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`I understand that Micron’s expert, Dr. David Liu, agrees with this
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`definition. Ex. 1009, ¶ 7. This accords with my experience. Many of the individuals
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`hired by semiconductor manufacturing companies at the time of the invention did
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`not have graduate degrees, and thus the level of ordinary skill in the art should
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`specifically include such individuals.
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` GENERAL BACKGROUND OF THE RELEVANT TECHNOLOGY
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` Volatile memory, such as static random access memory (“SRAM”) and
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`dynamic random access memory (“DRAM”), lose memory when power is turned
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`off. However, more persistent memory is needed for many applications, such as
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`photos in a digital camera, bootable code or settings in circuits, or a wide range of
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`Vervaiin Ex. 2001, p. 15
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`data storage needs. Non-volatile memories (e.g., thumb drives, hard drives, and
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`compact discs) can store information after the system is powered off. Traditionally,
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`media such as hard disks, floppy disks, compact discs, or magnetic tapes was used
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`for persistent storage in computing systems, but these media are large, bulky, and
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`slow, and use a large amount of power. Flash memory is a specific type of non-
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`volatile memory, where data is stored in “blocks” of “pages.” Flash memory chips
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`have come to be used for persistent data storage in a wide range of applications.
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`Data stored in flash memory persists across power on/off cycles and has a small size,
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`high performance, and low power consumption.
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` Flash memory uses a special type of transistor that has both a “floating
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`gate” and a “control gate.” In a floating gate transistor, charge is stored on an
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`isolated conductor, called the floating gate. This charge has no path to dissipate.
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`The charge on the floating gate controls the current flowing between the source and
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`drain. This current allows the user to determine the value stored in the cell.
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` To erase the cell, a reverse voltage is applied between the drain and the
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`control gate. Charge is then dissipated through tunneling.
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`Vervaiin Ex. 2001, p. 16
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` Floating gate transistors individually are limited in endurance.
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`Depending on the type of transistor and how it is configured, an individual transistor
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`may not work reliably after it has been programmed and erased too many times. For
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`example, endurance for some flash transistors is on the order of 10,000 to 100,000
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`program-erase cycles.
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` Because of the limited endurance of floating gate transistors, and
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`because some locations in a memory may be very frequently rewritten, it is not
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`always feasible to use the same transistor each time for each memory location.
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`Rather, flash memory typically includes a controller that uses a flash translation
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`layer to map logical addresses presented to the host to physical addresses used to
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`address the physical flash memory. This flash translation layer allows for wear to
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`be leveled across all the transistors on a device, and for bad blocks to be managed
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`and avoided.
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`A.
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`SLC and MLC Flash
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`Early flash memory stored only a “0” or a “1” in each transistor. This
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`is today known as “SLC,” or “single level cell,” flash. Later on, to increase the
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`density of storage in flash memory, a technique known as “MLC”, or “multiple level
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`cell,” was introduced, where multiple threshold voltage levels in each transistor
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`would represent multiple bits of data. For example, the following diagram shows
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`how in SLC flash, large voltage ranges are assigned to the “1” and “0” bits
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`respectively, whereas in MLC flash, smaller voltage ranges are assigned to multiple-
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`bit values such as “11,” “10,” “01,” and “00.”
`
`Chen et al., Ultra MLC Technology Introduction, Advantech Technical White Paper
`
`(Oct. 5, 2012), 3.
`
` The primary difference between SLC and MLC is what data each
`
`voltage represents. With SLC flash, the transistor stores only a 1 or 0, so a wide
`
`range of voltages can be allotted to a single bit. This allows for faster and more
`
`reliable memory access. On the other hand, MLC flash must be slowly and carefully
`
`programmed using a narrow, precise range of voltages, with each voltage range
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`representing a specific sequence of bits (see the figure above, which shows four
`
`sequences of bits—11, 10, 01, and 00—corresponding to different ranges of
`
`threshold voltages).
`
` Flash memories sometimes use dual-mode flash, where the cells can be
`
`configured as SLC or MLC. When the cell is in SLC-mode, it does not use multiple
`
`levels per cell, but instead uses a single dividing line between ‘1’ and ‘0’.
`
`B.
`
`Address Table
`
`To provide wear leveling, garbage collection, and bad block
`
`management, a translation layer is used to map logical addresses to actual physical
`
`locations. As part of this translation layer, tables are widely used in order to map
`
`sectors and pages from logical to physical. These tables map logical blocks to
`
`physical blocks. Using a “block” or similar granularity is important, since flash
`
`memory is arranged so that when erasing and rewriting data, all the memory in a
`
`block is erased together. Therefore, Dr. Rao explained that “[t]he address ranges
`
`within the translation table will assume some minimum quantum, such as, for
`
`example, one block, although a smaller size, such as one page could be used, if the
`
`NAND flash has the capability of erasing the smaller size quantum.” 240 patent,
`
`5:46-50. Dr. Rao further explained that memory is written and mapped on the
`
`granularity of a “quantum,” such as a block or page. 240 Patent, Figs. 3A-B.
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`C.
`
`Data Integrity Tests
`
`When data is stored in MLC memory, it is more prone to errors, and
`
`some data is more prone to errors than other data. Errors can occur when writing or
`
`reading the data. Errors can also be caused by the data stored in neighboring cells.
`
`A data integrity test is a test that checks the integrity of the data (i.e., whether errors
`
`have occurred). This test can be run immediately after data is written, or at a later
`
`time. If the test reveals a problem such as corrupt data, the data can be remapped to
`
`higher-performance SLC or less-used MLC, and the address table is modified
`
`accordingly. 240 Patent, 4:24-30.
`
`D.
`
`Hot and Cold Data
`
`One of the key features of Dr. Rao’s invention is how it distinguishes
`
`between “hot” blocks (which receive more frequent writes), and “cold” blocks
`
`(which receive less frequent writes). 240 Patent, 6:46-52. Because SLC flash has
`
`the endurance to handle frequent writes, “hot” blocks can be allocated to SLC flash
`
`to increase the lifetime of the system. “Cold” blocks, on the other hand, can be
`
`allocated to MLC flash to take advantage of its higher density storage.
`
`THE PATENTS-IN-SUIT
`
` The Patents-in-Suit relate to systems for storing data using SLC and
`
`MLC flash memory.
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` U.S. Patent No. 8,891,298 (the “’298 patent”), entitled “Lifetime Mixed
`
`Level Non-Volatile Memory System,” issued on November 18, 2014. I understand
`
`the Asserted Claims from the 298 patent include claims 1, 3-5, and 11.
`
` U.S. Patent No. 9,196,385 (the “’385 patent”), entitled “Lifetime Mixed
`
`Level Non-Volatile Memory System,” issued on November 24, 2015. I understand
`
`the Asserted Claims from the 385 patent include claims 1, 3-5, and 11-13.
`
` U.S. Patent No. 9,997,240 (the “’240 patent”), entitled “Lifetime Mixed
`
`Level Non-Volatile Memory System,” issued on June 12, 2018. I understand the
`
`Asserted Claims from the 240 patent include claims 1-2 and 6-7.
`
` U.S. Patent No. 10,950,300 (the “’300 patent”), entitled “Lifetime
`
`Mixed Level Non-Volatile Memory System,” issued on March 16, 2021. I
`
`understand the Asserted Claims from the 300 patent include claims 1-12.
`
`G.R. Mohan Rao is the sole named inventor of the four Patents-in-Suit.
`
`
`
`In the Asserted Claims, data is stored in non-volatile memory using
`
`single level cell (SLC) memory that stores 1 bit per cell, and multiple level cell
`
`(MLC) memory that stores more than 1 bit per cell. There are pros and cons to SLC
`
`and MLC flash. SLC is faster and less prone to errors, but requires more space and
`
`power to store a given amount of data. The opposite is true of MLC. MLC flash is
`
`slower and more prone to errors, but stores data more densely with less power
`
`consumption.
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` The Asserted Claims are directed to specific techniques for efficiently
`
`using SLC and MLC flash to improve the overall performance of the memory. For
`
`example, if certain data is more prone to errors, or is used more frequently, then it is
`
`transferred to higher-performance SLC or less-used MLC. By doing so, the number
`
`of errors is reduced, and the overall endurance of the memory is increased.
`
`TECHNICAL OPINIONS
`
` When data is stored in MLC memory, it is more prone to errors, and
`
`some data is more prone to errors than other data. One reason for this is that the
`
`threshold voltage intervals for MLC memory are smaller than the threshold voltage
`
`intervals for SLC memory, and thus, more errors can occur when writing or reading
`
`the MLC data. Errors can also be caused by the data stored in neighboring cells. A
`
`data integrity test is a test that checks the integrity of the data (i.e., whether errors
`
`have occurred). This test can be run immediately after data is written, or at a later
`
`time.
`
` Flash memory systems typically have two forms of addressing: a
`
`“logical address,” which is an address from the perspective of an executing
`
`application program and a “physical address,” indicating the specific location in a
`
`flash memory chip where the data is stored.
`
` During operation of the flash memory, logical addresses are frequently
`
`remapped to new physical locations. Over time, a particular logical address may be
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`mapped or associated with many different physical locations (blocks). And multiple
`
`logical addresses may point to the same block over time, so there is not a one-to-one
`
`correspondence between the logical addresses and the blocks over time.
`
` A system that determines how frequently data is written to each of the
`
`logical addresses will not necessarily determine which of the physical blocks are
`
`accessed most frequently.
`
` A logical address may be remapped to a new physical address due to,
`
`for example, wear leveling, garbage collection, or bad block management. When
`
`this occurs, the frequency of writes to the logical address may be different from the
`
`frequency of writes to the physical block that it is currently mapped to. If, for
`
`example, “LogicalAddressA” is remapped from Block1 to Block2, there may be 100
`
`writes to LogicalAddressA, but only 70 writes to Block1 and 30 writes to Block2.
`
` Additionally, over time, multiple logical addresses may point to the
`
`same block. When this occurs, the frequency of writes to the logical addresses may
`
`be different from the frequency of writes to the blocks. If, for example,
`
`“LogicalAddressA” is mapped to Block1; and “LogicalAddressB” is first mapped to
`
`Block2, and then “LogicalAddressC” is subsequently mapped to Block2, the
`
`frequency of the writes to the Logical Addresses may provide a distorted view of the
`
`frequency of the writes to the blocks. For example, Block2 may have 150 writes and
`
`Block1 may have 100 writes, while LogicalAddressA may have 100 writes, and each
`
`
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`of LogicalAddressB and LogicalAddressC have 75 writes. In this example,
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`LogicalAddressA may have the most writes, but Block2 will have more writes than
`
`Block1.
`
`
`
`In Sutardja
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