(19) United States
`(12) Patent Application Publication (10) Pub. No.: US 2012/0311244 A1
`Huang et al.
`(43) Pub. Date:
`Dec. 6, 2012
`
`US 20120311244A1
`
`(54)
`
`BALANCED PERFORMANCE FOR ON-CHIP
`FOLDING OF NON-VOLATILE MEMORIES
`
`(76)
`
`Inventors:
`
`Yichao Huang, San Jose, CA (US);
`Jianmin Huang, Sunnyvale, CA
`(US); Gautam Ashok Dusija,
`Milpitas, CA (US); Oleg Kragel,
`Minsk (BY)
`
`(21)
`
`Appl. No.:
`
`13/491,879
`
`(22)
`
`Filed:
`
`Jun. 8, 2012
`
`(63)
`
`Related U.S. Application Data
`Continuation-in-part of application No. 12/642,611,
`filed on Dec. 18, 2009, Continuation-in-part of appli
`cation No. 12/642,649, filed on Dec. 18, 2009, now
`Pat. No. 8,144,512.
`
`(60)
`
`Provisional application No. 61/495,053, filed on Jun.
`9, 2011.
`
`Publication Classification
`
`(51) Int. Cl.
`(2006.01)
`G06F 12/00
`(52) U.S. Cl. ................................. 711/103; 711/E12.008
`(57)
`ABSTRACT
`A non-volatile memory system receives and stores host data.
`As the memory system receives host data, it initially writes
`the data in a binary format and then Subsequently performs an
`on-chip folding operation on the data, storing the data in a
`multi-state format. The memory system interleaves the
`phases of the folding operations so that performance is made
`more uniform across allocation units, where the host stores
`data according to allocation units. The memory system also
`can perform the binary and Subsequent on-chip folding opera
`tions on multiple memory planes in parallel, where the con
`troller also balances the operations so that performance is
`made more uniform between planes with respect to allocation
`units as the data is received from the host. To further maintain
`performance, the memory system uses a free block list having
`a reserve portion that is only accessible for a specified set of
`commands.
`
`HOST 80
`
`MEMORY SYSTEM 90
`
`Controller 100
`
`Interface 1 1 O
`
`Processor 120
`Optional CoProcessor
`121
`
`
`
`ROM 122
`Optional
`Programmable
`Non-Volatile Memory
`124
`
`RAM 130
`
`
`
`
`
`
`
`
`
`Flash Memory
`200
`
`
`
`Micron Ex. 1044, p.1
`Micron v. Vervain
`IPR2021-01547
`
`

`

`Patent Application Publication
`
`Dec. 6, 2012 Sheet 1 of 34
`
`US 2012/0311244 A1
`
`HOST 80
`
`MEMORY SYSTEM 90
`
`Controller 100
`
`interface 110
`
`Processor 120
`Optional CoProcessor
`121
`
`
`
`
`
`
`
`ROM 122
`Optional
`Programmable
`Non-Volatile Memory
`124
`
`RAM 130
`
`
`
`FIG. 1
`
`Flash Memory
`200
`
`Micron Ex. 1044, p.2
`Micron v. Vervain
`IPR2021-01547
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`

`

`Patent Application Publication
`
`Dec. 6, 2012 Sheet 2 of 34
`
`US 2012/0311244 A1
`
`Control
`Gate
`
`y 1 O
`
`REF
`
`
`
`O5 1.O 15 2.O
`2.5
`FIG. 3
`
`3.O
`
`3.5
`
`WCG(V)
`
`Micron Ex. 1044, p.3
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`

`Patent Application Publication
`
`Dec. 6, 2012 Sheet 3 of 34
`
`US 2012/0311244 A1
`
`Drain
`
`56
`
`NAND STRING
`50
`
`Drain
`Select
`
`32
`
`S2
`
`Control Gate n
`
`2O
`
`3O
`
`1O
`
`Min
`
`:
`
`Control Gate 2
`
`10
`
`M2
`
`Control Gate 1
`
`3O
`
`3O
`
`1O
`
`M1
`
`Source Select
`
`O
`
`S1
`
`32
`
`FIG. 4A
`
`54
`Source
`
`Micron Ex. 1044, p.4
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`

`Patent Application Publication
`
`Dec. 6, 2012 Sheet 4 of 34
`
`US 2012/0311244 A1
`
`
`
`Bit Lines
`FIG. 4B
`
`Micron Ex. 1044, p.5
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`

`Patent Application Publication
`
`Dec. 6, 2012 Sheet 5 of 34
`
`US 2012/0311244 A1
`
`
`
`LLITIE
`L-ULIT?
`
`ZTE
`
`Micron Ex. 1044, p.6
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`

`

`Patent Application Publication
`
`Dec. 6, 2012 Sheet 6 of 34
`
`US 2012/0311244 A1
`
`
`
`(?)
`
`-e-m-m-m-Threshold Window -o-o->
`Erased
`
`rV.
`
`rV2
`
`rV3
`
`wV
`
`VV2 2-
`
`wV3
`
`(\
`/N
`
`Upper Bit
`
`lower Bit
`
`Programming into Four States Represented by a 2-bit Code
`FIG. 6
`
`Micron Ex. 1044, p.7
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`

`Patent Application Publication
`
`Dec. 6, 2012 Sheet 7 of 34
`
`US 2012/0311244 A1
`
`Upper Bit-
`"O1 y
`
`LOWer Bit
`* O”
`
`it 1 1 y
`
`“OO"
`
`Threshold Voltage
`
`Multistate Memory
`FIG. 7A
`
`- N.
`
`"XO"
`
`1 1
`
`
`
`
`
`s
`
`Lower Page Programming (2-bit Code)
`FIG 7B
`
`- N.
`2S,
`
`"intermediate'
`
`Upper Page Programming (2-bit Code)
`FIG. 7C
`
`Micron Ex. 1044, p.8
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`IPR2021-01547
`
`

`

`Patent Application Publication
`
`Dec. 6, 2012 Sheet 8 of 34
`
`US 2012/0311244 A1
`
`lower Bit or "O"
`Lower PageRead (2-bit Code)
`
`
`
`Upper Bit = "O"
`
`Upper Bit = "O"
`
`Upper Page Read (2-bit Code)
`FIG. 7E
`
`Micron Ex. 1044, p.9
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`

`Patent Application Publication
`
`Dec. 6, 2012 Sheet 9 of 34
`
`US 2012/0311244 A1
`
`
`
`
`
`
`
`
`
`
`
`
`
`AF
`
`BF gF
`
`DF
`
`EF
`
`FF
`
`First
`Program
`(1st Stage)
`
`Foggy
`Program
`GF (2nd Stage)
`
`FIG. 7F
`
`Micron Ex. 1044, p.10
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`

`Patent Application Publication
`
`Dec. 6, 2012 Sheet 10 of 34
`
`US 2012/0311244 A1
`
`HOST 80
`
`Application
`
`OSI
`File System
`
`Clusters (Logical Sectors)
`
`Host-Side Memory Manager (Optional)
`
`Logical Sectors
`
`MEMORY SYSTEM 90
`Memory Manager 300
`
`Front-End System 310
`
`Host interface
`
`3f2
`
`
`
`Back-End System
`320
`
`Flash Memory
`200
`
`FIG.
`
`Micron Ex. 1044, p.11
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`IPR2021-01547
`
`

`

`Patent Application Publication
`
`Dec. 6, 2012 Sheet 11 of 34
`
`US 2012/0311244 A1
`
`Host interface
`
`
`
`BACK-END SYSTEM 320
`Dataflow &
`Sequencing layer
`340
`Command
`Sequencer
`342
`
`
`
`
`
`
`
`Media Management
`Layer
`330
`
`
`
`
`
`
`
`
`
`
`
`LOW-Level
`Sequencer
`344
`
`Flash Contro
`Layer
`346
`
`FIG. 9
`
`Micron Ex. 1044, p.12
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`IPR2021-01547
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`

`Patent Application Publication
`
`Dec. 6, 2012 Sheet 12 of 34
`
`US 2012/0311244 A1
`
`Logical Group
`
`() LG,
`
`0 | 1. KK 1
`
`...
`
`N-1
`
`"" |
`
`|
`
`|
`
`|
`
`|
`
`TF
`
`Physical Group
`(Metablock)
`
`
`
`Page Tag
`N--
`FIG. 10A
`
`
`
`Logical Group
`
`Physical Group
`(Metablock)
`
`Logical to
`Physical
`Directories
`
`FIG 10B
`
`Micron Ex. 1044, p.13
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`IPR2021-01547
`
`

`

`Patent Application Publication
`
`Dec. 6, 2012 Sheet 13 of 34
`
`US 2012/0311244 A1
`
`FLASH MEMORY DEVICE
`
`Controller
`
`Main Memory
`
`Binary Cache
`
`Host Cache |N
`(RAM)
`
`FIG 11
`
`
`
`Binary Block
`SECC
`
`-Hwup-
`Data from
`Controller Host
`
`
`
`
`
`N=3 Block
`
`F.G. 12
`
`611
`613
`615
`
`617
`
`623
`
`621
`
`Micron Ex. 1044, p.14
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`IPR2021-01547
`
`

`

`Patent Application Publication
`
`Dec. 6, 2012 Sheet 14 of 34
`
`US 2012/0311244 A1
`
`
`
`Micron Ex. 1044, p.15
`Micron v. Vervain
`IPR2021-01547
`
`

`

`Patent Application Publication
`
`Dec. 6, 2012 Sheet 15 of 34
`
`US 2012/0311244 A1
`
`
`
`??epdn pe??uenb?S
`
`
`
`
`
`
`
`
`
`6upped
`
`999| 89|
`
`ETIA
`
`ÁJeug
`
`?uoz
`
`Micron Ex. 1044, p.16
`Micron v. Vervain
`IPR2021-01547
`
`

`

`Patent Application Publication
`
`Dec. 6, 2012 Sheet 16 of 34
`
`US 2012/0311244 A1
`
`
`
`Micron Ex. 1044, p.17
`Micron v. Vervain
`IPR2021-01547
`
`

`

`Patent Application Publication
`
`Dec. 6, 2012 Sheet 17 of 34
`
`US 2012/0311244 A1
`
`
`
`
`
`Micron Ex. 1044, p.18
`Micron v. Vervain
`IPR2021-01547
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`

`

`Patent Application Publication
`
`Dec. 6, 2012 Sheet 18 of 34
`
`US 2012/0311244 A1
`
`
`
`(non)
`
`uo?ep?osuoO ? Kdo O
`50 | - - - - - - - - -—HL|| -9n :
`
`
`
`
`
`| ||
`
`£CI
`
`----
`
`Micron Ex. 1044, p.19
`Micron v. Vervain
`IPR2021-01547
`
`

`

`Patent Application Publication
`
`Dec. 6, 2012 Sheet 19 of 34
`
`US 2012/0311244 A1
`
`
`
`
`
`Z
`
`Micron Ex. 1044, p.20
`Micron v. Vervain
`IPR2021-01547
`
`

`

`Patent Application Publication
`
`Dec. 6, 2012 Sheet 20 of 34
`
`US 2012/0311244 A1
`
`
`
`----- ~~~. :) ---- ---- --- • • • •— —— ——• • ? = = = =,
`
`
`
`
`
`– 6uipped
`
`For -
`
`
`
`
`
`
`
`
`
`
`Micron Ex. 1044, p.21
`Micron v. Vervain
`IPR2021-01547
`
`

`

`Patent Application Publication
`
`Dec. 6, 2012 Sheet 21 of 34
`
`US 2012/0311244 A1
`
`
`
`FIG. 20
`
`Micron Ex. 1044, p.22
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`IPR2021-01547
`
`

`

`Patent Application Publication
`
`Dec. 6, 2012 Sheet 22 of 34
`
`US 2012/0311244 A1
`
`
`
`
`
`Micron Ex. 1044, p.23
`Micron v. Vervain
`IPR2021-01547
`
`

`

`Patent Application Publication
`
`Dec. 6, 2012 Sheet 23 of 34
`
`US 2012/0311244 A1
`
`
`
`W/ZZ "SDI-J
`
`
`
`
`
`
`
`
`
`
`
`Micron Ex. 1044, p.24
`Micron v. Vervain
`IPR2021-01547
`
`

`

`Patent Application Publication
`
`Dec. 6, 2012 Sheet 24 of 34
`
`US 2012/0311244 A1
`
`
`
`
`
`Micron Ex. 1044, p.25
`Micron v. Vervain
`IPR2021-01547
`
`

`

`Patent Application Publication
`
`Dec. 6, 2012 Sheet 25 of 34
`
`US 2012/0311244 A1
`
`
`
`
`
`
`
`Micron Ex. 1044, p.26
`Micron v. Vervain
`IPR2021-01547
`
`

`

`Patent Application Publication
`
`Dec. 6, 2012 Sheet 26 of 34
`
`US 2012/0311244 A1
`
`
`
`
`
`Micron Ex. 1044, p.27
`Micron v. Vervain
`IPR2021-01547
`
`

`

`Patent Application Publication
`
`Dec. 6, 2012 Sheet 27 of 34
`
`US 2012/0311244 A1
`
`
`
`
`
`Micron Ex. 1044, p.28
`Micron v. Vervain
`IPR2021-01547
`
`

`

`Patent Application Publication
`
`Dec. 6, 2012 Sheet 28 of 34
`
`US 2012/0311244 A1
`
`
`
`Micron Ex. 1044, p.29
`Micron v. Vervain
`IPR2021-01547
`
`

`

`Patent Application Publication
`
`Dec. 6, 2012 Sheet 29 of 34
`
`US 2012/0311244 A1
`
`
`
`Micron Ex. 1044, p.30
`Micron v. Vervain
`IPR2021-01547
`
`

`

`Patent Application Publication
`
`Dec. 6, 2012 Sheet 30 of 34
`
`US 2012/0311244 A1
`
`
`
`Background
`Mode
`
`Balanced Mode
`(e.g., seq.)
`
`I 801
`
`\813
`
`Urgent Mode
`(e.g., non-seq.)
`
`8O3
`
`FIG. 28
`
`Micron Ex. 1044, p.31
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`IPR2021-01547
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`

`

`Patent Application Publication
`
`Dec. 6, 2012 Sheet 31 of 34
`
`US 2012/0311244 A1
`
`
`
`
`
`||||||||||||||||||||||||||||||||
`
`GWO []
`
`Micron Ex. 1044, p.32
`Micron v. Vervain
`IPR2021-01547
`
`

`

`Patent Application Publication
`
`Dec. 6, 2012 Sheet 32 of 34
`
`US 2012/0311244 A1
`
`E.
`I
`---------H
`II I
`
`3
`
`FIG. 30A
`
`6 II
`is H H---------
`3 I I
`
`2
`
`we win C
`
`C
`
`or of r "e" is
`
`to co -, - c. c. C. c. o x x - c.
`
`f
`
`FIG. 30B '"
`
`Micron Ex. 1044, p.33
`Micron v. Vervain
`IPR2021-01547
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`

`Patent Application Publication
`
`Dec. 6, 2012 Sheet 33 of 34
`
`US 2012/0311244 A1
`
`
`
`
`
`Micron Ex. 1044, p.34
`Micron v. Vervain
`IPR2021-01547
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`

`

`Patent Application Publication
`
`Dec. 6, 2012 Sheet 34 of 34
`
`US 2012/0311244 A1
`
`FBL.
`
`FB1 FB2 FB3 FB4 FBS FB6 FB7
`
`FB8 FB9 FB10
`
`Standard
`
`f
`
`--
`Reserve
`
`FIG. 32
`
`Background
`Mode
`
`1 OO1
`
`
`
`1
`Specified
`Set
`N ?
`
`
`
`
`
`
`
`Select BOCKS
`from Only
`Standard FBL
`
`
`
`Select Blocks
`from A
`of the FBL
`
`FIG. 33
`
`Micron Ex. 1044, p.35
`Micron v. Vervain
`IPR2021-01547
`
`

`

`US 2012/0311244 A1
`
`Dec. 6, 2012
`
`BALANCED PERFORMANCE FOR ON-CHIP
`FOLDING OF NON-VOLATILE MEMORIES
`
`CROSS-REFERENCE TO RELATED PATENT
`APPLICATIONS
`0001. This application claims priority from U.S. Provi
`sional Application No. 61/495,053, filed Jun. 9, 2011, and
`both it and the present application are continuations in part of
`U.S. patent application Ser. No. 12/642,611, published as
`US-2011-0153913-A1, and U.S. patent application Ser. No.
`12/642,649, now U.S. Pat. No. 8,144,512.
`
`BACKGROUND
`0002 This application relates to the operation of re-pro
`grammable non-volatile memory systems such as semicon
`ductor flash memory, and, more specifically, to the manage
`ment of the interface between a host device and the memory.
`0003 Solid-state memory capable of nonvolatile storage
`of charge, particularly in the form of EEPROM and flash
`EEPROM packaged as a small form factor card, has recently
`become the storage of choice in a variety of mobile and
`handheld devices, notably information appliances and con
`Sumer electronics products. Unlike RAM (random access
`memory) that is also solid-state memory, flash memory is
`lion-volatile, and retaining its stored data even after power is
`turned off. Also, unlike ROM (read only memory), flash
`memory is rewritable similar to a disk storage device. In spite
`of the higher cost, flash memory is increasingly being used in
`mass storage applications. Conventional mass storage, based
`on rotating magnetic medium Such as hard drives and floppy
`disks, is unsuitable for the mobile and handheld environment.
`This is because disk drives tend to be bulky, are prone to
`mechanical failure and have high latency and high power
`requirements. These undesirable attributes make disk-based
`storage impractical in most mobile and portable applications.
`On the other hand, flash memory, both embedded and in the
`form of a removable card is ideally suited in the mobile and
`handheld environment because of its small size, low power
`consumption, high speed and high reliability features.
`0004 Flash EEPROM is similar to EEPROM (electrically
`erasable and programmable read-only memory) in that it is a
`non-volatile memory that can be erased and have new data
`written or “programmed' into their memory cells. Both uti
`lize a floating (unconnected) conductive gate, in a field effect
`transistor structure, positioned over a channel region in a
`semiconductor Substrate, between source and drain regions.
`A control gate is then provided over the floating gate. The
`threshold voltage characteristic of the transistor is controlled
`by the amount of charge that is retained on the floating gate.
`That is, for a given level of charge on the floating gate, there
`is a corresponding Voltage (threshold) that must be applied to
`the control gate before the transistor is turned “on” to permit
`conduction between its source and drain regions. In particu
`lar, flash memory such as Flash EEPROM, allows entire
`blocks of memory cells to be erased at the same time.
`0005. The floating gate can hold a range of charges and
`therefore can be programmed to any threshold Voltage level
`within a threshold voltage window. The size of the threshold
`Voltage window is delimited by the minimum and maximum
`threshold levels of the device, which in turn correspond to the
`range of the charges that can be programmed onto the floating
`gate. The threshold window generally depends on the
`memory device's characteristics, operating conditions and
`
`history. Each distinct, resolvable threshold voltage level
`range within the window may, in principle, be used to desig
`nate a definite memory state of the cell.
`0006. The transistor serving as a memory cell is typically
`programmed to a “programmed' state by one of two mecha
`nisms. In "hot electron injection, a high Voltage applied to
`the drain accelerates electrons across the Substrate channel
`region. At the same time a high Voltage applied to the control
`gate pulls the hot electrons through a thin gate dielectric onto
`the floating gate. In “tunneling injection, a high Voltage is
`applied to the controlgate relative to the Substrate. In this way,
`electrons are pulled from the substrate to the intervening
`floating gate. While the term “program' has been used his
`torically to describe writing to a memory by injecting elec
`trons to an initially erased charge storage unit of the memory
`cell so as to alter the memory state, it has now been used
`interchangeable with more common terms such as “write' or
`“record.
`0007. The memory device may be erased by a number of
`mechanisms. For EEPROM, a memory cell is electrically
`erasable, by applying a high Voltage to the Substrate relative to
`the controlgate so as to induce electrons in the floating gate to
`tunnel through a thin oxide to the Substrate channel region
`(i.e., Fowler-Nordheim tunneling.) Typically, the EEPROM
`is erasable byte by byte. For flash EEPROM, the memory is
`electrically erasable either all at once or one or more mini
`mum erasable blocks at a time, where a minimum erasable
`block may consist of one or more sectors and each sector may
`store 512 bytes or more of data.
`0008. The memory device typically comprises one or
`more memory chips that may be mounted on a card. Each
`memory chip comprises an array of memory cells Supported
`by peripheral circuits such as decoders and erase, write and
`read circuits. The more Sophisticated memory devices also
`come with a controller that performs intelligent and higher
`level memory operations and interfacing.
`0009. There are many commercially successful non-vola
`tile solid-state memory devices being used today. These
`memory devices may be flash EEPROM or may employ other
`types of nonvolatile memory cells. Examples offlash memory
`and systems and methods of manufacturing them are given in
`U.S. Pat. Nos. 5,070,032, 5,095,344, 5,315,541, 5,343,063,
`and 5,661,053, 5,313,421 and 6.222,762. In particular, flash
`memory devices with NAND string structures are described
`in U.S. Pat. Nos. 5,570,315, 5,903,495, 6,046,935. Also non
`Volatile memory devices are also manufactured from memory
`cells with a dielectric layer for storing charge. Instead of the
`conductive floating gate elements described earlier, a dielec
`tric layer is used. Such memory devices utilizing dielectric
`storage element have been described by Eitan et al., “NROM:
`A Novel Localized Trapping, 2-Bit Nonvolatile Memory
`Cell, IEEE Electron Device Letters, vol. 21, no. 11, Novem
`ber 2000, pp. 543-545. An ONO dielectric layer extends
`across the channel between source and drain diffusions. The
`charge for one data hit is localized in the dielectric layer
`adjacent to the drain, and the charge for the other data bit is
`localized in the dielectric layer adjacent to the source. For
`example, U.S. Pat. Nos. 5,768,192 and 6,011,725 disclose a
`nonvolatile memory cell having a trapping dielectric sand
`wiched between two silicon dioxide layers. Multi-state data
`storage is implemented by separately reading the binary
`states of the spatially separated charge storage regions within
`the dielectric.
`
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`US 2012/0311244 A1
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`Dec. 6, 2012
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`0010. In order to improve read and program performance,
`multiple charge storage elements or memory transistors in an
`array are read or programmed in parallel. Thus, a “page of
`memory elements are read or programmed together. In exist
`ing memory architectures, a row typically contains several
`interleaved pages or it may constitute one page. All memory
`elements of a page will be read or programmed together.
`0011. In flash memory systems, erase operation may take
`as much as an order of magnitude longer than read and pro
`gram operations. Thus, it is desirable to have the erase block
`of Substantial size. In this way, the erase time is amortized
`over a large aggregate of memory cells.
`0012. The nature of flash memory predicates that data
`must be written to an erased memory location. If data of a
`certain logical address from a host is to be updated, one way
`is rewrite the update data in the same physical memory loca
`tion. That is, the logical to physical address mapping is
`unchanged. However, this will mean the entire erase block
`contain that physical location will have to be first erased and
`then rewritten with the updated data. This method of update is
`inefficient, as it requires an entire erase block to be erased and
`rewritten, especially if the data to be updated only occupies a
`small portion of the erase block. It will also result in a higher
`frequency of erase recycling of the memory block, which is
`undesirable in view of the limited endurance of this type of
`memory device.
`0013 Data communicated through external interfaces of
`host systems, memory systems and other electronic systems
`are addressed and mapped into the physical locations of a
`flash memory system. Typically, addresses of data files gen
`erated or received by the system are mapped into distinct
`ranges of a continuous logical address space established for
`the system in terms of logical blocks of data (hereinafter the
`“LBA interface'). The extent of the address space is typically
`sufficient to cover the full range of addresses that the system
`is capable of handling. In one example, magnetic disk storage
`drives communicate with computers or other host systems
`through Such a logical address space. This address space has
`an extent Sufficient to address the entire data storage capacity
`of the disk drive.
`0014 Flash memory systems are most commonly pro
`vided in the form of a memory card or flash drive that is
`removably connected with a variety of hosts such as a per
`Sonal computer, a camera or the like, but may also be embed
`ded within such host systems. When writing data to the
`memory, the host typically assigns unique logical addresses
`to sectors, clusters or other units of data within a continuous
`virtual address space of the memory system. Like a disk
`operating system (DOS), the host writes data to, and reads
`data from, addresses within the logical address space of the
`memory system. A controller within the memory system
`translates logical addresses received from the host into physi
`cal addresses within the memory array, where the data are
`actually stored, and then keeps track of these address trans
`lations. The data storage capacity of the memory system is at
`least as large as the amount of data that is addressable over the
`entire logical address space defined for the memory system.
`0015. In current commercial flash memory systems, the
`size of the erase unit has been increased to a block of enough
`memory cells to store multiple sectors of data. Indeed, many
`pages of data are stored in one block, and a page may store
`multiple sectors of data. Further, two or more blocks are often
`operated together as metablocks, and the pages of such blocks
`logically linked together as metapages. A page or metapage of
`
`data are written and read together, which can include many
`sectors of data, thus increasing the parallelism of the opera
`tion. Along with Such large capacity operating units the chal
`lenge is to operate them efficiently.
`0016 For ease of explanation, unless otherwise specified,
`it is intended that the term “block' as used herein refer to
`either the block unit of erase or a multiple block “metablock.”
`depending upon whether metablocks are being used in a
`specific system. Similarly, reference to a “page’ herein may
`refer to a unit of programming within a single block or a
`"metapage' within a metablock, depending upon the system
`configuration.
`(0017. When the currently prevalent LBA interface to the
`memory system is used, files generated by a host to which the
`memory is connected are assigned unique addresses within
`the logical address space of the interface. The memory system
`then commonly maps data between the logical address space
`and pages of the physical blocks of memory. The memory
`system keeps track of how the logical address space is
`mapped into the physical memory but the host is unaware of
`this. The host keeps track of the addresses of its data files
`within the logical address space but the memory system oper
`ates with little or no knowledge of this mapping.
`0018. Another problem with managing flash memory sys
`tem has to do with system control and directory data. The data
`is produced and accessed during the course of various
`memory operations. Thus, its efficient handling and ready
`access will directly impact performance. It would be desir
`able to maintain this type of data in flash memory because
`flash memory is meant for storage and is nonvolatile. How
`ever, with an intervening file management system between
`the controller and the flash memory, the data can not be
`accessed as directly. Also, System control and directory data
`tends to be active and fragmented, which is not conducive to
`storing in a system with large size block erase. Convention
`ally, this type of data is set up in the controller RAM, thereby
`allowing direct access by the controller. After the memory
`device is powered up, a process of initialization enables the
`flash memory to be scanned in order to compile the necessary
`system control and directory information to be placed in the
`controller RAM. This process takes time and requires con
`troller RAM capacity, all the more so with ever increasing
`flash memory capacity.
`00.19
`U.S. Pat. No. 6,567,307 discloses a method of deal
`ing with sector updates among large erase block including
`recording the update data in multiple erase blocks acting as
`scratch pad and eventually consolidating the valid sectors
`among the various blocks and rewriting the sectors after rear
`ranging them in logically sequential order. In this way, a block
`needs not be erased and rewritten at every slightest update.
`0020 WO 03/027828 and WO 00/49488 both disclose a
`memory system dealing with updates among large erase
`block including partitioning the logical sector addresses in
`Zones. A Small Zone of logical address range is reserved for
`active system control data separate from another Zone for user
`data. In this way, manipulation of the system control data in
`its own Zone will not interact with the associated user data in
`another Zone. Updates are at the logical sector level and a
`write pointerpoints to the corresponding physical sectors in a
`block to be written. The mapping information is buffered in
`RAM and eventually stored in a sector allocation table in the
`main memory. The latest version of a logical sector will
`obsolete all previous versions among existing blocks, which
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`Dec. 6, 2012
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`become partially obsolete. Garbage collection is performed
`to keep partially obsolete blocks to an acceptable number.
`0021
`Prior art systems tend to have the update data dis
`tributed over many blocks or the update data may render
`many existing blocks partially obsolete. The result often is a
`large amount of garbage collection necessary for the partially
`obsolete blocks, which is inefficient and causes premature
`aging of the memory. Also, there is no systematic and efficient
`way of dealing with sequential update as compared to non
`sequential update.
`0022 Flash memory with a block management system
`employing a mixture of sequential and chaotic update blocks
`is disclosed in United States Patent Publication No. US-2005
`0144365-A1 dated Jun. 30, 2005, the entire disclosure of
`which is incorporated herein by reference.
`0023 Prior art has disclosed flash memory systems oper
`ating with a cache and operating in mixed MLC (multi-level
`cell) and SLC (single-level cell) modes and with the SLC
`memory operating as a dedicated cache. However, the cache
`disclosed is mainly to buffer the data between a fast host and
`a slower MLC memory and for accumulation to write to a
`block. These systems mostly treat the cache memory at a high
`level as storage and ignoring the underlying low level oper
`ating considerations of the block structure and its update
`scheme. The following publications are examples of these
`prior art.
`0024. Using RAM in a write cache operating with a flash
`memory has been disclosed in U.S. Pat. No. 5,936,971 to
`Harari et al.
`0025 Partitioning the memory into two portions one oper
`ating in binary and the other in MLC has been disclosed in
`U.S. Pat. No. 5,930,167 to Lee etal and U.S. Pat. No. 6,456,
`528 to Chen, the entire disclosure of which is incorporated
`therein by reference.
`0026. United States Patent Publication Number: Publica
`tion Number: US-2007-0061502-A1 on Mar. 15, 2007 and
`US-2007-0283081-A1 dated Dec. 6, 2007 by Lasser both
`disclose a flash memory operating in mixed MLC and SLC
`modes. A specific portion of the memory is always allocated
`to operate in SLC mode and to serve as a dedicated cache.
`0027. Therefore there is a general need for high capacity
`and high performance non-volatile memory. In particular,
`there is a need to have a high capacity nonvolatile memory
`able to conduct memory operations in large blocks without
`the aforementioned problems.
`
`SUMMARY OF THE INVENTION
`0028. According to a general aspect of the invention, a
`method of operating a non-volatile memory system is pre
`sented, where the memory system includes a controller circuit
`and a memory circuit having an array of non-volatile memory
`cells. A sequence of data is received from a host, where the
`host structures data as allocation units. The received sequence
`of data is written into a first section of the array in a series of
`binary format pages, wherein the size of allocation unit cor
`responds to multiple binary pages. The data written in binary
`format pages is folded into the array in a multi-state format.
`The folding operation includes: reading data from N of the
`pages written in binary format into registers associated with
`the array, where N is an integer greater than one; and Subse
`quently performing a N-State per cell programming operation
`of the N pages from the registers into a second section of the
`array, wherein the N-state per cell programming operations a
`first phase and a second phase. The controller circuit balances
`
`the writing pages of binary format pages and Subsequent
`folding operations of the sequence of data, including selec
`tively interleaving first and second phases of the N-state per
`cell programming operations betweenwriting pages of binary
`format pages, to provide uniform performance across differ
`ent allocation units of the sequence of data.
`0029. In other aspects of the invention, a method of oper
`ating a non-volatile memory system is presented, where the
`memory system includes a controller circuit and a memory
`circuitry having multiple semi-autonomous memory arrays
`of non-volatile memory cells. A sequence of data is received
`from a host, where the host structures data as allocation units.
`The received sequence of data is written into a first section of
`each of a plurality of the arrays in a series of binary format
`pages, wherein the size of allocation unit corresponds to
`multiple binary pages. For each of the plurality of arrays, the
`data written in binary format pages is folded into the array in
`a multi-state format, wherein the folding operation includes:
`reading data from N of the pages written in binary format into
`registers associated with the array, where N is an integer
`greater than one; and Subsequently performing a N-State per
`cell programming operation of the N pages from the registers
`into a second section of the array, wherein the N-state per cell
`programming operations a first phase and a second phase. The
`controller circuit balances between the plurality of the semi
`autonomous memory arrays of the writing pages of binary
`format pages and Subsequent folding operations of the
`sequence of data to provide uniform performance between
`the plurality of the semi-autonomous memory arrays the
`across different allocation units of the sequence of data.
`0030. According to other aspects, a method of operating a
`non-volatile memory system is presented, where the memory
`system includes one or more arrays each formed of multiple
`blocks of non-volatile memory cells, and a controller circuit
`connected to the memory circuit to control the transfer of data
`between the memory system a host and manage the storage of
`data on the memory circuit. The controller circuit maintains
`ofalist of free blocks from which the controller circuit selects
`blocks for the writing of data, the list of free block including
`a first portion of one or more blocks and a reserve portion of
`one or more blocks. The method further includes receiving a
`command from the host and the controller circuit determining
`whether or not the command belongs to a specified set of
`commands. In response to determining that the command
`belongs to the specified set, the controller circuit selects
`blocks from the first and reserve portions as needed to execute
`the command. In response to determining that the command
`does not belong to the specified set, the controller circuit
`selects blocks from the first portion, but not the reserve por
`tion, as needed to execute the command.
`0031. Various aspects, advantages, features and embodi
`ments of the present invention are included in the following
`description of exemplary examples thereof, which descrip
`tion should be taken in conjunction with the accompanying
`drawings. All patents, patent applications, articles, other pub
`lications, documents and things referenced herein are hereby
`incorporated herein by this reference in their entirety for all
`purposes. To the extent of any inconsistency or conflict in the
`definition or use of terms between any of the incorporated
`publications, documents or things and the present applica
`tion, those of the present application shall prevail.
`BRIEF DESCRIPTION OF THE DRAWINGS
`0032 FIG. 1 illustrates schematically the main hardware
`components of a memory system suitable for implementing
`the present invention.
`
`Micron Ex. 1044, p.38
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`IPR2021-01547
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`US 2012/0311244 A1
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`Dec. 6, 2012
`
`0033 FIG. 2 illustrates schematically a non-volatile
`memory cell.
`0034 FIG. 3 illustrates the relation between the source
`drain current I, and the control gate Vo