(19) United States
`(12) Patent Application Publication (10) Pub. No.: US 2006/0053246A1
`(43) Pub. Date:
`Mar. 9, 2006
`Lee
`
`US 20060053246A1
`
`(54) SYSTEMS AND METHODS FOR PROVIDING
`NONVOLATILE MEMORY MANAGEMENT
`IN WIRELESS PHONES
`(76) Inventor: Schweiray Joseph Lee, San Diego, CA
`(US)
`Correspondence Address:
`KNOBBE MARTENS OLSON & BEAR LLP
`2040 MAIN STREET
`FOURTEENTH FLOOR
`IRVINE, CA 92614 (US)
`(21) Appl. No.:
`11/215,744
`(22) Filed:
`Aug. 30, 2005
`Related U.S. Application Data
`(60) Provisional application No. 60/605,265, filed on Aug.
`30, 2004. Provisional application No. 60/611,219,
`filed on Sep. 20, 2004.
`
`Publication Classification
`
`(51) Int. Cl.
`(2006.01)
`G06F 12/14
`(52) U.S. Cl. .............................................................. 711/100
`(57)
`ABSTRACT
`The present invention is related to memory management,
`and in particular, to methods and Systems for accessing and
`managing nonvolatile, Such as in a wireleSS phone. A wire
`leSS phone memory controller is disclosed that, comprises a
`first interface circuit configured to be coupled to wireleSS
`phone nonvolatile memory, a Second interface circuit con
`figured to be coupled to wireleSS phone volatile memory, a
`first processor interface configured to be coupled to a first
`wireleSS phone processor, wherein the first processor inter
`face is configured to provide the first processor with access
`to the wireleSS phone volatile memory, a Second processor
`interface configured to be coupled to a Second wireleSS
`phone processor, and a controller circuit configured to copy
`at least a portion of wireleSS phone nonvolatile memory data
`to the wireleSS phone volatile memory.
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
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`-----------------------------
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`external
`electronics
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`Control Circuit
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`Secondary
`Processor
`
`Secondary
`Processor 2
`
`V 206
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`Cellular Phone Electronic System V 2O2
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`201
`
`
`
`Micron Ex. 1033, p. 1
`Micron v. Vervain
`IPR2021-01547
`
`

`

`Patent Application Publication Mar. 9, 2006 Sheet 1 of 32
`
`US 2006/0053246A1
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`Micron Ex. 1033, p. 2
`Micron v. Vervain
`IPR2021-01547
`
`

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`Patent Application Publication Mar. 9, 2006 Sheet 2 of 32
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`US 2006/0053246A1
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`Micron Ex. 1033, p. 3
`Micron v. Vervain
`IPR2021-01547
`
`

`

`Patent Application Publication
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`US 2006/0053246A1
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`Micron Ex. 1033, p. 4
`Micron v. Vervain
`IPR2021-01547
`
`

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`Patent Application Publication Mar. 9, 2006 Sheet 4 of 32
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`US 2006/0053246A1
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`Micron Ex. 1033, p. 5
`Micron v. Vervain
`IPR2021-01547
`
`

`

`Patent Application Publication Mar. 9, 2006 Sheet 5 of 32
`
`US 2006/0053246A1
`
`
`
`Micron Ex. 1033, p. 6
`Micron v. Vervain
`IPR2021-01547
`
`

`

`Patent Application Publication Mar. 9, 2006 Sheet 6 of 32
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`US 2006/0053246A1
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`Micron Ex. 1033, p. 7
`Micron v. Vervain
`IPR2021-01547
`
`

`

`Patent Application Publication Mar. 9, 2006 Sheet 7 of 32
`
`US 2006/0053246A1
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`Micron Ex. 1033, p. 8
`Micron v. Vervain
`IPR2021-01547
`
`

`

`Patent Application Publication Mar. 9, 2006 Sheet 8 of 32
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`US 2006/0053246A1
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`Micron Ex. 1033, p. 9
`Micron v. Vervain
`IPR2021-01547
`
`

`

`Patent Application Publication Mar. 9, 2006 Sheet 9 of 32
`
`US 2006/0053246A1
`
`FIG. 9
`
`902 N
`
`boot
`Section
`
`FMM program code
`
`system boot code
`
`901
`
`Entire NAND
`flash logical
`storage space
`
`FMM-
`controlled
`section
`l/
`
`903
`
`Other program codes
`(e.g. operating System,
`application software
`etc.), user data and
`FMM book-keeping
`records
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`/ 906
`No address
`translation
`
`
`
`904
`No address
`translation
`
`905
`
`/ 907
`Logical-to-physical
`translation based on
`FMM algorithms
`
`FMM program code
`
`system boot code
`
`Other program codes
`(e.g. operating system,
`application Software,
`etc.), user data and
`FMM book-keeping
`records
`
`908
`
`/
`Entire NAND
`flash physical
`storage space
`
`Micron Ex. 1033, p. 10
`Micron v. Vervain
`IPR2021-01547
`
`

`

`Patent Application Publication Mar. 9, 2006 Sheet 10 of 32
`
`US 2006/0053246A1
`
`1001
`
`1002
`
`BOOT CTLR generates
`first PPA of boot Section
`
`BOOT CTLR configures FLASHCTLR
`to read NAND flash page of this PPA
`
`BOOT. CTLR activates FLASH CTLR
`
`1003
`
`1004
`
`FLASH CTLR idle?
`
`yes
`
`1 OO6
`
`FIG. 10
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`FMM program code
`
`FMM program code or
`t
`?
`system boot code
`
`System boot code
`1008
`
`BOOTCTLR copies data
`from PAGE BUFF to
`FMMRAM
`
`BOOT CTLR copies data
`from PAGE BUFF to
`BOOT RAM
`
`1010
`
`BOOT CTLR
`generates the next
`PPA
`
`1009
`
`More pages
`irred
`in boot section
`
`d
`
`BOOT CTLR initializes SDRAM
`
`BOOTCTLR releases FMM from idle
`
`
`
`FMM executes FMM program and
`initializes FMM Scheme
`
`1014
`
`yes
`
`BOOT. CTLR releases Primary
`Processor from reset
`
`BOOTCTLR becomes idle and
`Primary Processor executes system
`initialization program in BOOT RAM
`
`Normal Operation Mode
`
`1017
`
`1011
`
`1012
`
`1013
`
`1015
`
`1016
`
`Micron Ex. 1033, p. 11
`Micron v. Vervain
`IPR2021-01547
`
`

`

`Patent Application Publication Mar. 9, 2006 Sheet 11 of 32
`
`US 2006/0053246A1
`
`FIG. 1 1
`
`Primary Processor programs
`DMA CONFIG register
`
`1101
`
`1 102
`
`Primary Processor issues "Download
`DMA Transfer" Command
`
`CMD CTLR activates DMA CTLR
`
`DMA CTLR generates first NAND flash
`LPA & corresponding SDRAM address
`
`1103
`
`1 104
`
`X
`
`1105
`
`DMA CTLR activates FMM to read
`from NAND flash LPA
`
`FMM converts LPA to PPA and
`configures FLASHCTLR for page read
`
`1106
`
`1107
`
`FMM activates FLASH CTLR
`
`
`
`FLASHCTLR idle? d
`
`yeS
`DMA CTLR requests to access
`SDRAM
`
`granted by MAD?
`
`
`
`yes
`DMACTLR transfers one burst of
`page data from PAGE BUFF to
`SDRAM
`
`1113
`
`
`
`
`
`
`
`
`
`1115
`
`
`
`DMA CTLR generates
`next LPA 8.
`corresponding SDRAM
`address
`
`DMA CTLR
`1112
`generates
`yes SDRAM address
`for next burst
`
`1114
`
`ore bursts in page data
`O
`
`More pages to transfer?
`
`O
`CMD CTLR interrupts Primary
`Processor
`
`1116
`
`Micron Ex. 1033, p. 12
`Micron v. Vervain
`IPR2021-01547
`
`

`

`Patent Application Publication Mar. 9, 2006 Sheet 12 of 32
`
`US 2006/0053246A1
`
`1201
`
`12O2
`
`12O3
`
`1204
`
`FIG. 12
`
`Primary Processor programs
`DMA CONFIG register
`
`Primary Processor issues "Upload
`DMA Transfer" Command
`
`CMD CTLR activates DMA CTLR
`
`DMA CTLR generates first NAND flash
`LPA & corresponding SDRAM address
`
`DMACTLR requests to access
`SDRAM
`
`ro- granted by MAD?
`yes
`DMA CTLR transfers one burst of
`page data from SDRAM to
`PAGE BUFF
`
`1208
`
`5More bursts in page data
`
`O
`
`DMA CTLR activates FMM to write to
`NAND flash LPA
`
`FMM converts LPA to PPA and
`configures FLASHCTLR for page
`write
`
`
`
`
`
`
`
`
`
`DMA CTLR
`generates SDRAM
`address for next
`burst
`
`no
`
`FMM activates FLASHCTLR
`
`FLASHCTLR idle?
`yes
`More pages to transfer?
`O
`CMD CTLR interrupts Primary
`Processor
`
`
`
`1214
`
`
`
`DMA CTLR generates
`next LPA 8.
`corresponding SDRAM
`address
`
`1216
`
`Micron Ex. 1033, p. 13
`Micron v. Vervain
`IPR2021-01547
`
`

`

`Patent Application Publication Mar. 9, 2006 Sheet 13 of 32
`
`US 2006/0053246A1
`
`FIG. 13
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Primary Processor
`programs DMA CONFIG
`register to set up DMA to
`download next program to
`SDRAM
`
`Normal Operation Mode
`
`1301
`
`Primary Processor identifies software
`programs needed for user mode
`
`Primary Processor programs
`DMA CONFIG register to set up DMA
`to download first program from NAND
`flash to SDRAM
`
`1302
`
`1303
`
`1304
`
`Primary Processor issues "Download
`DMA Transfer" Command
`
`Primary Processor waits for
`CMD CTLR to interrupt
`
`1305
`
`1306
`
`CMD CTLR interrupt?
`
`yes
`
`1307
`
`yes
`
`more programs
`or user mode?
`
`O
`
`1309
`
`Primary Processor branches to
`execute programs in SDRAM
`
`1310
`
`Micron Ex. 1033, p. 14
`Micron v. Vervain
`IPR2021-01547
`
`

`

`Patent Application Publication Mar. 9, 2006 Sheet 14 of 32
`
`US 2006/0053246A1
`
`Primary Processor receives user
`Command to launch an application
`
`Primary Processor identifies software
`programs needed for this application
`
`Primary Processor programs
`DMA CONFIG register to set up DMA
`to download first program from NAND
`flash to SDRAM
`
`1401
`
`1402
`
`1403
`
`1404
`
`Primary Processor issues "Download
`DMA Transfer" Command
`
`Primary Processor waits for
`CMD CTLR to interrupt
`
`1405
`
`1406
`
`CMD CTLR interrupt?
`
`SS
`y
`
`1407
`
`yes
`
`more programs
`or application?
`O
`
`Primary Processor executes
`application in SDRAM
`
`1409
`
`
`
`
`
`
`
`
`
`Primary Processor
`programs DMA CONFIG
`register to set up DMA to
`download next program to
`SDRAM
`
`Micron Ex. 1033, p. 15
`Micron v. Vervain
`IPR2021-01547
`
`

`

`Patent Application Publication Mar. 9, 2006 Sheet 15 of 32
`
`US 2006/0053246A1
`
`FIG. 15
`
`Primary Processor receives user command to
`activate a Secondary Processor application
`
`Primary Processor identifies software programs
`needed by the Secondary Processor
`
`Primary Processor programs DMA CONFIG
`register to set up DMA to download first
`program from NAND flash to SDRAM
`
`
`
`Primary Processor issues "Download DMA
`Transfer" Command
`
`1501
`
`1502
`
`1503
`
`1504
`
`
`
`
`
`Primary Processor
`programs DMA CONFIG
`register to set up DMA to
`download next program to
`SDRAM
`
`Primary Processor waits for
`CMD CTLR to interrupt
`
`MD CTLR interrupt
`yes
`
`1505
`
`1506
`
`1507
`
`SS
`
`ore programs
`needed?
`
`O
`Primary Processor programs
`SDRAMPARTITION register to set SDRAM
`address offset for Secondary Processor
`
`Primary Processor writes to RESET register to
`release Secondary Processor from reset
`
`Secondary Processor executes programs in
`SDRAM at the offset SDRAM address
`
`
`
`
`
`1509
`
`1510
`
`1511
`
`interrupt received?
`yes
`
`Primary Processor reads iNTRECORD
`register to determine interrupt source
`
`1512
`
`1513
`
`1514
`
`Primary Processor writes to RESET register to
`put Secondary Processor back into reset
`
`Micron Ex. 1033, p. 16
`Micron v. Vervain
`IPR2021-01547
`
`

`

`Patent Application Publication
`
`Mar. 9, 2006 Sheet 16 of 32
`
`US 2006/0053246A1
`
`
`
`?SelJ ONV/N
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`Micron Ex. 1033, p. 17
`Micron v. Vervain
`IPR2021-01547
`
`

`

`Patent Application Publication Mar. 9, 2006 Sheet 17 of 32
`
`US 2006/0053246A1
`
`FIG. 17
`
`BOOTCTLR generates
`first PPA of boot Section
`
`17
`O2
`
`BOOT CTLR configures FLASHCTLR
`to read NAND flash page of this PPA
`
`1703
`
`1704
`
`BOOTCTLR activates FLASHCTLR
`-6. 1705
`FLASHCTLR idle?
`yes
`
`1708
`
`1706
`FMM program code
`System boot Code
`FMM program code
`BOOTCTLR requests to
`access 1 SDRAM address
`or system boot Code?
`no-a
`1709
`granted by MAD?
`1710
`yes
`BOOT CTLR transfers one
`burst of page data from
`PAGE BUFF to SDRAM
`
`BOOT CTLR copies
`data from
`PAGE BUFF to
`FMM RAM
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`BOOT CTLR yes
`generates the
`next PPA
`
`a-
`ore pages in boot section
`O
`
`1714.
`
`BOOTCTLR releases FMM from idle
`
`1711
`
`O
`
`1713
`
`ore bursts in page
`yes
`
`BOOT. CTLR
`generates
`SDRAM
`address for
`next burst
`
`1715
`
`
`
`1716
`
`
`
`FMM executes FMM program and
`initializes FMM Scheme
`
`1717
`
`yeS
`BOOT CTLR releases Primary
`Processor from reset
`
`BOOT CTLR becomes idle and
`Primary Processor executes system
`boot Code in SDRAM
`
`Normal Operation Mode
`
`1720
`
`1718
`
`1719
`
`Micron Ex. 1033, p. 18
`Micron v. Vervain
`IPR2021-01547
`
`

`

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`Micron v. Vervain
`IPR2021-01547
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`Micron Ex. 1033, p. 19
`Micron v. Vervain
`IPR2021-01547
`
`
`
`
`

`

`Patent Application Publication Mar. 9, 2006 Sheet 19 of 32
`
`US 2006/0053246A1
`
`FIG. 19
`
`BOOTCTLR generates
`first PPA of boot Section
`
`1902
`
`BOOTCTLR configures FLASHCTLR
`to read NAND flash page of this PPA
`
`BOOTCTLR activates FLASHCTLR
`
`1903
`
`1904
`
`FLASHCTLR idle?
`
`1906
`
`yes
`
`BOOT. CTLR copies
`data from
`PAGE BUFF to
`FMM RAM
`
`
`
`
`
`
`
`
`
`BOOT. CTLR yes
`generates the
`next PPA
`
`
`
`
`
`More pages in
`boot section?
`
`O
`
`1908
`
`
`
`
`
`
`
`BOOTCTLR releases FMM from idle,
`FMM performs initialization including
`copying system boot code from NAND
`flash to SDRAM
`
`=-FMM ided-l
`
`yes
`BOOTCTLR releases Primary
`Processor from reset
`
`BOOT CTLR becomes idle and
`Primary Processor executes system
`boot code in SDRAM
`
`1907
`
`1909
`
`1910
`
`1911
`
`1912
`
`Normal Operation Mode
`
`1913
`
`Micron Ex. 1033, p. 20
`Micron v. Vervain
`IPR2021-01547
`
`

`

`Patent Application Publication
`
`US 2006/0053246A1
`
`
`
`
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`Micron Ex. 1033, p. 21
`Micron v. Vervain
`IPR2021-01547
`
`

`

`Patent Application Publication Mar. 9, 2006 Sheet 21 of 32
`
`US 2006/0053246A1
`
`
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`Micron Ex. 1033, p. 22
`Micron v. Vervain
`IPR2021-01547
`
`

`

`US 2006/0053246A1
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`Patent Application Publication
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`Mar. 9, 2006 Sheet 22 of 32
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`Micron Ex. 1033, p. 23
`Micron v. Vervain
`IPR2021-01547
`
`

`

`Patent Application Publication Mar. 9, 2006 Sheet 23 of 32
`
`US 2006/0053246A1
`
`FIG. 23
`
`
`
`
`
`
`
`
`
`
`
`
`
`LCD CTLR generates
`SDRAM address for next
`burst transfer
`
`Primary Processor programs
`LCD CONFIG register
`
`Primary Processor issues "LCD Write"
`Command
`
`CMD CTLR activates LCD CTLR to
`copy data from SDRAM to LCD screen
`
`LCD CTLR generates SDRAM
`address for first burst transfer
`
`2301
`
`2302
`
`2303
`
`2304
`
`a
`
`2305
`
`LCD CTLR requests to access
`SDRAM
`
`re- granted by MAD?
`yes
`
`2306
`
`LCD CTLR transfers one burst of data
`from SDRAM to LCD Screen
`
`2307
`
`2308
`
`O
`LCD CTLR interrupts Primary
`Processor
`
`231 O
`
`Micron Ex. 1033, p. 24
`Micron v. Vervain
`IPR2021-01547
`
`

`

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`Patent Application Publication Mar. 9, 2006 Sheet 24 of 32
`
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`Micron Ex. 1033, p. 25
`Micron v. Vervain
`IPR2021-01547
`
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`Micron Ex. 1033, p. 25
`Micron v. Vervain
`IPR2021-01547
`
`
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`

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`Micron Ex. 1033, p. 26
`Micron v. Vervain
`IPR2021-01547
`
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`Micron Ex. 1033, p. 26
`Micron v. Vervain
`IPR2021-01547
`
`
`
`

`

`Patent Application Publication Mar. 9, 2006 Sheet 26 of 32
`
`US 2006/0053246A1
`
`FIG. 26
`
`Primary Processor programs
`M
`FIG redi
`C-CON
`register
`
`26O1
`
`26O2
`
`Primary Processor issues "MC Write"
`Command
`
`CMD CTLR activates MC CTLR to
`copy data from SDRAM to MC
`
`MCCTLR generates SDRAM address
`for first burst transfer
`
`
`
`MCCTLR requests to access SDRAM
`
`granted by MAD?
`
`yes
`
`MCCTLR transfers one burst of data
`from SDRAM to MC
`
`2603
`
`2604
`
`2605
`
`26O7
`
`MC CTLR generates
`SDRAM address for next
`burst transfer
`
`
`
`S
`
`2608
`
`O
`MC CTLR interrupts Primary
`Processor
`
`2610
`
`
`
`
`
`Micron Ex. 1033, p. 27
`Micron v. Vervain
`IPR2021-01547
`
`

`

`Patent Application Publication Mar. 9, 2006 Sheet 27 of 32
`
`US 2006/0053246A1
`
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`Micron Ex. 1033, p. 28
`Micron v. Vervain
`IPR2021-01547
`
`

`

`Patent Application Publication Mar. 9, 2006 Sheet 28 of 32
`
`US 2006/0053246A1
`
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`Micron Ex. 1033, p. 29
`Micron v. Vervain
`IPR2021-01547
`
`

`

`Patent Application Publication Mar. 9, 2006 Sheet 29 of 32
`
`US 2006/0053246A1
`
`
`
`
`
`
`
`
`
`
`
`Micron Ex. 1033, p. 30
`Micron v. Vervain
`IPR2021-01547
`
`

`

`Patent Application Publication Mar. 9, 2006 Sheet 30 of 32
`
`US 2006/0053246A1
`
`
`
`Micron Ex. 1033, p. 31
`Micron v. Vervain
`IPR2021-01547
`
`

`

`Patent Application Publication Mar. 9, 2006 Sheet 31 of 32
`
`US 2006/0053246A1
`
`FIG. 31
`
`Primary Processor programs
`DMA CONFIG register
`
`31 O1
`
`3102
`
`Primary Processor issues "Flash Read"
`Command
`
`CMDCTLR activates DMA CTLR and
`asserts "wait" signal
`
`DMA CTLR generates first NAND flash
`LPA & BOOT RAM address
`
`DMA CTLR activates FMM to read
`from NAND flash LPA
`
`FMM converts LPA to PPA and
`configures FLASHCTLR for page read
`
`FMM activates FLASH CTLR
`
`3103
`
`3104
`
`3105
`
`31 O6
`
`31 O7
`
`e
`
`3.108
`
`FLASHCTLR idle?
`
`yes
`
`3109
`
`s
`
`DMA CTLR transfers page data from
`PAGE BUFF to BOOT RAM
`
`CMD CTLR deasserts "wait"
`
`.
`
`Primary Processor reads from
`BOOT RAM
`
`3112
`
`3110
`
`3111
`
`CMD-CTLR aSSertS
`wait" signal
`
`More pages to transfer?
`
`O
`CMD CTLR interrupts Prima
`
`3115
`
`next LPA 8.
`BOOT RAM address
`
`3114
`
`
`
`
`
`
`
`
`
`
`
`
`
`Micron Ex. 1033, p. 32
`Micron v. Vervain
`IPR2021-01547
`
`

`

`Patent Application Publication Mar. 9, 2006 Sheet 32 of 32
`
`US 2006/0053246A1
`
`FIG. 32
`
`Primary Processor programs
`DMA CONFI
`ist
`G register
`
`32O1
`
`- 3202
`
`Primary Processor issues "Flash Write"
`Command
`
`CMD CTLR activates DMA CTLR
`
`Primary Processor writes data to
`BOOT RAM
`m
`
`DMA CTLR transfers page data from
`BOOT RAM to PAGE BUFF
`
`DMA CTLR generates NAND flash
`LPA
`
`DMA CTLR activates FMM to write to
`NAND flash LPA
`
`FMM converts LPA to PPA and
`configures FLASHCTLR for page
`Write
`
`FMM activates FLASHCTLR
`
`3203
`
`3204
`
`3205
`
`32O6
`
`32O7
`
`3208
`
`3209
`
`- FLASH CTLR idle?
`
`
`
`3210
`
`S
`ye
`
`3211
`
`More pages to transfer?
`
`O
`CMD CTLR interrupts Primary
`Processor
`
`3212
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Micron Ex. 1033, p. 33
`Micron v. Vervain
`IPR2021-01547
`
`

`

`US 2006/0053246 A1
`
`Mar. 9, 2006
`
`SYSTEMS AND METHODS FOR PROVIDING
`NONVOLATILE MEMORY MANAGEMENT IN
`WIRELESS PHONES
`
`PRIORITY APPLICATION
`0001) This application claims the benefit under 35 U.S.C.
`119(e) of U.S. Provisional Application 60/605,265 (filed
`Aug. 30, 2004), and U.S. Provisional Patent Application
`60/611,219 (filed Sep. 20, 2004). The entire disclosure of
`both of these applications is hereby incorporated by refer
`ence herein.
`
`COPYRIGHT RIGHTS
`0002 A portion of the disclosure of this patent document
`contains material that is Subject to copyright protection. The
`copyright owner has no objection to the facsimile reproduc
`tion by any one of the patent document or the patent
`disclosure, as it appears in the Patent and Trademark Office
`patent file or records, but otherwise reserves all copyright
`rights whatsoever.
`
`BACKGROUND OF THE INVENTION
`0003) 1. Field of the Invention
`0004. The present invention is related to memory man
`agement, and in particular, to methods and Systems for
`accessing and managing nonvolatile memory, Such as in a
`wireleSS phone.
`0005 2. Description of the Related Art
`0006 With the advent of Smaller, faster and less power
`consuming electronic components Such as processors,
`memories and ASICs, many cellular phones provide increas
`ingly complex capabilities Such as multimedia information
`and entertainment, commonly referred to as the “applica
`tions”. A cellular phone further includes wireleSS commu
`nication modulation/demodulation capabilities, commonly
`referred to as the “modem”. To handle the modem and the
`application functions, many cellular phone designs include
`two processors whereby the “application processor controls
`the application functions and the “modem processor con
`trols the communication functions. Some cellular phones
`include yet another processor Specifically designed to per
`form digital signal processing (DSP) algorithms. Although
`Single-processor cellular phones do exist, many current
`complex cellular phones include multiple processors. In
`many conventional applications, each processor utilizes both
`non-volatile and volatile memory to perform their functions.
`0007. In addition, traditionally, NOR Flash memory has
`been commonly used as the cellular phone's non-volatile
`memory. In recent years, Several new Flash memory tech
`nologies have emerged on the market. These relatively new
`high density Flash memories, such as AND Flash memory
`and NAND Flash memory, are designed to have lower costs,
`Smaller sizes and higher Storage capacities than NOR Flash
`memory. Thus high density Flash memory technology is
`often the preferred technology for non-volatile mass data
`Storage in complex cellular phones. However, many con
`ventional cellular phones that currently use NOR Flash
`cannot use AND or NAND Flash memory as a drop-in
`replacement without making design and/or circuit board
`modification. This is because these high-density Flash tech
`
`nologies have different characteristics than NOR Flash
`memory, and So necessitate Special treatment.
`0008 For example, high-density Flash memory is typi
`cally accessed in page-mode, with Significant initial access
`time, and thus is not Suitable for a processor to execute
`program code out of, as processor's typically need random
`acceSS on a byte or word level. Therefore, program code
`Stored in high-density Flash memory is usually first moved
`to RAM memory and then the processor executes the
`program codes from the RAM. In addition, high-density
`Flash memory often has a higher probability of introducing
`errors to the data stored therein as compared to NOR Flash
`memory, and thus Error Correction Coding (ECC) often
`needs to be applied when accessing the high-density Flash.
`Further, high-density Flash memory typically can only
`endure a limited number of erase-rewrite cycles. Flash
`media management techniqueS Such as wear-leveling, gar
`bage collection, bad-block replacement and power-failure
`recovery are often employed to increase the endurance and
`reliability of these Flash memory devices.
`0009. To take advantage of high-density Flash technolo
`gies, many cellular phone System designs have incorporated
`very complex Flash media management algorithms and
`procedures in the System Software to accommodate the
`above-mentioned special characteristics of the high-density
`Flash. These complex algorithms and procedures use up
`plenty of computational/control capacity of the Flash-ac
`cessing processor and thus degrade the performance of the
`System. Therefore, it would be advantageous to have a
`control circuit included in the cellular phone where the
`control circuit performs the algorithms and procedures of the
`Flash media management techniques as well as ECC and
`releases the Flash-accessing processor from Such duties.
`0010. In an electronic system which includes a processor,
`non-volatile memory and Volatile memory, a task commonly
`performed by the processor is moving data from one
`memory to another. An example data movement operation
`involves moving program code from a non-volatile page
`mode memory device to a Volatile random access memory
`device to allow the processor to execute the program code.
`Another example data movement operation involves moving
`data from volatile memory to nonvolatile memory to thereby
`permanently Store the data. Furthermore, in cellular phones
`which provide multimedia functions, Such as graphics and
`Video, the processor(s) often moves image data from memo
`ries to the cellular phone display (e.g., an LCD display) to
`thereby display images. Moving data in and out of memories
`is a very repetitive proceSS which consumes a large amount
`of processor computational/control capacity.
`SUMMARY OF THE INVENTION
`0011. In view of the foregoing, in order to reduce costs
`and the size of the overall size of a wireleSS phone design,
`Such as a cellular phone design, it would be advantageous to
`have a memory management circuit which accommodates
`the multiple processors need for memory capacity without
`requiring that each processor have its own, Separate memory
`management circuit. Reducing the number of cellular
`memory Systems not only reduces the number of memory
`devices, but also makes the data transfer among the proces
`SorS more efficient.
`0012 Further, in view of the foregoing, it would be
`advantageous for a cellular phone to have a memory System
`
`Micron Ex. 1033, p. 34
`Micron v. Vervain
`IPR2021-01547
`
`

`

`US 2006/0053246 A1
`
`Mar. 9, 2006
`
`containing high-density Flash memory, RAM memory, and
`a control circuit that, under the control of one or multiple
`processors, provides a DMA function to transfer data among
`memories, displays (e.g., LCD Screens), and/or an externally
`inserted memory card.
`0013. It would be further advantageous for a cellular
`phone to have a memory System that performs ECC and
`user-defined Flash media management autonomously with
`minimal processor intervention, and allows the processor(s)
`to access the memories within the memory System. Such a
`memory System would allow for consolidating memory
`needs of multiple processors into fewer or even a Single
`memory System, thus reducing the cost and the size of the
`cellular phone. The use of high-density Flash memory for
`mass data Storage can further reduce the phone cost and size.
`In addition, it would be advantageous to relieve the proces
`sors from having to perform the low level functions of
`moving data, performing ECC and Flash media manage
`ment, to thereby improve cellular phone System perfor
`CC.
`However, it should be understood that not all the
`0.014.
`advantages referred to herein need to be achieved by a given
`embodiment of the present invention.
`0.015. One embodiment provides a wireless phone
`memory controller, comprising: a nonvolatile memory con
`troller circuit coupled to nonvolatile memory; a volatile
`memory controller circuit coupled to volatile memory; a
`boot controller circuit coupled to the nonvolatile memory
`controller circuit, the boot controller circuit configured to
`cause user-defined boot program code to be read from
`nonvolatile memory into memory controller memory; a first
`processor interface, including a first reset Signal, coupled to
`a first wireleSS phone processor, wherein, the memory con
`troller is configured to release the first wireleSS phone
`processor from a reset State after the user-defined code is
`read into the memory controller memory; a Second processor
`interface, including a Second reset Signal, coupled to a
`Second wireleSS phone processor, wherein the Second reset
`Signal is configured to be controlled at least in part by the
`first processor.
`0016. Another embodiment provides a method of trans
`ferring data from wireleSS phone nonvolatile memory, the
`proceSS comprising: after a power-on reset, generating a first
`address using a boot circuit; accessing data from the wireleSS
`phone's nonvolatile Flash memory, including at least data
`Stored at the first address, Storing the accessed data in a page
`buffer; determining whether the accessed data is boot code
`or Flash memory management code; if the accessed data is
`boot code, copying the data from the page buffer to a boot
`random acceSS memory; and if the accessed data is Flash
`memory management code, copying the data from the page
`buffer to Flash memory management random acceSS
`memory.
`0017 Still another embodiment provides a wireless
`phone memory controller, comprising: a first interface cir
`cuit configured to be coupled to wireleSS phone nonvolatile
`memory; a Second interface circuit configured to be coupled
`to wireleSS phone volatile memory; a first processor inter
`face configured to be coupled to a first wireleSS phone
`processor, wherein the first processor interface is configured
`to provide the first processor with access to the wireleSS
`phone volatile memory; a Second processor interface con
`
`figured to be coupled to a Second wireleSS phone processor;
`and a controller circuit configured to copy at least a portion
`of wireleSS phone nonvolatile memory data to the wireleSS
`phone volatile memory without intervention by the first
`processor or the Second processor.
`0018 Yet another embodiment provides a method of
`operating a wireleSS phone memory circuit, the method
`comprising: deasserting a reset Signal, generating a first
`address corresponding to boot data Stored in wireleSS phone
`nonvolatile memory; reading boot program code from the
`wireleSS phone nonvolatile memory beginning at the first
`address, providing error detection with respect to the boot
`program code; correcting at least a first error if a first error
`is detected; loading the boot code, including corrected boot
`code if Such is present, into volatile random acceSS memory;
`loading Flash memory management program code, includ
`ing wear leveling code, from the wireleSS phone nonvolatile
`memory into Flash memory management volatile memory;
`enabling the Flash memory management program code to be
`executed by a Flash memory management circuit, releasing
`a first wireleSS phone processor, coupled to the wireleSS
`phone memory circuit, from a reset State; providing the first
`wireleSS phone processor with access to the boot program
`code; and providing a Second wireleSS phone processor with
`access to code Stored in the volatile memory.
`0019. One embodiment provides a method of performing
`error correction on data Stored or being Stored in a wireleSS
`phone's nonvolatile memory, the method comprising:
`receiving a first page of data configured to be Stored in a
`wireleSS phone nonvolatile memory, the first page including
`user data Stored in a user portion and Spare data Stored in a
`Spare portion; generating page parity data for the first page
`of data; Storing the page parity data in the wireleSS phone
`nonvolatile memory; Storing spare data in the wireleSS phone
`nonvolatile memory; wherein the Spare data includes book
`keeping data for nonvolatile memory management and/or
`System flags, Storing parity data for the Spare data in the
`wireleSS phone nonvolatile memory; reading the Spare data
`from the wireleSS phone nonvolatile memory; reading the
`parity data for the Spare data from the wireleSS phone
`nonvolatile memory; and performing error detection and
`error correction, if needed, on the Spare data from the
`wireleSS phone nonvolatile memory using the Spare data
`parity information.
`0020. One embodiment provides a wireless phone
`memory System, comprising: a first port coupled to wireleSS
`phone nonvolatile memory; a Second port circuit coupled to
`wireleSS phone volatile memory; a first processor interface
`coupled to a first wireleSS phone processor, wherein the first
`processor interface is configured to provide the first proces
`Sor with access to the wireleSS phone volatile memory; and
`a Second processor interface coupled to a Second wireleSS
`phone processor, wherein one of the first and Second pro
`ceSSorS is configured to provide modem control.
`0021 Another embodiment provides a wireless phone
`memory controller device, comprising: a first port config
`ured to be coupled to wireleSS phone nonvolatile memory; a
`Second port circuit configured to be coupled to a modem
`processor of a wireleSS phone; a volatile boot memory; a
`boot controller configured to copy boot code from the
`wireless phone nonvolatile memory to the volatile boot
`memory; a direct memory access controller configured to
`
`Micron Ex. 1033, p. 35
`Micron v. Vervain
`IPR2021-01547
`
`

`

`US 2006/0053246 A1
`
`Mar. 9, 2006
`
`copy data from the nonvolatile memory to the volatile boot
`memory