(19) United States
`(12) Patent Application Publication (10) Pub. No.: US 2015/0214476A1
`(43) Pub. Date:
`Jul. 30, 2015
`Matsui et al.
`
`US 20150214476A1
`
`SEMCONDUCTOR MEMORY
`
`Publication Classification
`
`(54)
`(71)
`
`(72)
`
`(21)
`(22)
`
`(63)
`
`Applicant: Renesas Electronics Corporation,
`Kawasaki-shi (JP)
`Inventors: Yuichi Matsui, Kawasaki (JP): Nozomu
`Matsuzaki, Kokubunji (JP); Norikatsu
`Takaura, Tokyo (JP): Naoki Yamamoto,
`Kochi (JP); Hideyuki Matsuoka, Tokyo
`(JP); Tomio Iwasaki, Tsukuba (JP)
`Appl. No.: 14/683,112
`Filed:
`Apr. 9, 2015
`
`Related U.S. Application Data
`Continuation of application No. 13/493,442, filed on
`Jun. 11, 2012, now abandoned, which is a continuation
`of application No. 12/613,235, filed on Nov. 5, 2009,
`now Pat. No. 8,890,107, which is a continuation of
`application No. 1 1/596,220, filed on Nov. 14, 2006,
`now abandoned, filed as application No. PCT/JP05/
`08419 on May 9, 2005.
`Foreign Application Priority Data
`
`(30)
`May 14, 2004
`
`(JP) ................................. 2004-144704
`
`(51) Int. Cl.
`HOIL 45/00
`HOIL 27/24
`(52) U.S. Cl.
`CPC ................ HOIL 45/06 (2013.01); HOIL 45/12
`(2013.01); HOIL 45/1253 (2013.01); HOIL
`45/1233 (2013.01); HOIL 27/2436 (2013.01)
`
`(2006.01)
`(2006.01)
`
`(57)
`
`ABSTRACT
`
`Manufacturing processes for phase change memory have Suf
`fered from the problem of chalcogenide material being Sus
`ceptible to delamination, since this material exhibits low
`adhesion to high melting point metals and silicon oxide films.
`Furthermore, chalcogenide material has low thermal stability
`and hence tends to Sublime during the manufacturing process
`of phase change memory. According to the present invention,
`conductive or insulative adhesive layers are formed over and
`under the chalcogenide material layer to enhance its delami
`nation strength. Further, a protective film made up of a nitride
`film is formed on the sidewalls of the chalcogenide material
`layer to prevent Sublimation of the chalcogenide material
`layer.
`
`Continuous
`or discontinuous
`film
`
`
`
`SY
`
`
`
`
`
`
`
`Micron Ex. 1032, p. 1
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`IPR2021-01547
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`Patent Application Publication
`
`Jul. 30, 2015 Sheet 1 of 12
`
`US 2015/0214476 A1
`
`Continuous
`or discontinuous
`film
`N
`
`
`
`
`
`
`
`
`
`272
`
`122-1722222
`
`EMPERATURE
`
`MELTING POINT ---------1-----------------------------------
`RESET PULSE (AMORPHIZATION)
`SET PUSE
`N- (CRYSTALLIZATION)
`
`
`
`CRYSTALLIZATION
`TEMPERATURE
`
`-- IME
`
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`Patent Application Publication
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`Jul. 30, 2015 Sheet 2 of 12
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`US 2015/0214476 A1
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`FIG 3
`E
`3
`
`
`
`>
`
`
`
`
`
`FIG-4
`
`
`
`
`
`2
`
`Micron Ex. 1032, p. 3
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`Patent Application Publication
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`Jul. 30, 2015 Sheet 3 of 12
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`US 2015/0214476 A1
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`FIG5
`
`
`
`
`
`
`
`
`
`
`
`
`
`FIG.6A
`
`O -
`
`
`
`O -
`
`O -
`
`1 O -
`
`O
`
`T/e=74 (Ge)
`OO 2OO 3OO 400 5OO
`
`TEMPERATURE (C)
`
`Micron Ex. 1032, p. 4
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`IPR2021-01547
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`Patent Application Publication
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`Jul. 30, 2015 Sheet 4 of 12
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`US 2015/0214476 A1
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`FIG.6B
`
`10-11
`
`10-12
`
`1013
`
`O -14
`O
`
`mAe=121 (Sb)
`OO 2OO 3OO 4OO 5OO
`
`TEMPERATURE (C)
`
`FIG-6C
`
`10-11
`
`0-12
`
`10-13
`
`0-4
`O
`
`m/e=128 (e)
`1 OO 2OO 3OO AOO 5OO
`
`TEMPERATURE (C)
`
`Micron Ex. 1032, p. 5
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`Patent Application Publication
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`Jul. 30, 2015 Sheet 5 of 12
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`US 2015/0214476 A1
`
`s
`s
`9.
`2
`ca
`
`f
`
`
`
`O
`
`103
`
`101
`
`10
`
`103
`
`O 5
`
`O7
`O
`
`2OO
`
`4.OO
`
`6OO
`
`8OO
`
`OOO
`
`TEMPERATURE (C)
`
`Micron Ex. 1032, p. 6
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`Patent Application Publication
`
`Jul. 30, 2015 Sheet 6 of 12
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`US 2015/0214476 A1
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`FIG.8
`
`50
`
`40
`
`30
`
`20
`
`10
`O Q ()
`WAO W
`ADHESION
`AYER
`
`AI
`
`AN AIO
`
`is
`
`TiN
`
`TO
`
`MATERIALS OF ADHESON LAYER
`
`FIG.9A
`
`TEMPERATURE (C)
`
`109 2OO
`
`16O
`
`20
`
`
`
`50
`
`3O
`
`HEAEING
`
`24,
`
`26
`
`28
`
`32
`30
`1/kT (eV)
`
`34
`
`36
`
`38
`
`Micron Ex. 1032, p. 7
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`Patent Application Publication
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`Jul. 30, 2015 Sheet 7 of 12
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`US 2015/0214476A1
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`FIG.9B
`
`TEMPERATURE (C)
`
`2OO
`
`50
`
`100
`
`7O
`
`5O 2O
`
`HEATING
`- - - - - - -
`-C-
`
`- - - - - u - COOLING
`
`24 26 28 30 32 34 36 38 40
`1/kT (eV)
`
`
`
`Micron Ex. 1032, p. 8
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`Patent Application Publication
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`Jul. 30, 2015 Sheet 8 of 12
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`US 2015/0214476 A1
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`FIG 11
`
`zzzzzzzzzzzzzzy 1 SE 14 4.
`2 l,
`L.
`N
`3
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Micron Ex. 1032, p. 9
`Micron v. Vervain
`IPR2021-01547
`
`

`

`Patent Application Publication
`
`Jul. 30, 2015 Sheet 9 of 12
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`US 2015/0214476 A1
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`
`
`11 OB
`
`1 O6
`
`Micron Ex. 1032, p. 10
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`IPR2021-01547
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`

`

`Patent Application Publication
`
`Jul. 30, 2015 Sheet 10 of 12
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`US 2015/0214476 A1
`
`
`
`OB
`
`FIG-13
`
`NNNNN
`
`108
`
`1 O2
`10
`
`106
`
`Micron Ex. 1032, p. 11
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`Patent Application Publication
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`Jul. 30, 2015 Sheet 11 of 12
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`US 2015/0214476 A1
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`FIG 4
`
`
`
`1 OB
`
`XXXXXX 8 2
`3
`3
`
`8 s
`
`X
`
`3 & 1 is
`S
`8 sS&
`
`8
`S. 8
`SS -1-1-1-1
`3.
`3.
`
`118
`19
`
`6
`
`23
`112
`
`1 11
`11 OA
`
`O8.
`
`SRS
`SS
`3-S S2
`
`S
`
`8
`
`SS SS
`
`Micron Ex. 1032, p. 12
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`Patent Application Publication
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`Jul. 30, 2015
`
`Sheet 12 of 12
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`FIG 15
`
`
`
`)
`
`Micron Ex. 1032, p. 13
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`IPR2021-01547
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`

`

`US 2015/0214476 A1
`
`Jul. 30, 2015
`
`SEMCONDUCTOR MEMORY
`
`TECHNICAL FIELD
`0001. The present invention relates to a technique that is
`effective when applied to semiconductor integrated circuit
`devices which employ phase change memory cells formed of
`a phase change material Such as chalcogenide.
`
`BACKGROUND ART
`0002 Mobile devices, typified by cellular phones, use a
`semiconductor memory such as a DRAM, SRAM, or flash
`memory. A DRAM provides large capacity but its access
`speed is low. A SRAM, on the other hand, is high-speed
`memory, but is not suitable for forming a large capacity
`memory, since each cell requires a number of transistors (4 to
`6 transistors) and hence it is difficult to produce highly inte
`grated SRAM. DRAM and SRAM must continuously receive
`power to retain data; that is, they are volatile memories. Flash
`memory, on the other hand, is a nonvolatile memory; it does
`not need to continuously receive power to electrically retain
`data. However, the flash memory is disadvantageous in that its
`programferase count is limited to a maximum of approxi
`mately 10 and its reprogramming speed is a few orders of
`magnitude lower than those of other memories. Since each
`memory (described above) has its disadvantage, it is current
`practice to select Suitable memory depending on the applica
`tion.
`0003) If a universal memory having all the advantages of
`DRAM, SRAM, and flash memory were developed, a plural
`ity of memories could be integrated on a single chip, which
`allows cellular phones and other mobile devices to be minia
`turized and enhanced in functionality. If the universal
`memory could replace all other types of memory, it would
`have a tremendous impact (on the semiconductor industry).
`The requirements for universal memory are that: (1) like
`DRAM, it is highly integrated (and hence can have large
`capacity); (2) its access (write/read) speed is high, compa
`rable to that of SRAM; (3) it has the same nonvolatility as
`flash memory; and (4) it exhibits low power consumption and
`hence can be powered by a small battery.
`Among next-generation nonvolatile memories referred to as
`universal memories, phase change memory is currently
`attracting the most attention. Phase change memory uses a
`chalcogenide material, which is also used by CD-RWs and
`DVDs. Like these disks, phase change memory stores data by
`assuming two states: a crystalline state and an amorphous
`state. However, they differ in how data is written to or read
`from them. Specifically, whereas a laser is used to write to or
`read from CD-RWs and DVDs, the Jouleheat generated by an
`electrical current is used to write data to the phase change
`memory and the change in the resistance of the memory due
`to the phase change is read as a data value.
`0004. The principle of operation of phase change memory
`will be described with reference to FIG. 2. When a chalco
`genide material is amorphized. Such a reset pulse is applied
`that causes the chalcogenide material to be rapidly quenched
`after it is heated to a melting point or more. The melting point
`is, for example, 600° C., and the quench time (t1) is, for
`example, 2nsec. When crystallizing the chalcogenide mate
`rial, on the other hand, a set pulse is applied to the memory so
`as to maintain the chalcogenide material at a temperature
`between its crystallization point and melting point. The crys
`
`tallization point is, for example, 400° C., and the time (t2)
`required for the crystallization is, for example, 50 nsec.
`0005. A feature of phase change memory is that the resis
`tance value of the chalcogenide material (of the phase change
`memory) varies by two to three orders of magnitude depend
`ing on its crystallization state. Since (the change in) the resis
`tance value is used as a signal, the read signal is large, facili
`tating the sense operation and hence increasing the speed of
`the read operation. Another feature of the phase change
`memory is that it can be reprogrammed 10' times, which is
`an advantage over flash memory. Still another feature of the
`phase change memory is that it can operate at a low Voltage
`and low power, which allows it to be formed on the same chip
`as logic circuitry. Therefore, phase change memory is Suitable
`for use in mobile devices.
`0006 An exemplary manufacturing process for a phase
`change memory cell will now be briefly described with ref
`erence to FIGS. 3 to 5. First, a select transistor is formed on a
`semiconductor Substrate by a known manufacturing method
`(not shown). The select transistor is made up of a MOS
`transistor or bipolar transistor. Then, an interlayer insulating
`film 1 made up of a silicon oxide film is deposited and a plug
`2 of, for example, tungsten is formed in the interlayer insu
`lating film 1 by a known manufacturing method. This plug is
`used to electrically connect between the select transistor and
`the phase change material layer overlying the select transis
`tor. Then, a chalcogenide material layer 3 of for example,
`GeSbTe, an upper electrode 4 of for example, tungsten, and
`a hard mask 5 made up of for example, a silicon oxide film are
`sequentially deposited, forming the structure shown in FIG.
`3.
`0007. Then, the hard mask5, the upper electrode 4, and the
`chalcogenide material layer3 are processed by a known litho
`graphic technique and dry etching technique, as shown in
`FIG. 4.
`After that, an interlayer insulating film 6 is deposited, as
`shown in FIG. 5.
`Then, a wiring layer electrically connected to the upper elec
`trode 4 is formed on the interlayer insulating film 6, and a
`plurality of other wiring layers are formed on the wiring layer
`on the interlayer insulating film 6, completing formation of
`phase change memory (not shown).
`
`Patent Document 1: Japanese Laid-Open Patent Publication
`No. 2003-174144
`
`Patent Document 2: Japanese Laid-Open Patent Publication
`No. 2003-22953T
`
`DISCLOSURE OF THE INVENTION
`
`Problems to be Solved by the Invention
`0008. There are two problems that make it difficult to
`manufacture phase change memory: the low adhesive
`strength and the low thermal stability of the chalcogenide
`material. How the manufacturing process is affected by each
`problem will be specifically described.
`0009 First, since chalcogenide material has low adhesive
`strength, it tends to delaminate (or peel) during the manufac
`turing process. Since the chalcogenide material is heated to its
`melting point or a higher temperature when the phase change
`memory is in operation (as described above), the plug and the
`upper electrode in contact with the chalcogenide material
`must be formed of a high melting point metal. For example,
`
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`

`US 2015/0214476 A1
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`Jul. 30, 2015
`
`tungsten is a high melting point metal conventionally used in
`semiconductor integrated circuit devices. However, we have
`found that since chalcogenide material (layer) has low adhe
`sion to high melting point metals such as tungsten, it tends to
`delaminate at its interfaces with the plug and the upper elec
`trode. Furthermore, since the chalcogenide material also
`exhibits low adhesion to silicon oxide films, it also tends to
`delaminate at its interface with the interlayer insulating film.
`0010. It is obvious that the manufacturing process
`described with reference to FIGS. 3 to 5 produces a phase
`change memory cell in which the chalcogenide material
`exhibits low adhesion at its upper and lowerinterfaces. There
`fore, there is a need for a means of enhancing the adhesive
`strength of the chalcogenide material (at these interfaces).
`0011 Second, since the thermal stability of chalcogenide
`material is low, it tends to Sublime during the manufacturing
`process. FIGS. 6A to 6C show results of thermal desorption
`spectrometry of a GeSbTe film. This analysis was conducted
`in ultrahigh vacuum (approximately, 107 Pa). When the
`GeSbTe film was heated to approximately 300° C., the ele
`ments Ge, Sb, and Tesublimed at the same time, as shown in
`the figures. The sample was further heated to 500° C. and then
`cooled to room temperature. After this, we retrieved the
`sample and found that the GeSbTe film had completely dis
`appeared. Thus, chalcogenide material has very low thermal
`stability. The low thermal stability of the chalcogenide mate
`rial does not cause problems with CD-RW and DVD manu
`facturing processes, since these processes do not include any
`high-temperature heating process. (That is why CD-RWs and
`DVDs employ a substrate of polycarbonate, which has low
`heat resistance.) However, care must be taken when using a
`chalcogenide material in a semiconductor integrated circuit
`device whose manufacture includes a wiring process in which
`the wafer is heated to 400° C. or higher. FIG. 7 is a graph
`showing the sublimation characteristics of a GeSbTe film,
`wherein the horizontal axis represents temperature and the
`Vertical axis represents pressure. Specifically, the tempera
`ture and pressure at which the GeSbTe film was heat-treated
`were varied. In the figure, each open circle indicates a condi
`tion in which the GeSbTe film did not sublime, while each
`solid circle indicates a condition in which the GeSbTe film
`sublimed. As show in the figure, the lower the pressure under
`which the GeSbTe film was heat-treated, the lower the tem
`perature at which it Sublimed. A manufacturing process of a
`semiconductor integrated circuit device performs, for
`example, chemical vapor phase growth at a pressure of
`approximately 10-10 Pa and a temperature of approxi
`mately 400-700° C.
`As can be seen from FIG. 7, the GeSbTe film will sublime if
`it is directly exposed to these conditions.
`In the manufacturing process described with reference to
`FIGS. 3 to 5, the interlayer insulating film 6 must be formed
`by chemical vapor phase growth, which is Superiorinterms of
`step coverage. As a result, the chalcogenide material layer3
`might sublime at its sidewalls. Therefore, there is a need for a
`means for maintaining the thermal stability of chalcogenide
`material even if a portion of the material is exposed.
`
`Means for Solving the Problems
`0012. The above objects may be achieved by a semicon
`ductor memory device comprising: a semiconductor Sub
`strate; a select transistor formed on a principal Surface of the
`semiconductor Substrate; an interlayer insulating film pro
`vided on the select transistor, a plug provided so as to pen
`
`etrate through the interlayer insulating film, and electrically
`connected to the select transistor, a phase change material
`layer provided so as to extend over the interlayer insulating
`film, and connected with the plug; an upper electrode pro
`vided on the phase change material layer; and an adhesive
`layer provided between an under Surface of the phase change
`material layer and top Surfaces of the interlayer insulating
`film and the plug.
`0013 Further, the above objects may also be achieved by
`a semiconductor memory device comprising: a semiconduc
`tor Substrate; a select transistor formed on a principal Surface
`of the semiconductor Substrate; an interlayer insulating film
`provided on the select transistor, a plug provided so as to
`penetrate through the interlayer insulating film, the plug
`being electrically connected to the select transistor; a phase
`change material layer provided on the interlayer insulating
`film Such that a portion of the phase change material layer is
`connected with the plug; an upper electrode provided on the
`phase change material layer, and a protective film formed on
`at least a sidewall of the phase change material layer and
`containing a silicon nitride.
`
`Effects of the Invention
`
`0014. The major effects of the present invention will now
`be briefly described.
`The adhesive layers formed over and under the chalcogenide
`material layer can prevent delamination of the chalcogenide
`material layer during the manufacturing process. Further, the
`protective film formed on the sidewalls of the chalcogenide
`material layer can prevent Sublimation of the chalcogenide
`material layer during the manufacturing process.
`These arrangements improve the phase change memory
`manufacturing process in Sucha way as to reduce variations in
`the electrical characteristics of the phase change memory, as
`well as preventing reliability degradation.
`
`BEST MODES FOR CARRYING OUT THE
`INVENTION
`
`0015. A first means of the present invention is to form
`adhesive layers over and under the chalcogenide material
`(layer) So as to enhance the adhesive strength of the chalco
`genide material (at its interfaces with the overlying and under
`lying layers).
`(0016 First, the effects of these adhesive layers will be
`described. We formed GeSbTefilms on SiO films to a thick
`ness of 100 nm, and performed a scratch test on these GeSbTe
`films to compare their delamination strength. In a scratch test,
`a thin film Surface of a sample is scratched by an indenter
`while applying a load to the sample in the vertical direction,
`in order to determine the minimum load that cause delami
`nation (referred to as the “critical delamination load'). The
`higher the critical delamination load, the higher the delami
`nation strength. FIG. 8 shows the (critical delamination load)
`measurement results. As shown in FIG. 8, the delamination
`strength of the GeSbTe film was extremely low when an
`adhesive layer was not inserted (between the GeSbTefilm and
`the SiO, film). Further, insertion of a W layer did not lead to
`any improvement in the delamination strength of the GeSbTe
`film. This reflects the fact that chalcogenide material has low
`adhesion to high melting point metals. On the other hand,
`inserting an Al material layer increased the delamination
`
`Micron Ex. 1032, p. 15
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`IPR2021-01547
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`

`US 2015/0214476 A1
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`Jul. 30, 2015
`
`strength of the GeSbTe film by a factor of 7-9, and inserting a
`Ti material layer enhanced the delamination strength by a
`factor of 10-15.
`0017. These results indicate that insertion of an adhesive
`layer may be effective in enhancing the adhesive properties of
`the chalcogenide material. As can be seen from FIG. 8, Ti
`material is Superior to Al material as an adhesive layer. Fur
`ther, nitrides have higher adhesion to chalcogenide material
`than oxides, and individual metals have higher adhesion than
`oxides and nitrides.
`0018. An exemplary manufacturing process of the present
`invention will be described with reference to FIG.1. First, an
`interlayer insulating film 1 and a plug 2 are formed by a
`conventional technique. Then, the following layers are
`sequentially deposited: an adhesive layer 7 of for example,
`titanium; a chalcogenide material layer 3 of for example,
`GeSbTe; an adhesive layer 8 of for example, titanium; an
`upper electrode 4 of for example, tungsten; and a hard mask
`5 made up of for example, a silicon oxide film. Then, the hard
`mask 5, the upper electrode 4, the adhesive layer 8, the chal
`cogenide material layer 3, and the adhesive layer 7 are pro
`cessed by a known lithographic technique and dry etching
`technique, forming the structure shown in FIG. 1.
`0019. Thus, in the above manufacturing process, adhesive
`layers are formed over and under the chalcogenide material
`layer, which increases the delamination strength of the chal
`cogenide material layer and thereby prevents its delamination
`during the manufacturing process.
`It should be noted that although in the above example two
`adhesive layers are formed over and under, respectively, the
`chalcogenide layer, the present invention is not limited to this
`particular arrangement. An adhesive layer may be formed
`only either over or under the chalcogenide layer.
`0020. The desired thickness of the adhesive layers will
`now be described. FIGS.9A and 9B show the temperature vs.
`resistance characteristics of GeSbTe films. Specifically, FIG.
`9A shows the temperature vs. resistance characteristics of a
`GeSbTe film with no adhesive layer. When the GeSbTe film
`set in an amorphous state was heated, it crystallized at
`approximately 120-130° C. and, as a result, its resistance
`rapidly decreased. Then, the film was cooled after being
`heated to approximately 200°C. (as shown in FIG.9A). The
`resistance of the GeSbTe film changed by five or more orders
`of magnitude (between the amorphousand crystalline states).
`Since phase change memory uses the resistance value of the
`chalcogenide material layer as a signal, the larger the change
`in the resistance of the chalcogenide material between amor
`phous and crystalline states, the better. On the other hand,
`FIG.9B shows the temperature vs. resistance characteristics
`of a GeSbTe film with a 2.5 nm thick adhesive layer of
`titanium. In this case, the GeSbTe film had low resistance
`even when it was in an amorphous state. The GeSbTefilm was
`heated to approximately 200°C., so that the film crystallized.
`Then, the GeSbTe film was cooled. The resistance did not
`change much (between the amorphousand crystalline states).
`The reason for this may be that titanium within the adhesive
`layer diffused into the GeSbTe film. This indicates that if the
`adhesive layer has a small thickness, it may degrade the
`characteristics of the phase change memory.
`0021. The thickness of the adhesive layers in phase change
`memory is preferably 5 nm or less although this may vary
`depending on the material of these layers. Further, the thick
`
`ness of the adhesive layers is more preferably 2 nm or less to
`increase the ratio between the resistance values in amorphous
`and crystalline states.
`0022. The desired materials for the adhesive layers will
`now be described. A current (as a set pulse or reset pulse) is
`Supplied from the select transistor to the chalcogenide mate
`rial (layer) through the plug to change the phase of the chal
`cogenide material. To efficiently deliver this current to the
`chalcogenide material, the adhesive layer at the interface
`between the chalcogenide material layer and the plug is pref
`erably electrically conductive. Likewise, the adhesive layer at
`the interface between the chalcogenide material layer and the
`upper electrode is also preferably conductive.
`Further, the Smaller the regions used to change the phase of
`the chalcogenide material, the Smaller the current required for
`reprogramming (the memory cell). That is, to reduce the
`power consumption of the phase change memory cell, all
`regions other than the plug need be insulative (or nonconduc
`tive), and the adhesive layer at the interface between the
`chalcogenide material layer and the interlayer insulating film
`is preferably insulative.
`0023 FIG. 10 shows a phase change memory cell using an
`ideal material for the adhesive layers. Referring to the figure,
`a conductive adhesive layer 9 is formed at the interface
`between a chalcogenide material layer 3 and a plug 2; an
`insulative adhesive layer 10 is formed at the interface between
`the chalcogenide material layer 3 and an interlayer insulating
`film 1; and a conductive adhesive layer 11 is formed between
`the chalcogenide material layer 3 and an upper electrode 4.
`0024 Examples of conductive adhesive layers include Ti,
`Al, Ta, Si, Ti nitride, Al nitride, Ta nitride, W nitride, TiSi,
`TaSi, WSi, TiW, TiA1 nitride. TaSi nitride, TiSi nitride, and
`WSi nitride films. Further, since Te in chalcogenide material
`is reactive with Ti and Al, a layer formed of a compound of Ti
`and Te, or Al and Te, may be used as a conductive adhesive
`layer. Examples of insulative adhesive layers include Ti
`oxide, Al oxide, Ta oxide, Nb oxide, V oxide, Cr oxide, W
`oxide, Zr oxide, Hf oxide, and Si nitride films.
`0025. Further, the adhesive layer at the interface between
`the chalcogenide material layer and the interlayer insulating
`film need not necessarily be insulative (or nonconductive) if
`the chalcogenide material layer is not (fully) electrically con
`nected to the interlayer insulating film. (This also reduces the
`regions used to cause a change in the phase of the chalco
`genide material.) For example, the adhesive layer may be a
`conductive layer having an island shape (i.e., a discontinuous
`conductive layer). In this case, the adhesive layer at the inter
`face between the chalcogenide material layer and the plug and
`the adhesive layer at the interface between the chalcogenide
`material layer and the interlayer insulating film can beformed
`of the same material at the same time. When an adhesive layer
`is formed to an island shape (or when a discontinuous adhe
`sive layer is formed), its thickness is preferably 2 nm or less.
`Further, the thickness of the adhesive layer is more preferably
`1 nm or less to increase or ensure the electrical discontinuity
`(between the chalcogenide material layer and the interlayer
`insulating film). For example, the adhesive layers may be
`formed of titanium to a thickness of 0.5 nm.
`It should be noted that Patent Document 1 (listed above), for
`example, discloses means for using an adhesive layer to
`improve the adhesion between a chalcogenide material and a
`dielectric material. The present invention is different from
`this technique. As described above, in a phase change
`memory cell, the plug and the upper electrode must beformed
`
`Micron Ex. 1032, p. 16
`Micron v. Vervain
`IPR2021-01547
`
`

`

`US 2015/0214476 A1
`
`Jul. 30, 2015
`
`of a high melting point metal such as tungsten. However, we
`have found that the chalcogenide material tends to delaminate
`at its interfaces with Such a plug and upper electrode. The
`present invention has been devised to solve this problem. On
`the other hand, the above known technique (disclosed in
`Patent Document 1) is intended to insert an adhesive layer
`only between a chalcogenide material and an interlayer insu
`lating film (formed of a dielectric material), which is dis
`tinctly different from the technique of the present invention.
`0026. A second means of the present invention is to form
`a protective film on the sidewalls of the chalcogenide material
`layer to ensure the thermal stability of the chalcogenide mate
`rial.
`0027. An exemplary manufacturing process of the present
`invention will be described with reference to FIG.11. First, an
`interlayer insulating film 1 and a plug 2 are formed by a
`conventional technique. Then, a chalcogenide material layer
`3 of, for example, GeSbTe, an upper electrode 4 of for
`example, tungsten, and a hard mask 5 made up of for
`example, a silicon oxide film are sequentially deposited. After
`that, the hard mask 5, the upper electrode 4, and the chalco
`genide material layer 3 are processed by a known lithographic
`technique and dry etching technique. Then, a sidewall pro
`tective film 12 made up of, for example, a silicon nitride film
`is deposited, and an interlayer insulating film 6 is further
`deposited, as shown in FIG. 11.
`Thus, the sidewalls of the chalcogenide material layer that
`have been processed by dry etching are fully covered with the
`protective film, preventing Sublimation of the chalcogenide
`material during the interlayer insulating film forming pro
`CCSS,
`0028. The desired conditions for forming the sidewall pro
`tective film will now be described. Chalcogenide material
`Sublimes when exposed to high temperature, low pressure
`conditions, as described with reference to FIG. 7. Therefore,
`the sidewall protective film must be formed under low tem
`perature, high pressure conditions, which correspond to the
`upper left portion of FIG. 7. Especially, reducing the process
`temperature is effective in preventing sublimation of the chal
`cogenide material. Exemplary conditions are such that the
`pressure is 0.1 Pa or more and the temperature is 450° C. or
`less, although this may vary depending on the chalcogenide
`material.
`0029. The desired material for the sidewall protective film
`will now be described. The sidewall protective film is formed
`by plasma CVD, etc., since it must be formed at low tempera
`ture. If a silicon oxide film is used as the sidewall protective
`film, the sidewalls of the chalcogenide material (layer) are
`exposed to oxygen activated by the plasma. In this case, since
`chalcogenide material is easily oxidized, a portion of the
`chalcogenide material (layer) might be oxidized, resulting in
`degraded characteristics. Therefore, a silicon nitride film is
`preferably used as the sidewall protective film, since it is
`“inactive against chalcogenide material’ (or does not cause
`an oxidation problem Such as that described above) and can
`beformed by CVD, which is a superior technique in terms of
`Step coverage.
`0030. It should be noted that Patent Document 2 (listed
`above), for example, discloses means for forming a protective
`film on the sidewalls of a chalcogenide material (layer) to
`prevent its sublimation. However, this technique is different
`from the present invention in that an oxide film is used as the
`protective film.
`
`Preferred embodiments of the present invention will
`0031
`be described in detail with reference to the accompanying
`drawings. It should be noted that in all figures, like numerals
`are used to denote components having like functions to avoid
`undue repetition.
`
`First Embodiment
`0032. A first embodiment of the present invention will be
`described with reference to FIG. 12. This embodiment pro
`vides an example in which conductive adhesive layers are
`formed both over and under the chalcogenide material layer.
`0033 First of all, a semiconductor substrate 101 is pro
`vided, and a MOS transistor is formed on the substrate as a
`select transistor. Specifically, trenchisolation (or device sepa
`ration) oxide films 102 for isolating the MOS transistor are
`formed in the surface of the semiconductor substrate 101 by
`a known selective oxidation technique or shallow trench iso
`lation technique. The present embodiment uses the shallow
`trench isolation technique, which also can planarize the Sur
`face. First, isolation trenches are formed in the substrate by a
`known dry etching technique. Then, after removing damage
`loft on the sidewalls and bottoms of the trenches in the pre
`vious dry etching process, an oxide film is deposited by a
`known CVD technique. Then, portions of the oxide film other
`than those in the trenches are polished (and thereby removed)
`by a known CMP technique, leaving the trench isolation
`oxide films 102 within the trenches.
`0034. Then, though not shown in the figure, wells of two
`different conductive types are formed by high-energy impu
`rity implantation.
`0035. Then, after cleaning the surface of the semiconduc
`tor substrate, a gate oxide film 103 (for the MOS transistor) is
`grown by a known thermal oxidation technique. Then, a gate
`electrode 104 of polysilicon and a silicon nitride film 105 are
`(sequentially) deposited on the Surface of the gate oxide film
`103. After that, the gate is processed by a lithographic process
`and a dry etching process, and then impurities are implanted
`using the gate electrode and a resist as masks to form diffu
`sion layers 106. It should be noted that although according to
`the present embodiment the gate electrode is made of poly
`silicon, it may be a polymetal gate (low resistance gate)
`having a laminated structure (metal/bar