USOO8120960B2
`
`(12) United States Patent
`Varkony
`
`(10) Patent No.:
`(45) Date of Patent:
`
`US 8,120,960 B2
`Feb. 21, 2012
`
`(54) METHOD AND APPARATUS FOR ACCESSING
`A NON-VOLATILE MEMORY ARRAY
`COMPRISING UNIDIRECTIONAL CURRENT
`FLOWING MULTIPLEXERS
`(75) Inventor: Roni Varkony, Kfar Yona (IL)
`(73) Assignee: Spansion Israel Ltd., Netanya (IL)
`c
`(*) Notice:
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 576 days.
`(21) Appl. No.: 12/289.947
`(22) Filed:
`Nov. 7, 2008
`(65)
`Prior Publication Data
`US 2009/O116288A1
`May 7, 2009
`
`Related U.S. Application Data
`(60) Provisional application No. 60/985,993, filed on Nov.
`7, 2007, provisional application No. 60/985,994, filed
`on Nov. 7, 2007.
`(51) Int. Cl.
`(2006.01)
`GIC I6/04
`(52) U.S. Cl. ......... 365/185.16; 365/185.23:365/230.02;
`365/230.06
`(58) Field of Classification Search ............. 365/185.01,
`365/185.13, 185.16, 185.17, 185.23, 230.02,
`365/230.06, 185.16 O, 185.23 X, 230.02 X,
`365/230.06 X
`See application file for complete search history.
`
`(56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`5,650,959 A
`7/1997 Hayashi
`6,130,452. A 10/2000 Lu
`6,175,519 B1
`1/2001 Lu
`6,532,173 B2 * 3/2003 Iioka et al. ............... 365,185.16
`6,744,667 B2 * 6/2004 Yamamoto et al. ...... 365,185.16
`6,768, 165 B1
`7/2004. Eitan
`6,967,896 B2 11/2005 Eisen
`6,975,536 B2 12/2005 Maayan
`6,992,932 B2
`1/2006 Cohen
`
`OTHER PUBLICATIONS
`"A Mathematical Theory of Communication” The Bell System Tech
`nical Journal, vol. 27, pp. 379-423, 623-656, Jul., Oct. 1948.
`* cited by examiner
`Primary Examiner — VanThu Nguyen
`74). Att
`Agent, or Fi
`Eitan Mehulal Law G
`(74) Attorney, Agent, or Firm — Eitan Mehulal Law Group
`(57)
`ABSTRACT
`A non-volatile memory (NVM) having an array of memory
`cells and a unidirectional multiplexer (UMUX), the UMUX
`may be comprised of two or more address line ports adapted
`to receive addressing signals corresponding with elements in
`the memory array, and a set of Switching transistors adapted
`to switch a supply voltage in accordance with the addressing
`signal Such that current only flows into the array.
`5 Claims, 18 Drawing Sheets
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`Micron Ex. 1015, p. 1
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`IPR2021-01547
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`U.S. Patent
`
`Feb. 21, 2012
`
`Sheet 1 of 18
`
`US 8,120,960 B2
`
`n-CHANNEL
`MOSFET
`
`FIG.1
`PRIOR ART
`
`FLOATING GATE
`MEMORY CELL
`--
`-o-
`l
`
`SOURCE
`
`-200
`INTERPOLY OXDE
`control GATEGATE
`funnel. OXDE
`(FLOATING GATE)
`FLOATING GATE
`
`SUBSTRATE
`FIG2
`PRIOR ART
`
`NROM
`MEMORY CELL
`
`
`
`
`
`-300
`
`328 (GATE)
`326 (OXIDE)
`324 (NITRIDE)
`OXIDE)
`
`PROGRAM RIGHT BIT
`READ RIGHT BIT
`
`PROGRAM LEFT BIT
`READ LEFT BIT
`FIG 3
`PROR ART
`
`Micron Ex. 1015, p. 2
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`U.S. Patent
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`Feb. 21, 2012
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`Sheet 2 of 18
`
`US 8,120,960 B2
`
`
`
`FIG 4A
`PROR ART
`
`DATA
`STREAM
`
`CACHE
`MEMORY
`
`NVM
`ARRAY
`
`FIG4B
`PRIOR ART
`
`Micron Ex. 1015, p. 3
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`U.S. Patent
`U.S. Patent
`
`Feb. 21, 2012
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`Sheet 3 of 18
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`US 8,120,960 B2
`US 8,120,960 B2
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`Micron Ex. 1015, p. 4
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`Sheet 4 of 18
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`US 8,120,960 B2
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`Micron Ex. 1015, p. 5
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`Micron Ex. 1015, p. 5
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`U.S. Patent
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`Feb. 21, 2012
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`Sheet 5 of 18
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`US 8,120,960 B2
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`PRIOR ART
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`Micron Ex. 1015, p. 6
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`U.S. Patent
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`Feb. 21, 2012
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`Sheet 6 of 18
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`US 8,120,960 B2
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`Micron Ex. 1015, p. 7
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`U.S. Patent
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`Feb. 21, 2012
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`Sheet 7 of 18
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`US 8,120,960 B2
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`Micron Ex. 1015, p. 8
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`IPR2021-01547
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`U.S. Patent
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`Feb. 21, 2012
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`Sheet 8 of 18
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`US 8,120,960 B2
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`VSOURCE (Vsr)
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`
`Micron Ex. 1015, p. 9
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`U.S. Patent
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`Feb. 21, 2012
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`Sheet 9 of 18
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`US 8,120,960 B2
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`Micron Ex. 1015, p. 10
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`Micron Ex. 1015, p. 10
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`U.S. Patent
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`Feb. 21, 2012
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`Sheet 10 of 18
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`US 8,120,960 B2
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`Micron Ex. 1015, p. 11
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`IPR2021-01547
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`U.S. Patent
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`Feb. 21, 2012
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`Sheet 11 of 18
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`US 8,120,960 B2
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`/ 900
`
`
`
`VSOURCE (Vsr)
`
`975
`
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`
`FIG 9C
`
`Micron Ex. 1015, p. 12
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`U.S. Patent
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`Feb. 21, 2012
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`Sheet 12 of 18
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`US 8,120,960 B2
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`
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`Micron Ex. 1015, p. 13
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`U.S. Patent
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`Feb. 21, 2012
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`Sheet 13 of 18
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`US 8,120,960 B2
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`
`
`
`
`
`
`A SpA
`
`Micron Ex. 1015, p. 14
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`U.S. Patent
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`Feb. 21, 2012
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`Sheet 14 of 18
`
`US 8,120,960 B2
`
`
`
`
`
`FIGURES 8A-C
`
`IDEAL CURRENT
`SOURCE AS
`MEMORY DEVICE
`% OF b LENGTH DRAN UMUX ON
`(MEMORY DEVICE BOT, SOURCEUMUX SAS Y-MUX
`POSITION)
`ON TOP Was V
`BOT VSOURCE IV)
`
`FIGURE 7
`
`
`
`20%
`
`3805
`
`IDEAL CURRENT
`SOURCE AS
`MEMORY DEVICE
`% OF b LENGTH
`(MEMORY DEVICE
`POSITION)
`
`FIGURES 9A - C
`
`DRAN UMUX ON
`
`ON TOP AND BOT
`Vds V
`
`FIG.10C(i)
`
`Micron Ex. 1015, p. 15
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`U.S. Patent
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`Feb. 21, 2012
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`Sheet 15 of 18
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`US 8,120,960 B2
`
`
`
`*
`
`
`
`
`
`
`
`
`
`
`
`
`
`FIGURE 7
`
`
`
`Sloursec lecure,
`6.3Voir"
`3.98 1858549
`3.97 2749,687
`3.985815659
`3.954456664
`3.945272902
`3.936064576
`3.92683 1892
`3.9 17575058
`3.908294.795
`
`FIGURES 8A-C
`DEVICE
`% OF b LENGTH DRAN UMUX ON
`POSITION)
`|ON TOP Vas (V)
`20%.
`3.954.228524
`30%
`3.9543045
`40%
`3.954580628
`50%
`3.954456908
`60%
`3.954535336
`70%
`3.95460991
`80%
`3.954686629
`90%
`3.954783491
`100%
`3.95484.0502.
`
`
`
`DEVICE
`% OF b LENGTH
`(MEMORY DEVICE
`POSITION)
`
`FIGURE 7
`
`FIGURES 9A-C
`DRAIN UMUX ON
`BOT, SOURCE UMUX STANDARD Y-MUX
`UMUX ON TOP AND ON BOT VSOURCE IV
`BOT VSOURCE IV)
`
`4. O754 18866m
`7.252O566255m
`9.524.5 O996 16n
`1 O888,3759 O5n
`1134213586m
`1 O.885 155289m
`9.5 1868758 13m
`7.245651 O725m
`4O7O653O277m
`
`4.0%
`
`60%,
`
`
`
`
`
`4,528949,573.4m
`9. O7 O725O255m
`13.625 155891 m.
`18, 1921 69,552m
`22,771666535m
`27.565547246 m
`31.9677O99 66m
`36.58.4051846m
`412 124687 O5m
`45.8526 OOO46m
`
`FIG 10C(ii)
`
`Micron Ex. 1015, p. 16
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`U.S. Patent
`
`Feb. 21, 2012
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`Sheet 16 of 18
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`US 8,120,960 B2
`
`1 1 O1
`ADRESS WL IN MEMORY
`THROUGH X-MUX
`
`
`
`ADRESS LSBL IN
`MEMORY ARRAY
`IN FIRST UMUX
`
`1 O 3.
`ADRESS LDBL IN MEMORY
`ARRAY IN SECOND UMUX
`
`1 104
`APPLY SOURCE VOLTAGE
`THROUGH FRST UMUX
`
`1 1 O5
`SENSE CELL CURRENT
`THROUGH SECOND UMUX
`
`FIG 11
`
`Micron Ex. 1015, p. 17
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`U.S. Patent
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`Feb. 21, 2012
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`Sheet 17 of 18
`
`US 8,120,960 B2
`
`12O1
`ADRESS WL IN MEMORY
`THROUGH X-MUX
`
`12O2
`
`
`
`ADRESS LSBL IN
`MEMORY ARRAY IN
`UMUX AND IN Y-MUX
`
`12O3
`ADRESS LDBL IN MEMORY
`ARRAY IN Y-MUX
`
`12O4
`APPLY SOURCE VOLTAGE
`THROUGH UMUX AND Y-MUX
`
`12O5
`SENSE CELL CURRENT
`THROUGH Y-MUX
`
`FIG 12
`
`Micron Ex. 1015, p. 18
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`U.S. Patent
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`Feb. 21, 2012
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`Sheet 18 of 18
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`US 8,120,960 B2
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`
`
`
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`Micron Ex. 1015, p. 19
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`US 8,120,960 B2
`
`1.
`METHOD AND APPARATUS FOR ACCESSING
`A NON-VOLATILE MEMORY ARRAY
`COMPRISING UNIDIRECTIONAL CURRENT
`FLOWING MULTIPLEXERS
`
`CROSS-REFERENCE(S) TO RELATED
`APPLICATION(S)
`This application claims the benefit of U.S. Provisional
`Application No. 60/985,993, filed 7 Nov. 2007; and 60/985,
`994, filed 7 Nov. 2007; the disclosures of which are incorpo
`rated herein by reference in their entirety.
`
`FIELD OF THE INVENTION
`
`The present invention relates generally to the field of semi
`conductors. More specifically, the present invention relates to
`non-volatile memory (NVM) devices.
`
`10
`
`15
`
`BACKGROUND
`
`2
`An integrated circuit (IC) device may comprise many mil
`lions of FETs on a single semiconductor “chip” (or “die”),
`measuring only a few centimeters on each side. Several IC
`chips may be formed simultaneously, on a single "wafer.
`using conventional semiconductor fabrication processes
`including deposition, doping, photolithography, and etching.
`After all the chips are formed, they can be singulated from the
`wafer.
`The Floating Gate Transistor
`A floating gate transistor is generally a transistor structure,
`broadly based on the FET, as described hereinabove. As sche
`matically illustrated in FIG. 2, floating gate transistor 200 has
`a source and a drain, but rather than having only one gate, it
`has two gates which are called control gate (CG) and floating
`gate (FG). It is this arrangement of control gate and floating
`gate which enables the floating gate transistor to function as a
`memory cell, as described herein below.
`The floating gate is disposed over tunnel oxide (compa
`rable to the gate oxide of the FET). The floating gate is a
`conductor; the tunnel oxide is an insulator (dielectric mate
`rial). Another layer of oxide (interpoly oxide, also a dielectric
`material) separates the floating gate from the control gate.
`Since the floating gate is a conductor, and is Surrounded by
`dielectric material, it can store a charge. Electrons can move
`around freely within the conductive material of the floating
`gate (which comports with the basic definition of a “conduc
`tor). Since the floating gate can store a charge, it can exert a
`field effect on the channel region between the source and the
`drain, in a manner similar to how a normal FET works, as
`described hereinabove. Mechanisms for storing charges on
`the floating gate structure, as well as removing charges from
`the floating gate, are described herein below.
`Generally, if a charge is stored on the floating gate, this
`represents a binary “1”. If no charge is stored on the floating
`gate, this represents a binary '0'. (These designations are
`arbitrary, and can be reversed so that the charged State repre
`sents binary “0” and the discharged state represents binary
`“1”.) That represents the programming “half of how a float
`ing gate memory cell operates. The other half is how to
`determine whether there is a charge stored on the floating
`gate in other words, to “read the memory cell. Generally,
`this is done by applying appropriate Voltages to the source,
`drain and gate terminals, and determining how conductive the
`channel is. Some modes of operation for a floating gate
`memory cell are described herein below.
`Normally, a floating gate non-volatile memory (NVM) cell
`has only a single "charge-storing area' namely, the conduc
`tive floating gate (FG) structure, and can therefore only store
`a single bit of information (binary “1” or binary 'O'). More
`recently, using a technology referred to as “multi-level cell
`(MLC), two or more bits can be stored in and read from the
`floating gate cell.
`The NROM Memory Cell
`Another type of memory cell, called a "nitride, read only
`memory” (NROM) cell, has a charge-storage structure which
`is different from that of the floating gate memory cell and
`which permits charges to be stored (or trapped) in two sepa
`rate charge-storage areas. Generally, the two separate charge
`storage areas are located within a non-conductive layer dis
`posed between the gate and the underlying Substrate, such as
`a layer of nitride formed in an oxide-nitride-oxide (ONO)
`stack underneath the gate. The non-conductive layer acts as a
`charge-trapping medium. Generally, electrical charges will
`stay where they are put in the charge-trapping medium, rather
`than being free to move around, as in the example of the
`conductive floating gate of the floating gate memory cell. A
`first bit of binary information (binary “1” or binary “O”) can
`be stored in a first portion (such as the left-hand side) of the
`charge-trapping medium, and a second bit of binary informa
`tion (binary “1” or binary “O”) can be stored in a second
`
`25
`
`The Field Effect Transistor
`The transistor is a solid state semiconductor device which
`can be used for amplification, Switching, Voltage stabiliza
`tion, signal modulation and many other functions. Generally,
`a transistor has three terminals, and a Voltage applied to a
`specific one of the terminals controls current flowing between
`the other two terminals. One type of transistor is known as the
`field effect transistor (FET).
`The terminals of a field effect transistor (FET) are com
`monly named source (S), gate (G) and drain (D). In the FET
`30
`a small amount of voltage is applied to the gate (G) in order to
`control current flowing between the source (S) and the drain
`(D). In FETs the main current appears in a narrow conducting
`channel formed near (usually primarily under) the gate. This
`channel connects electrons from the Source terminal to the
`drain terminal. The channel conductivity can be altered by
`varying the Voltage applied to the gate terminal, enlarging or
`constricting the channel and thereby controlling the current
`flowing between the source and the drain.
`FIG. 1 schematically illustrates a FET 100 comprising a
`p-type Substrate (or a p-well in the Substrate), and two spaced
`apart n-type diffusion areas—one of which will serve as the
`“source', the other of which will serve as the "drain' of the
`transistor. The space between the two diffusion areas is the
`“channel. A thin dielectric layer is disposed over the sub
`strate in the neighborhood of the channel, and a "gate' struc
`ture is disposed over the dielectric layer atop the channel.
`(The dielectric under the gate is also commonly referred to as
`“gate oxide' or “gate dielectric'.) Electrical connections (not
`shown) may be made to the source, the drain, and the gate.
`The Substrate may be grounded, or it may be biased at a
`desired Voltage, depending on applications.
`Generally, when there is no Voltage on the gate, there is no
`electrical conduction (connection) between the Source and
`the drain. AS Voltage (of the correct polarity) is applied to the
`gate, there is a “field effect” in the channel between the source
`and the drain, and current can flow between the source and the
`drain, and can be controlled by the Voltage applied to the gate.
`In this manner, a Small signal (gate Voltage) can control a
`relatively large signal (current flow between the Source and
`the drain).
`FET 100 is exemplary of a MOSFET (metal oxide semi
`conductor FET) transistor. With the specified “n” and “p”
`types shown above, an “in-channel MOSFET can be formed.
`With opposite polarities (swapping “p' for “n” in the diffu
`sions, and “n” for “p' in the substrate or well), a p-channel
`FET can be formed. In CMOS (complementary metal oxide
`semiconductor), both n-channel and p-channel MOS transis
`tors may be used, and are often paired with one another.
`
`35
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`40
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`45
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`50
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`55
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`60
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`65
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`Micron Ex. 1015, p. 20
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`3
`portion (such as the right-hand side) of the charge-trapping
`medium. An alternative viewpoint is that different charge
`concentrations can be considered for each bit of storage.
`Using MLC technology, at least two bits can be stored in and
`read from each of the two portions (charge storage areas) of
`the charge-trapping medium (for a total of 4 bits), similarly 3
`bits or more than 4 bits may be identified.
`FIG. 3 schematically illustrates a basic NROM memory
`cell, which may be viewed as an FET with an “ONO” struc
`ture inserted between the gate and the substrate. (One might
`say that the ONO structure is “substituted for the gate oxide
`of the FET). The ONO structure is a stack (or “sandwich') of
`bottom (lower) oxide 322, a charge-trapping material such as
`nitride 324, and a top (upper) oxide 326. The ONO structure
`may have an overall thickness of approximately 10-25 nm,
`Such as 18 nm, as follows:
`the bottom oxide layer 322 may be from 3 to 6 nm, for
`example 4 nm thick;
`the middle nitride layer 324 may be from 3 to 8 nm, for
`example 4 nm thick; and
`the top oxide layer 326 may be from 5 to 15 nm, for
`example 10 nm thick.
`The NROM memory cell has two spaced apart diffusions 314
`and 316 (which can function as source and drain, as discussed
`herein below), and a channel region 320 defined in the sub
`strate 312 between the two diffusion regions 314 and 316, and
`a gate 328 disposed above the ONO stack 321.
`In FIG.3, the diffusions are labeled "N+'. This means that
`they are regions in the substrate that have been doped with an
`electron donor material. Such as phosphorous or arsenic.
`These diffusions are typically created in a larger region which
`is a p-type cell well (CW) doped with boron (or indium or
`both). This is the normal “polarity” for an NVM cell employ
`ing electron injection (but which may also employ hole injec
`tion, such as for erase). With opposite polarity (boron or
`indium implants in an n-type cell well), the primary injection
`mechanism would be for holes, which is generally accepted to
`be not as effective as electron injection. One skilled in the art
`will recognize that the concepts disclosed herein can be
`applied to opposite polarity devices.
`The charge-trapping material 324 is non-conductive, and
`therefore, although electrical charges can be stored in the
`charge-trapping material, they are not free to move around;
`they will generally stay where they are stored. Nitride is a
`Suitable charge-trapping material. Charge trapping materials
`other than nitride may also be suitable for use as the charge
`trapping medium. One Such material is silicon dioxide with
`buried polysilicon islands. A layer324 of silicon dioxide with
`polysilicon islands would be sandwiched between the two
`layers of oxide 322 and 326. Alternatively, the charge-trap
`ping layer324 may be constructed by implanting an impurity,
`Such as arsenic, into a layer of silicon dioxide deposited on
`top of the bottom oxide 322.
`Memory cell 300 is generally capable of storing at least two
`bits of data—at least one bit(s) in a first storage area of nitride
`layer 324 represented by the dashed circle 323, and at least
`one bit(s) in a second storage area of the nitride layer 324
`represented by the dashed circle 321. Thus, the NROM
`memory cell can be considered to comprise two “half cells'.
`each half cell capable of storing at least one bit(s). It should be
`understood that a half cell is not a physically separate struc
`ture from another half cell in the same memory cell. The term
`“half cell’, as it may be used herein, is used herein only to
`refer to the “left” or “right” bit storage area of the ONO stack
`(nitride layer). The storage areas 321, 323 may variously be
`referred to as “charge storage areas”, “charge trapping areas.
`and the like, throughout this document. (The two charge
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`storage areas may also be referred to as the right and left
`“bits.) Each of the storage areas 321, 323 in the charge
`trapping material 324 can exert a field effect on the channel
`region 320 between the source and the drain, in a manner
`similar to how a normal FET works, as described hereinabove
`(FIG. 2).
`Generally, ifa charge is stored in a given storage area of the
`charge-trapping material, this represents a binary '1', and if
`no charge is stored in a given storage area of the charge
`trapping material, this represents a binary “0”. (Again, these
`designations are arbitrary, and can be reversed so that the
`charged state represents binary “0” and the discharged state
`represents binary '1'.) That represents the programming
`“half of how an NROM memory celloperates. The other half
`is how to determine whether there is a charge stored in a given
`storage area of the charge-trapping material—in other words,
`to “read the memory cell. Generally, this is done by applying
`appropriate Voltages to the diffusion regions (functioning as
`Source and drain) and gate terminals, and determining how
`conductive the channel is.
`Modes of Operation
`Generally, the modes of operation for any NVM memory
`cell (either floating gate, SONOS, TANOS, NROM or other)
`include “program”, “erase' and “read. Modes of operation
`for NROM are now discussed.
`Program generally involves injecting electrons into the
`charge storage areas of the NROM cell, typically by a process
`known as channel hot electron (CHE) injection.
`Exemplary Voltages to program (by CHE injection of elec
`trons) the right bit (right bit storage area) of an NROM cell,
`The left BL (acting as source, Vs) is set to 0 volts
`the right BL (acting as drain, Vd) is set to +5 Volts
`the gate (Vg) is set to +8-10 volts
`the substrate (Vb) is set to 0 volts
`and the bit storage area above the drain (right BL) becomes
`programmed. To program the left bit storage area, Source and
`drain are reversed the left bitline serves as the drain, and the
`right bitline serves as the source.
`Erase may involve injecting holes into the charge storage
`areas of the NROM cell, typically by a process known as hot
`hole injection (HHI). Generally, holes cancel out electrons
`(they are electrically opposite), on a one-to-one basis. Exem
`plary voltages to erase (by HHI injection of holes) the right bit
`of the NROM cell,
`the left BL (acting as source, Vs) is set to float
`the right BL (acting as drain, Vd) is set to +5 Volts
`the gate (Vg) is set to -7 volts
`the substrate (Vb) is set to 0 volts
`and the bit storage area above the drain (right BL) becomes
`erased. To erase the left bit storage area, Source and drain are
`reversed the left bitline serves as the drain and the right
`bitline serves as the source.
`Read may involve applying Voltages to the terminals of the
`memory cell and, based on Subsequent current flow, ascer
`taining the threshold Voltage of the charge storage area within
`the cell. Generally, to read the right bit of the NROM cell,
`using “reverse read”,
`the right BL (acting as source, Vs) is set to 0 volts
`the left BL (acting as drain, Vd) is set to +2 volts
`the gate (Vg) is set to +5 Volts
`the substrate (Vb) is set to 0 volts
`and the bit storage area above the source (right BL) can be
`read. To read the left bit storage area, Source and drain are
`reversed the left bitline serves as the source, and the right
`bitline serves as the drain.
`
`Micron Ex. 1015, p. 21
`Micron v. Vervain
`IPR2021-01547
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`“Reading an NROM Cell, Generally
`Reading an NROM memory cell may involve applying
`Voltages to the terminals of the memory cell comparable to
`those used to read a floating gate memory cell, but reading
`may be performed in a direction opposite to that of program
`ming. Generally, rather than performing 'symmetrical pro
`gramming and reading (as is the case with the floating gate
`memory cell, described hereinabove), the NROM memory
`cell is usually programmed and read “asymmetrically.
`meaning that programming and reading occur in opposite
`directions. This is illustrated by the arrows in FIG. 3. Pro
`gramming is performed in what is termed the forward direc
`tion, and reading is performed in what is termed the opposite
`or reverse direction. For example, to program the right storage
`area 323 (in other words, to program the right “bit”), electrons
`generally flow from left (source) to right (drain). To read the
`right storage area 323 (in other words, to read the right “bit”),
`Voltages are applied to cause electrons to flow from right to
`left, in the opposite or reverse direction. For example, gener
`ally, to program the left storage area 321 (in other words, to
`program the left “bit”), electrons flow from right (source) to
`left (drain). To read the left storage area 321 (in other words,
`to read the left “bit”), Voltages are applied to cause electrons
`to flow from left to right, in the opposite or reverse direction.
`See, for example, U.S. Pat. No. 6,768,165.
`Memory Array Architecture, Generally
`Memory arrays are well known, and comprise a plurality
`(many, including many millions) of memory cells organized
`(including physically arranged) in rows (usually represented
`in drawings as going across the page, horizontally, from left
`to-right) and columns (usually represented in drawings as
`going up and down the page, from top-to-bottom). As dis
`cussed hereinabove, each memory cell comprises a first dif
`fusion (functioning as Source or drain), a second diffusion
`(functioning as drain or source) and a gate, each of which has
`to receive voltage in order for the cell to be operated, as
`discussed hereinabove. Generally, the first diffusions (usually
`designated “source') of a plurality of memory cells are con
`nected to a first bit line which may be designated “BL(n)', and
`second diffusions (usually designated “drain”) of the plural
`ity of memory cells are connected to a second bit line which
`may be designated “BL(n+1). Typically, the gates of a plu
`rality of memory cells are connected to common word lines
`(WL).
`The bitlines may be “buried bitline' diffusions in the sub
`strate, and may serve as the source/drain diffusions for the
`memory cells. The wordlines may be polysilicon structures
`and may serve as the gate elements for the memory cells.
`FIG. 4A schematically illustrates an array of NROM
`memory cells (labeled “a” through 'i') connected to a num
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`ber of word lines (WL) and bit lines (BL). For example, the
`memory cell 'e' has its gate connected to WL (n), its source
`(left hand diffusion) is connected to BL (n), and its drain
`(right hand diffusion) is connected to BL (n+1). The nine
`memory cells illustrated in FIG. 4A are exemplary of many
`millions of memory cells that may be resident on a single
`chip.
`Notice, for example, that the gates of the memory cells “e'
`and “f (to the right of “e') are both connected to the same
`word line WL (n). (The gate of the memory cell "d to the left
`of 'e' is also connected to the same word line WL (n).) Notice
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`also that the right hand terminal (diffusion) of memory cell
`“e' is connected to the same bit line BL (n+1) as the left-hand
`terminal (diffusion) of the neighboring memory cell “f. In
`this example, the memory cells 'e' and “f” have two of their
`three terminals connected together.
`The situation of neighboring memory cells sharing the
`same connection—the gates of neighboring memory cells
`being connected to the same word line, the Source (for
`example, right hand diffusion) of one cell being connected to
`the drain (for example left hand diffusion) of the neighboring
`cell is even more dramatically evident in what is called
`“virtual ground architecture' wherein two neighboring cells
`actually share the same diffusion. In virtual ground array
`architectures, the drain of one memory cell may actually be
`the same diffusion which is acting as the Source for its neigh
`boring cell. Examples of virtual ground array architecture
`may be found in U.S. Pat. Nos. 5,650,959; 6,130,452; and
`6,175,519, incorporated in their entirety by reference herein.
`Operating Flash Memory
`Flash is a non-volatile memory that can retain the data
`stored therein even after power is removed. NAND Flash,
`which is one type of Flash, is high-density design and has
`certain advantages over other types of memory, including a
`large storage capacity (such as one giga-bits or more), good
`speed for continued access, and low cost. However, NAND
`Flash also has several inherent drawbacks, including poor
`performance for random access and increased Susceptibility
`to bit errors over the NAND Flash's operating lifetime. In
`particular, NAND Flash is typically accessed in units of
`pages, one page at a time, with each page being of a particular
`size (for example, 512 bytes).
`Because the structure of NAND Flash is not suitable for
`random access, program codes cannot be executed directly
`from the NAND Flash. Instead, Static Random Access
`Memory (SRAM) or NOR Flash may be used as an interme
`diate storage for data and program codes that need to be
`accessed in a random manner by the processor. A memory
`architecture that incorporates both SRAM and NAND Flash
`or NOR and NAND Flash (with or without SRAM) may thus
`provide large storage capacity, reduced cost, and random
`aCCCSS,
`Conventionally, reading data from or writing data into
`NAND Flash requires excessive involvement and control by
`the processor. This can tie up the processor and prevent it from
`performing other functions, which can then result in overall
`performance degradation for the communication device.
`Moreover, since NAND Flash is more prone to bit errors, a
`mechanism is needed to ensure data integrity when loading
`data from or into the NAND Flash. As described in U.S. Pat.
`No. 6,967,896, a user wishing to write data to an NVMarray
`may typically write the data to a cache memory, Such as but
`not limited to, a static random access memory (SRAM). The
`cache memory routes or "addresses the data to the appropri
`ate bits in the NVM array. The data may be written to the
`SRAM in a byte granularity.
`In a manner similar to NVM, SRAM may also be arranged
`in an array—for example, an NXn array of 1-bit cells, where:
`n-byte width (such as 8, 16, 32 . . . )
`N=number of bytes
`Generally, m address bits may be divided into X row bits and
`y column bits (x+y=m). Address bits may be encoded such
`that 2"=N and the array may be organized with both vertical
`and horizontal stacks of bytes.
`An example of a typical SRAM addressing scheme is shown
`in the following table.
`
`Micron Ex. 1015, p. 22
`Micron v. Vervain
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`which of two program levels the single cell was programmed,
`since its threshold Voltage may have moved slightly upward
`or slightly downward since it was programmed. This is a
`benefit of reading bits one block at a time—to obtain a sta
`tistically meaningful sample of Vt’s across a number of cells.
`FIG. 5A is a graph schematically illustrating two states of
`a “binary” or single level cell (SLC) capable of storing one bit
`of information per cell (or per charge trapping area with an
`NROM cell), and utilizes only one read verify threshold (RV).
`Generally, the two states are erased (represented by “1”) and
`programmed (represented by 'O'). The horizontal axis is
`threshold voltage (Vt), increasing from left to right. Three
`voltage levels are illustrated in FIG. 5A, these are EV (erase
`verify), RV (read verify) and PV (program verify). As illus
`trated, EV is less than RV, which is less than PV. A high Vt
`may representa program state of binary “0”, and a lowVt may
`represent an erase state of binary “1”. The binary designations
`are arbitrary, and may be reversed (high Vt=“1”, low Vt=“0”).
`FIG. 5A is generalized, and is applicable to a typical float
`ing gate NVM memory cell or a given charge storage area of
`an NROM cell. The curves represent the threshold voltages
`(Vts) for a number of cells at the given program level. Typi
`cally, there is a distribution, or spread, about a nominal (or
`average, or center) value. For example,
`the center value for “1” equals approximately 3.5 volts
`the center value for “O'” equals approximately 6.0 volts
`EV equals approximately 4.0 volts
`RV equals approximately 4.5 volts
`PV equals approximately 5.5 volts
`FIG. 5B schematically illustrates a situation wherein there
`are four possible MLC program levels (or states) 11, 01, 00,
`10 for each memory cell (or, in the case of NROM, for each
`storage area of the memory cell). As illustrated, the program
`level 11 has the lowest Vt, the program level 01 has a higher
`Vt, the program level 00 has a yet higher Vt, and the program
`