@)WILEY
`
`SEMICONDUCTOR
`MEMORIES
`
`A Handbook of Design,
`Manufacture, and Application
`SECOND EDITION
`
`Betty Prince
`
`Micron Ex. 1014, p. 1
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`WBC11~1~1~J~H~r
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`Semiconductor
`Memories
`A Handbook of Design,
`Manufacture a~d Application
`Second Edition
`
`Betty Prince
`Texas Instruments, USA
`
`JOHN WILEY & SONS
`Chichester
`• New York
`• Brisbane
`
`• Toronto
`
`• Singapore
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`Second edition of the book Stmiconduclor Mtmorits by B. Prince and G. Due-Gundersen
`
`Copyright© 1983, 1991 by John Wiley & Sons Ltd.
`Baffins Lane, Chichester
`West Sussex POJ9 IUD, England
`
`Reprinted with corrections February 1995
`Reprinted January 1996
`Reprinted June 1996
`Reprinted June 19'J7
`
`All rights reserved.
`
`No part of this book may be reproduced by an}• means,
`or transmitted, or translated into a machine language
`without the written permission of the publisher.
`
`Other Wiley Editorial Offices
`John Wiley & Sons, Inc., 605 Third A venue.
`New York, NY 10158-0012, USA
`
`Jacaranda Wiley Ltd. G.P.O. Box 859. Brisbane,
`Queensland 4001, Australia
`
`John Wiley & Sons (Canada) Ltd, 22 Worcester Road.
`Rexdale, Ontario M9W lLI. Canada
`
`John Wiley 8c Sons (SEA) Pte Ltd. 3 7 Jalan Pemimpin * 05·04,
`
`Block B, Union Industrial Building. Singapore 2057
`
`Transferred to digital printing
`British Library C11taloguing-in-Publication Data
`
`A catalogue record for the book is
`available from the British Library
`
`ISBN o 471 92465 2 ; 0 471 94295 2 (pbk)
`
`Typeset by Techset Composition Limited, Salisbury, Wiltshire
`Printed and bound by Antony Rowe Ltd, Chippenham. Wiltshire
`
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`CONTENTS
`
`Introduction
`Acknowledgements
`
`1 The Strategic Nature of Semiconductor Memories
`· 1.1 Twenty years of memories
`1.2 The largest and most volatile integrated circuit market
`1.3 Structural and economic factors affecting volatility
`1.3.1 Structural supply factors
`1.3.2 General economic factors
`Interactions of short term and long tenn factors
`1.3.3
`1.3.4 Stabilizing factors
`1.4 A strategic component in advanced electronic systems
`1.5 A major trade issue
`1.5.1 Supply shifts in memory trade
`1.5.2 Demand shifts in memory trade
`1.6 An essenHal factor in MOS technological development
`1. 7 A key to low cost MOS manufacturing technology
`1.8 The new memory revolution
`Bibliography
`
`2 The Basics of Memories: Market, Technology and
`Product
`2.1 A brief history of the bulk memory storage market
`2.2 A marketing view of memories and the learning curve
`2.3 A marketing view of memory product life cycle theory
`2.4 A technology view of life cycles and learning curves
`2.5 Standardization of memories
`2.6 An overview of various data storage devices
`2.7 Charge coupled devices
`2.8 Bipolar memories
`2.9 MOS memories
`2.9.1 Read-write memories
`2.9.2 Non.volatile memories
`2.10 Alternatives to semiconductor memories
`2.10.1 Magnetic bubbles
`2.10.2 Magnetic disk
`2.10.3 Optical disk
`2.10.4 Holographic storage
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`2.11
`2.12
`2.13
`2.14
`2.15
`2.16
`2.17
`2.18
`
`High density memory packaging
`Test and test strategies
`Reliability concerns
`The super-factory and clustered clean equipment
`Memory applications
`Embedded memories
`Large scale integration of memories
`Where to from here
`Bibliography
`
`Trends in Memory Applications
`3
`Varieties of data storage devices by media
`3.1
`Functional characteristics of various semiconductor memories
`3.2
`3.2.1 MOS memory selection by system requirement
`3.3 Memory usage in computer applications
`3.4 Computer storage hierarchies
`3.4.1 Main memory
`3.4.2 Overview of cache
`3.4.3 Direct mapped cache
`3.4.4 Associative cache
`3.3.S Application-specific cache chips
`3.4.6 Dual-port SRAMs as cache buffers
`3.4.7
`Interleaving memory to gain system speed
`3.3.8 Archive or mass storage
`3.5 Supercomputers and parallel processors
`3.6 Memories for video processing and graphics workstations
`3.7 Example of typical computer memory storage configuration
`3.8 Some other system applications of memories
`3.8.1 Systems lor non-volatile memories
`3.8.2 Computer communications
`3.8.3 Distributed processing and process control
`3.8.4 High and extended definition television
`3.8.5 Teletext
`3.8.6 A programmable compact disk video processing system
`3.8.7 Portable systems
`3.8.8 Large memory smart cards
`3.8.9 Consumer games
`3.8.10 Memories in automotive electronics
`3.8.11 The automated factory and robotic advances
`3.8 .12 Computer integrated manufacturing
`3.8.13
`Industrial applications
`3.9 Basics of reading timing diagrams from a memory datasheet
`3.9.1 Timing diagrams
`3.10 Factors slowing down a memory system
`3.10.1 Bus contention
`3.10.2 Ground.bounce
`3.10.3 System bandwidth
`Bibliography
`
`4 Memory Device and Process Technology
`4.1 Required device characteristics
`4.2 Trends in MOS device characteristics
`
`CONTENTS
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`CONTENTS
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`Increased density
`4.2.1
`4.2.2 High speed
`4.2.3 Power consumption
`4.3 Basic MOS memory process
`4.4 Various MOS field effect transistor gates
`4.3.1 NMOS and PMOS field effect transistors
`4.4.2 MOS transistor characteristics
`4.4.3 CMOS field effect transistors
`4.5 CMOS invertor characteristics
`4.5.I An analytical approach
`4.6 EPROM memory cell: floating gate avalanche injection MOS
`4. 7 EEPROM memory storage transistor
`4.8 Bipolar circuits
`4.9 BICMOS gates
`4.10 Latch-up mechanism
`4.11 MOS scaling
`4.12 Development of MOS process technology
`4.12.l Silicon dioxide as the basis of MOS processing
`4.12.2 Local oxidation of silicon (LOCOS)
`'Bird's beak' effect
`4.12.3
`4.12.4 Trench isolation
`4.13 Photolithograpy
`4.14 Etching techniques
`4.15 Dopant introduction
`4.15.1 Structured doping techniques
`4.15.2 Doping for enhancement and depletion mode transistors
`4.15 .J Lightly doped drains (LOO)
`4.15.4 Double diffused MOSTs (DMOSJ
`4.15.5 Retrograde wells
`Interconnect technology-metallization, polysilicon
`4.16
`4.16.1 Polysilicon interconnects
`4.16.2 Metal interconnects
`4.16.3 Metal and polysilicon combination interconnects
`4.17 Planarization techniques
`4.18 Process considerations for redundancy techniques
`4.19 Contact technology
`4.20 An optimized CMOS submicron SRAM memory process
`4.21 A submicron BiCMOS process
`4.22 Process development for the one-transistor DRAM cell
`4.22.1 Planar DRAM cell theory
`4.22.2 High capacitance Implanted DRAM cell theory
`4.23 New structures for submicron geometry DRAMs
`4.23.1 Trench capacitors
`4.23.2 A basic trench DRAM capacitor process
`4.23.3 Stacked capacitors for DRAMs
`4.24 Silicon on insulator structures
`4.25 New rransistor structures for SRAMs
`4.26 Possibilities for deep submicron cells
`Bibliography
`
`5 Basic Memory Architecture and Cell Structure
`5.1
`Introduction
`5.2 Basic memory architecture
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`CONTENTS
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`5.3 Data storage elements
`5.3.l Static RAM <latched) cell~onfiguration and types
`5.3.2 Dynamic RAM (capacitor storage) cell evoluHon
`5.4 Static RAM architecture
`5.4.1 Basic architectural overview
`5.4.2 Basic SRAM cell operation
`5.4.3 Basic peripheral circuit operation of the SRAM
`5.4.4 Read and write circuitry
`5.4.5 Data path circuitry
`5.4.6
`Input circuitry for SRAMs
`5.4.7 Read and write circuitry
`5.4.8 Sense amplifier for SRAMs
`5.4.9 Output circuitry for SRAMs
`5.5 Synchronous (clocked) and asynchronous (non-clocked) SRAMs
`5.6 Terminology for RAMs
`5.7 Serially accessed memory (SAM) architecture and cells
`5.7.1 SAM architecture
`5.7.2 SAM cells
`5.8 DRAM specific architectures
`5.8.1 One-transistor cell operation
`5.8.2 Basic architecture
`5.8.3 Storage to bit-line capacitance ratios and signal levels
`5.8.4 Bil-line architectures
`5.8.5 Basic dynamic sense amplifier concept
`5.8.6 Dynamic sense amplifiers with dummy cell structures
`5.8.7 Timing and sequencing
`5.8.8 Advanced DRAM architectures
`5.9 Overview of non-volatile MOS memories
`5.10 Mask ROM architecture and cells (single transistor)
`5.11 UY-EPROM cell technology and architecture
`5.11.1 UV-EPROM cell technology
`5.11.2 UV-EPROM cell reliability
`5.11.3 UV-EPROM architecture
`5.12 One-time-programmable EPROM (OTP)
`5.13 Electrically erasable PROM technology and architecture
`5.13.1 Overview
`5.1.3.2 Fowlei--Nordheirn tunneling
`5.13.3 EEPROMs and EAROMs
`5.13.4 EEPROM reliability
`5.13.5 Flash mem<>ries
`5.14 On-chip voltage generation
`5.15 Bipolar memory basic gates and characteristics
`5.15.1 Basic bipolar flipflop
`5.15.2 ECL memory cell
`Integrated injection logic memory cells (11L)
`5.15.3
`5.15.4 Collector coupled static RAM cell (CCL)
`5.15.5 Multiple emitter cell
`5.15.6 Bipolar SCR dynamic cell structure
`5.15.7 Combination MOS and bipolar cells
`5.16 BiCMOS architectures and considerations
`5.17 1/0 interface characteristics and circuits
`5.17.1
`Interface characlerislics (l/0) of memory circuits
`5.17.2 Transfer characteristics and CMOS invertors
`5.17.3 Transfer characteristics of ECL gates
`5.18
`Input and output levels
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`CONTENTS
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`5.18.1 Commonly used input and output voltage levels
`5.18.2 Noise margin
`5 .18.3 Voltage level interfaces and level shifters
`5.19 Self and mutual inductance effects on output timing
`5.20 Multiplexing of input signals to the memory
`5.20.1 Address multiplexing in DRAMS
`5.20.2 Common as opposed lo separate 1/0
`5.20.3 Other types of multiplexing
`5.21 Redundant circuits for enhanced yield
`5.22 Error correction o n the memory chip
`5.23 Computer automated design and simulation
`Bibliography
`
`6 Dynamic Random Access Memory Trends-4k to 256Mb
`6.1 An overview o f dynamic RAMs
`· 6.2 Early dynamic RAM developments
`6.3 The first modern DRAM-the one-transistor cell 4k
`6.3.1 An example of an early 4k DRAM
`6.3.2 Address multiplexing and the 16 pin package
`6.4 The 16k DRAM-beginning of the era of technology innovation
`6.4.l Array efficiency
`6.4.2 RAS and CAS clock access
`6.4.3 The double poly one-transistor cell structure
`6.4.4 16k DRAM sense amplifier
`6.4.5 16k bit-line architecture and refresh cycles
`6.4.6 RAS only refresh
`lTL compatible MOS level shirters
`6.4.7
`6.5 The 64k DRAM
`6.5.1 Architecture and refresh on the 64k
`6.5.2 64k DRAM sense amplifiers and bit-line structures
`6.5.3 S V only power supplies appear
`6.5.4 Elimination of external back bias voltage
`6.5.5 64k pinout and package issues
`6.5.6 Noise related problems-alpha radiation
`6.5.7 Other noise considerations in S V only DRAMs
`6.5.8 Grounded word-lines
`6.5.9 Bit-line architectures to reduce noise
`6.5.10 Boosted bit-lines
`6.5.11 Boosted word-lines
`6.5.12
`Implanted capacitor storage cell and grounded cell plate
`6.5.13 Cell plate biased al Vee
`6.5.14 Noise due to voltage bump on a Vee biased cell plate
`6.5.15 New operational modes-nibble mode and CAS before RAS refresh
`6.6 An overview of the 256k DRAMs
`6.6.1 256k DRAM devices
`6.7 History of CMOS DRAMs
`6.7.1 Advantages of CMOS for DRAMs
`6.7.2 Drawbacks of CMOS with DRAMs
`6.8 The lMb D RAMs
`6.8.1 A typical production lMb DRAM
`6.8.2 New timing modes
`6.8.3
`Improved sense amplifiers for the lMb DRAMs
`6.8.4 Half Vee bit-line sensing schemes on DRAMS
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`CONTENTS
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`6.8.5 V cell biased cell plate
`6.8.6 Voltage generators for the IMb
`6.8.7 Address transition detection for power reduction
`6.8.8 Test modes for the IMb DRAM
`6.8.9 Reducing the resistance of long poly word-lines
`6.9 The 4Mb DRAM
`6.9.1 Overview
`6.9.2 Vertical cell structures-trench and stacked capacitors
`6.9.3 DRAM cell architectures
`6.9.4 On-chip voltage convertois
`6.9.5 Circuits for noise reduction in 4Mb DRAMS
`6.9.6 Voltage bump at the 4Mb level
`6.9.7 Transistor reliability concerns
`6.9.8 New access and test modes
`6.9.9 A typical 4Mb production DRAM
`6.10 16Mb DRAMs and beyond
`6.10.1 Overview of 16Mb DRAMs
`6.10.2 Vertical capacitors for the 16Mb DRAM
`6.10.3 Refresh related issues with 16Mb DRAMs
`6.10.4 Sense amplifier considerations
`6.10.5 Bit-line architectures for I6Mb DRAMs
`6.10.6 Low voltage power supplies and l/O interfaces
`6.11 64Mb DRAMs
`6.11.1 Cell structures for the 64Mb DRAM and beyond
`6.11.2 Architectural considerations for the 64Mb DRAM
`6.12
`Improved computer design tools for multimegabit DRAMs
`Bibliography
`
`7 Application-specific DRAMs
`7.1 Overview
`7.2 DRAMs for the smalJ system environment
`7.2.1 Non-multiplexed addressing for DRAMs
`7.2.2 Simplifying the external control requirements of the DRAM
`7.2.3 The first 64k DRAMs with simplified refresh control
`7.3 The pseudostatic and virtual static DRAMs (PSRAM-VSRAM)
`7.3.1 Early P/SRAMs
`7.3.2 A comparison of a 256k SRAM with a 256k pseudostatic RAM
`7.3.3 Two !Mb PS-DRAMs
`7.3.4 The !Mb PS-DRAMs compete for market with the 1Mb SRAMs
`7.3.5 The 'virtually' static transparent refresh RAMs
`7.3.6 The virtually pseudostatic DRAM
`7.3.7 4Mb PVSRAMs
`7.3.8 Other transparent refresh SRAMs with DRAM cells
`7.3.9 DRAM macrocells in logic J.C.s
`7.3.10 · Self-refresh DRAMs in battery back-up applications
`7.3.11 Low voltage DRAMs for battery back-up applications
`7.4 DRAMs target the disk market
`7.4.1 DRAMs as silicon files
`7.4.2 Multilevel storage techniques for high density
`7.5 High speed DRAMs
`7.5.1 BiCMOS DRAMs
`7.5.2 Special high speed DRAM modes
`7.6 A brief history of graphics applications for DRAMs
`7.6.1 Early dual-port VDRAMs
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`CONTENTS
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`7.6.2 The 256k VDRAMs establish the market
`7.6.J
`!Mb multiport video DRAMs
`7.6.4 Enhanced video DRAMs
`7.6.5 Triple-port video DRAMs
`7.7 Simplified display memories for consumer applications
`7.7.1 Line buffe.rs
`7.7.2 Field memories
`Bibliography
`
`8 Trends in Static RAMs
`8.1 Overview of SRAMs
`8.2 A brief history of static RAMs by technology
`8.2.1 NMOS SRAMs convert to Mix-MOS (R-load CMOS) SRAMs
`8.2.2 CMOS SRAMs
`8.3 Advantages of CMOS SRAMs
`8.3.1
`low static power dissipation
`8.3.2 High noise immunity
`8.3.3 Low voltage operation
`8.3.4 Cell size in low voltage applications
`8.2.5 Superior temperature characteristics and reliability
`8.3.6 Resistance to alpha particles
`8.4 Disadvantages of CMOS
`8.5 Evolution of high density commodity static RAMs
`8.5.1 Typical 256k byte-wide SRAM
`8.6 Technology evolution of high density SRAMs
`8.6.1 Scaling reduces chip size and improves performance
`8.6.2 Multiple interconnect layers
`·
`8.7 Design and architecture of high density SRAMs
`8.7.1 Stability requirements of the R-load cell
`8.7.2 Protection from hot carrier effects
`8.7.3 Substrate back-bias and grounded P-wells
`8.8 Address transition detection for synchronous internal operation
`8.8.1 Overview
`8.8.2 A TD for bit-line equalization
`8.8.3 ATD pulse generators
`8.8.4 Automatic power-down using address transition detection
`8.8.5 Deselection of array sections
`8.8.6 Sequential activation pulses to distribute power
`8.9 ATD techniques for power reduction during read
`8.9.1 Bit-line equalization technique
`8.9.2 Latched column technique
`8.9.3 Pulsed word-line technique
`·s.10 ATD techniques for power reduction during write
`8.10.1 Va.riable impedance bit-line loads
`8.10.2 Tri-level word-lines
`8.10.3 Data transition detection
`8.11 A pplications of ATD on the !Mb SRAMs
`8.11.1 ATD equalization, precharge and activation on the lMb SRAM
`8.11.2 Auto power-down during read and write on the IMb SRAM
`8.12 Specification for a typical first generation ! M b SRAM
`8.13 The search for improved speed
`8.13.l CMOS as opposed to resistor load cells in fast SRAMs
`8.13.2 Address transition detection for improved speed
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`CONTENTS
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`8.13.3 Short data hold time problems in fast SRAMs using ATD
`8.13.4 Address skew in fast SRAMs using dynamic circuitry
`8.IJ.5 Fast sense amplifiers for high density SRAMs
`8.13.6 Short bit-lines for improved speed
`8.IJ.7 Shortening the delay in the datapath
`8.14 Reducing supply line noise inductance effects
`Bibliography
`
`9 Future, Fast and Application-specific SRAMs
`9.1 Overview
`9.2 4Mb, 16Mb and future SRAMs-an overview
`9.3 Multimegabit cell technology
`9.3.1 Process developments for deep submicron transistors
`9.3.2 Refinement and scaling of planar CMOS cells
`9.3.3 The stacked transistor CMOS cell-poly-load PMOS
`9.3.4 Buried layers and silicon-on-insulator structures (SOI)
`9.3.5 Vertical CMOS transistors
`9.3.6 Combination vertical and stacked transistor technology
`9.4 External power supply level considerations
`9.4.1 Power supply levels on the 4Mb SRAM
`9.4.2 Power supply levels for the 16Mb SRAM and beyond
`9.5 Architecture for 4Mb SRAMs
`9.6 High speed SRAM technologies
`9.6.I Fast bipolar static RAMs
`9.6.2 Sub IO ns MOS and BiCMOS static RAMs
`9.6.3 Sub 10 ns high density BiCMOS technology
`9.6.4 Power consumption limitation of ECL interface circuitry
`9.6.5 Development of ECL 1/0 compatible CMOS interface circuitry
`9.6.6 GaAs and other speciality technology super fast SRAMs
`9.7 Features for improved speed
`9.7.l Separate 110
`9.7.2 Synchronous or self-timed SRAMs (STRAMs)
`9.7.3 Pinouts with mulHple and center power and ground pins
`9.7.4 A typical center-power and ground high speed SRAM
`9.7.5 Flash write feature
`9.8 Wide bus architecture trade-offs
`9.9 Specialty SRAM architectures
`9.9.1 Power-down protection and the battery RAM
`9.9.2 Dual-port RAMs
`9.9.3 FIFOs and line buffers
`9.9.4 Content addressable memories
`9.9.5 Cache TAG RAM
`Bibliography
`
`10 MOS ROMs, PROMs and EPLDs
`10.1 Overview
`10.2 History of ROMs
`10.3 ROM product types
`10.3.1 Customized standard parts
`10.3.2 Custom specials-
`the early character generators
`10.4 Unusual ROM organizations and package selections
`
`417
`417
`418
`420
`422
`423
`426
`
`430
`430
`432
`434
`435
`435
`436
`439
`439
`442
`444
`444
`444
`445
`452
`452
`453
`454
`463
`463
`465
`466
`467
`467
`472
`475
`477
`477
`478
`478
`479
`483
`483
`485
`485
`
`489
`489
`490
`494
`494
`497
`501
`
`Micron Ex. 1014, p. 12
`Micron v. Vervain
`IPR2021-01547
`
`

`

`CONTENTS
`
`I0.5 Production of customized ROMs
`10.5 .1 Customer-manufacturer interface
`10.6 Types of cell programming
`10.6.1 Field oxide programming
`10.6.2 Threshold voltage implant method of programming
`10.6.3 Through-hole contact programming
`I0.7 Different ROM array structures
`10.7.1 Parallel (NOR) array structure
`10.7.2 Serial (NANO) array structure
`10.7.3 Combination parallel-serial array structure
`10.8 Multiple state ROM cells
`10.9 Architectures for fast ROMs
`IO.IO Synchronous ROMs for low standby power
`I0.11 Multimegabit ROMs
`10.11.1 4Mb ROM
`10.11.2 16Mb ROM
`I0.12 Bipolar PROMs
`I0.13 Various semicustom arrays
`10.13.1 Gate arrays
`10.13.2 Erasable programmable logic devices (EPLDs)
`Bibliography
`
`11 Field Alterable ROMs I: EPROM, OTP, and Flash Memories
`11.1 Overview of field alterable ROMs
`11.1.l Field alterable ROM applications
`11.1.2 Field alterabfo ROM characteristics
`11.1.3 History of field alterable ROMs
`11.2 Early NMOS UV EPROM devices l k to IMb
`11.3 CMOS EPROMs and their operation .
`11.3.1 Early CMOS EPROMs
`11.3.2 Data sensing in EPROMs
`11.3.3 Address transition detection in CMOS EPROMs
`11.4 High speed CMOS EPROMs
`11.4.1 ATD for speed
`11.4.2 Double-layer metal strapping for speed
`11.4.3 New transistor structures for speed
`11.5 Programming time and test modes in CMOS EPROMs
`1 I.6 Latch-up protection techniques in CMOS EPROMs
`11.7 High density EPROM organizations and standards
`11.7.1 Byte-wide EPROM organizations and standards
`11.7.2 Word-wide EPROM organizations and standards
`11.8 A typical lMb CMOS EPROM in two organizations
`11.9 Electronic signature mode
`11.10 Multimegabit and future EPROMs
`Innovative cell developments for 4Mb EPROMs
`11.10.1
`11.10.2 An early 4Mb EPROM
`11.10.3 Speed issues on the 4Mb EPROM
`11.10.4 Noise immunity problems in fast 4Mb CMOS EPROMs
`11.11 The early 16Mb CMOS EPROM cell development and devices
`11.12 Application-specific and embedded EPROMs
`11.13 One-time-programmable (OTP) EPROMs
`
`xiii
`
`504
`504
`507
`507
`510
`510
`512
`512
`513
`515
`517
`519
`519
`520
`520
`520
`520
`525
`526
`526
`527
`
`529
`529
`530
`530
`533
`538
`541
`541
`545
`546
`549
`549
`550
`550
`553
`555
`557
`558
`559
`565
`568
`568
`569
`572
`573
`576
`578
`583
`583
`
`Micron Ex. 1014, p. 13
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`IPR2021-01547
`
`

`

`xiv
`
`CONTENTS
`
`11.14 Eledrically flash reprogrammable ROMs
`11.14.1 A short history of Aash memories
`11.14.2 Single-transistor flash memories as an EPROM compatible technology
`11.14.3 Flash memories with split gate single-transistor cells
`11.14.4 A typical lMb Rash memory
`11.14.5 S V only flash memories
`11.14.6 A stacked three-layer polysilicon flash memory cell
`11.14.7 A contactless NANO-structured flash memory cell
`11.14.8 3 V flash memories
`Bibliography
`
`12 Field Alterable ROMs II: EEPROM, EAROM, NV-RAM
`12.1 Overview of electrically erasable PROMs
`12.2 Electrically erasable PROM technology and trends
`12.3 T he MNOS process and trends
`12.4 The floating gate thin oxide process and trends
`12.4.1 Process, operation and reliabi!Hy
`ll.4.2 Early floating gate EEPROM cells and devices
`12.4.3 Early cell trends in floating gate nitride barrier technology
`12.5 Thick oxide process and early cell trends
`12.5.1 Early process development
`12.5.2 Early cell trends in asperity assisted Fowler-Nordheim process
`12.6 Eledrically erasable ROM devices
`12.6.1 Low density EAROM applicaHons and characteristics
`12.6.2 Medium density EEPROM characteristics and applications
`12.6.3 Change from NMOS to CMOS technology
`12.6.4 High speed features on EEPROMs
`12.6.5 Standards for system required features on EEPROMs
`12.6.6 A typical 256k EEPROM with required and optional features
`12.6.7 A typical 256k EEPROM timing diagram
`12. 7 Yield and endurance enhancement special features on EEPROMs
`12.7.1 The SEEQ Q-cell
`12.7.2 A IO million cycle endurance EEPROM design
`12.7.3 Hamming codes lo improve endurance
`12.7.4 Extended temperature
`12.7.S Low operating voltage
`12.8 EEPROM com binations and embedded EEPROMs
`12.9 Some general thoughts on EEPROMs
`12.10 Non-volatile SRAMs
`12.10.1 The NV-SRAM or shadow RAM
`12.10.2 The ferroelectric non-volatile RAM
`12.11 The non-volatile DRAM
`Bibliography
`
`13 Packaging-Single, Module and Wafer Scale Integration
`13.1 Overview
`13.2 Single-chip through-hole packages
`13.2.1 Dual-in-line package (OIL or DIP)
`13.2.2 DIP hermetic
`13.2.3 DIP plastic (PDIP)
`13.2.4 Zigzag-in-line package (ZIP)
`
`586
`586
`587
`589
`594
`598
`600
`603
`604
`605
`
`609
`609
`611
`611
`618
`618
`620
`623
`625
`626
`626
`627
`628
`629
`630
`631
`633
`637
`639
`641
`641
`643
`645
`645
`646
`647
`650
`650
`650
`654
`656
`660
`
`663
`663
`664
`664
`664
`667
`667
`
`Micron Ex. 1014, p. 14
`Micron v. Vervain
`IPR2021-01547
`
`

`

`CONTENTS
`
`13.2.5 Single-in-line package (SIP)
`13.3 Surface mount packages
`13.4 Small outline (SO) surface mount packages
`13.4.1 SOP- SOIC
`13.4.2 SOJ
`13.5 Miniature small outline packages
`13.5.1 Thin small outline package (TSOP)
`13.5.2 Vertical surface mount package (VPAK)
`13.6 Chip carrier surface mount packages
`13.6.1 Flatpack
`13.6.2 Ceramic leadless chip carrier (LCC)
`13.6.3 Plastic leaded chip carrier (PLCQ
`13.7 Multichip modules
`13.7.1 Single-in-line memory modules (SIMMs) for DRAMs
`13.7.2 Modules for high density SRAMs
`13.7.3 Application-specific memories using SIMMs
`13.7.4 Direct and reverse image packages
`13.7.5 Memory intensive modules
`13.8 Bare chip modules
`13.8.1 Conventional hybrids
`13.8.2 Flip-chip on substrate
`13.8.3 Tape-automated bonding (TAB)
`13.8.4 A multilayer module for high performance computers
`13.8.5 High density memory cards
`13.9 Wafer scale integration
`13.9.1 Programmed interconnections-discretionary wiring
`13.9.2 Multichip module with single substrate
`13.9.3 The spiral algorithm technique
`13.9.4 Vertical wafer scale integration
`Bibliography
`
`14 Memory Electrical and Reliability Testing
`14.1 Overview of memory testing
`14.1.l Characterization
`14.1.2 Probe
`14.1.3 Final test
`14.2 Failure modes and test patterns
`14.3 Testing DRAMs and SRAMs
`14.3.1 Fault coverage considerations
`14.3.2 Failure modes
`14.3.3 Voltage bump test for DRAMs
`14.3.4 Addressing considerations when testing a RAM
`14.3.5 Datapolarity
`14.3.6 Dual-port (video) DRAM
`14.3.7 DRAM test modes
`14.3.8 Self-testing of DRAMs
`14.3.9 SRAM test modes
`14.4 EPROMs
`14.4.l Common problems and failure modes in EPROMs
`14.4.2 Programming of EPROMs
`14.4.3 UV erase
`14.4.4 Test time for an EPROM
`14.4.5 Failure mechanisms for an EPROM
`
`xv
`
`670
`671
`672
`674
`674
`675
`675
`676
`676
`677
`677
`677
`678
`678
`679
`679
`682
`682
`684
`684
`684
`689
`690
`690
`690
`691
`692
`694
`695
`695
`
`697
`697
`698
`698
`699
`700
`705
`705
`707
`708
`709
`709
`709
`711
`713
`716
`716
`716
`718
`718
`719
`719
`
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`IPR2021-01547
`
`

`

`xvi
`
`CONTENTS
`
`14.5 Standard EPROM programming methods
`14.5.1 Single bit programming
`14.5.2 Byte programming algorithm
`14.5.3 16 bit programming algorithm
`14.5.4 32 bit page programming algorithm
`14.5.5 EPROM on-chip test modes
`14.6 OTP test considerations
`14.7 Statistical test analysis
`14.7.1 Average outgoing quality (AOQ)
`14.7.2 Standard deviaHon from the mean (sigma)
`14.8 Reliability and quality
`14.9 Reliability considerations
`14.9.1 General reliability
`14.9.2 Reliability tests and test conditions
`14.9.3 Failure rate calculations
`14.9.4 Mean lime between failures
`14.10 General reliability failure mechanisms
`14.10.1 Hot electron effects in MOS transistors
`14.10.2 Electromigration of metal interconnects
`14.10.3 Soft errors
`14.10.4 Latch-up susceptibility
`14.10.5 Electrostatic discharge (ESD)
`14.11 Noise sources in dynamic RAMs
`14.11.l Sense amplifier noise
`14.11.2 Array noise
`14.11.3 External noise
`14.11.4 A bit-line model of DRAM noise
`14.12 Reliability of EPROMs and EEPROMs
`14.13 Failure analysis
`14.14 Package reliability
`14.15 Memory test and burn-in equipment
`Bibliography
`
`15 Yield, Cost and the Modern Factory
`15.1 Overview
`15.2 Yield theory
`15.3 Yield ·enhancement
`15.3.1 Redundancy
`15.3.2 Redundancy and speed considerations
`15.3.3 Redundancy and power considerations
`15.3.4 Methods of replacing redundant elements
`15.4 Error correction
`15.4.1 Error correction theory
`15.4.2 Error correction on ROMs
`15.4 .. 3 Error correction on DRAMs
`15.5 Combination redundancy and error correction
`15.6 Yield improvement over time in a typical memorr. wafer fabrication line
`15.7 A simple cost analysis of a wafer processing line
`15.8 Trends in the modem memory factory
`15.8.1 The traditional 'clean room factory'
`15.8.2 A new concept in dean processing
`Bibliography
`
`721
`721
`721
`721
`721
`725
`728
`729
`729
`729
`731
`732
`732
`733
`735
`737
`737
`737
`738
`738
`742
`743
`743
`743
`745
`745
`745
`745
`748
`751
`751
`751
`
`755
`755
`755
`756
`757
`761
`761
`762
`764
`765
`767
`768
`772
`773
`774
`778
`778
`781
`784
`
`Micron Ex. 1014, p. 16
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`IPR2021-01547
`
`

`

`CONTENTS
`
`16 Memory Trends in the Future
`16.1 Future applications
`16.2 Marketing trends
`16.3 Memory systems
`16.4 Memory products
`16.4.1 DRAMs
`16.4.2 SRAMs
`16.4.J Non-volatiles
`16.5 Packag ing
`16.6 Memory process technology
`16.7 Memory manufacturing technology
`
`Index
`
`xvii
`
`786
`786
`787
`787
`788
`788
`788
`789
`789
`790
`790
`
`791
`
`Micron Ex. 1014, p. 17
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`IPR2021-01547
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`

`

`5 BASIC MEMORY
`ARCHITECTURE AND CELL
`STRUCTURE
`
`5.1
`
`INTRODUCTION
`
`Another possible set of classifications of semiconductor data storage devices is related
`to the basic architecture and cell structure of the memory circuit as shown in Table 5.1.
`Static memory gates store their data in latches, while dynamic memory gates store
`their data on capacitors. The static memory cell has a non-destructive readout and
`retains its memory under the application of de power. The one-transistor dynamic
`cell has a destructive readout. All DRAM cells lose their data without the application
`of a periodic refresh.
`Both dynamic and static RAMs are called volatile since they lose their data when
`the power is turned off. Another class of memory cells is called non-volatile since the
`data requires no refresh and is retained even when all power is off. This class of
`non-volatile memories, which includes the ROMs, EPROMs, and EEPROMs, stores
`data in preprogrammed storage cells.
`All of the devices mentioned so far have random access read capability and those
`that are writable have random access write. Memory devices that have only serial
`read and write capability are called Serial Access Memories (SAMs) and may be
`dynamic or static, volatile or non-volatile.
`
`5.2 BASIC MEMORY ARCHITECTURE
`
`The basic memory architecture has the configuration shown in Figure 5.l(a). This
`potentially includes: inputs, outputs, addresses, read control, write control and data
`storage. The three major divisions of memories are RAMs, ROMs, and SAMs. These
`subsets of this basic architecture are shown in 5. I(b), (c), and (d).
`The basic RAM (random access memory), shown in Figure 5.I(b), is a memory in
`which any storage location can be randomly accessed for Read and Write by inputting
`
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`

`150
`
`BASIC MEMORY ARCHITECTURE AND CELL STRUCTURE
`
`Table 5.1
`
`Data storage
`Volatile
`Destructive
`read
`Access
`
`SRAM
`
`DRAM
`
`(E)EPROM
`
`SAM
`
`latch
`yes
`no
`
`capacitor
`yes
`yes/no
`
`programmed
`no
`no
`
`xx
`yes
`xx
`
`Random
`
`Random
`
`Random
`
`Serial
`
`the coordinates of that bit on the address pins. It usually combines the Read (R) and
`Write (W) control pins into a single Write Enable (WE) control pin whose two states
`determine Read or Write.
`The basic ROM (read-only memory), shown in 5.l(c), is a hardware preprogrammed
`memory in which any storage !~cation can be randomly accessed for Read by inputting
`the coordinates of that bit on the address pins. The Data inputs and Write control
`pins are missing and the Read control pin usually becomes a Chip Select or Chip
`Enable (CS/CE) control pin.
`
`I (inputs)
`------
`
`I - D (data)
`~-------
`
`R,W .... WE
`(write enable)
`
`A (addresses)1
`I
`I
`I
`I
`I
`I
`I
`
`R (read)
`
`W (write)
`
`A
`
`0 (outputs)
`
`(a)
`
`------
`o-a (parallel outputs)
`( b)
`
`I (Serial input)
`
`A
`
`R-cs
`(control)
`
`0 -a (parallel outputs)
`( c)
`
`0 ( seria I output)
`
`{d)
`
`Figure 5.1
`Schematics of memory configurations. (a) Basic memory, (b) RAM, (c) ROM, (d) SAM.
`(From Salters [50] 1989, with permission of Philips Research.)
`
`Micron Ex. 1014, p. 19
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`
`

`

`BASIC MEMORY ARCHITEC